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drm/amd/pm: Adjust si_upload_smc_data register programming (v3)

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[ Upstream commit ce025130127437dc884c84c254170e27b2ce9309 ]

Based on some comments in dm_pp_display_configuration
above the crtc_index and line_time fields, these values
are programmed to the SMC to work around an SMC hang
when it switches MCLK.

According to Alex, the Windows driver programs them to:
mclk_change_block_cp_min = 200 / line_time
mclk_change_block_cp_max = 100 / line_time
Let's use the same for the sake of consistency.

Previously we used the watermark values, but it seemed buggy
as the code was mixing up low/high and A/B watermarks, and
was not saving a low watermark value on DCE 6, so
mclk_change_block_cp_max would be always zero previously.

Split this change off from the previous si_upload_smc_data
to make it easier to bisect, in case it causes any issues.

Fixes: 841686df9f ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Timur Kristóf 2025-08-28 17:11:07 +02:00 committed by Greg Kroah-Hartman
parent 82963fb4ec
commit 1ebcf6f1e5
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
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@ -5813,8 +5813,8 @@ static int si_upload_smc_data(struct amdgpu_device *adev)
crtc_index = amdgpu_crtc->crtc_id;
if (amdgpu_crtc->line_time) {
mclk_change_block_cp_min = amdgpu_crtc->wm_high / amdgpu_crtc->line_time;
mclk_change_block_cp_max = amdgpu_crtc->wm_low / amdgpu_crtc->line_time;
mclk_change_block_cp_min = 200 / amdgpu_crtc->line_time;
mclk_change_block_cp_max = 100 / amdgpu_crtc->line_time;
}
}