MIRRORS/linux-yocto
1
0
Fork 0
mirror of git://git.yoctoproject.org/linux-yocto.git synced 2025-10-22 23:13:01 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

GVT Changes:

Browse Source 
- gvt-next stuff mostly with refactor for the new MDEV interface.
 
 i915 Changes:
 - PSR fixes and improvements (Jouni)
 - DP DSC fixes (Vinod, Jouni)
 - More general display cleanups (Jani)
 - More display collor management cleanup targetting degamma (Ville)
 - remove circ_buf.h includes (Jiri)
 - wait power off delay at driver remove to optimize probe (Jani)
 - More audio cleanup targeting the ELD precompute readout (Ville)
 - Enable DC power states on all eDP ports (Imre)
 - RPL-P stepping info (Matt Atwood)
 - MTL enabling patches (RK)
 - Removal of DG2 force_probe (Matt)
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmN3+28ACgkQ+mJfZA7r
 E8rGZQf9HiTNW1yM1/YGq7ezD6/XN2sbCaH/iVNd0+FHxz4HHaTJaEVQ1xEBTdIb
 poMQiWl64ig3t2LuDrRGwlsVmFYV3vK5byt758sMpLb/M3cWbbB2swsW4YTbORM6
 qcatv9eYyuoiylwj6fVLFPMXpwNTyCdbngbLZt+tTcl1oxaZYp0PVXBkzlKFP02U
 KL4p+Dv4OHSjP38beIzUaHz3IJJAik/ttsxa1JhhC8F9UUJs7kuo6GXMY1OzRNpc
 jKj3+F0OtDRA2xaw7YpbLI8yt+pWzerqFsnZDAvvx8Js7SQLkyNtjkuHusp8OP77
 x99MlyOfbSfBnkbdm4Rhm7IIPTiUnw==
 =SHn9
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-next-2022-11-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

GVT Changes:
- gvt-next stuff mostly with refactor for the new MDEV interface.

i915 Changes:
- PSR fixes and improvements (Jouni)
- DP DSC fixes (Vinod, Jouni)
- More general display cleanups (Jani)
- More display collor management cleanup targetting degamma (Ville)
- remove circ_buf.h includes (Jiri)
- wait power off delay at driver remove to optimize probe (Jani)
- More audio cleanup targeting the ELD precompute readout (Ville)
- Enable DC power states on all eDP ports (Imre)
- RPL-P stepping info (Matt Atwood)
- MTL enabling patches (RK)
- Removal of DG2 force_probe (Matt)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y3f71obyEkImXoUF@intel.com
This commit is contained in:
Dave Airlie 2022-11-23 08:03:07 +10:00
commit 3d335a523b
122 changed files with 1173 additions and 749 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/i915/Makefile
View File

@ -248,6 +248,7 @@ i915-y += \
display/intel_global_state.o \
display/intel_hdcp.o \
display/intel_hotplug.o \
display/intel_hti.o \
display/intel_lpe_audio.o \
display/intel_modeset_verify.o \
display/intel_modeset_setup.o \

1
drivers/gpu/drm/i915/display/g4x_dp.c
View File

@ -8,6 +8,7 @@
#include <linux/string_helpers.h>
#include "g4x_dp.h"
#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_backlight.h"
#include "intel_connector.h"

2
drivers/gpu/drm/i915/display/g4x_dp.h
View File

@ -8,7 +8,7 @@
#include <linux/types.h>
#include "i915_reg.h"
#include "i915_reg_defs.h"
enum pipe;
enum port;

15
drivers/gpu/drm/i915/display/g4x_hdmi.c
View File

@ -6,6 +6,7 @@
*/
#include "g4x_hdmi.h"
#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_crtc.h"
@ -78,6 +79,18 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
return ret;
}
static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
if (HAS_PCH_SPLIT(i915))
crtc_state->has_pch_encoder = true;
return intel_hdmi_compute_config(encoder, crtc_state, conn_state);
}
static void intel_hdmi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@ -543,7 +556,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
"HDMI %c", port_name(port));
intel_encoder->hotplug = intel_hdmi_hotplug;
intel_encoder->compute_config = intel_hdmi_compute_config;
intel_encoder->compute_config = g4x_hdmi_compute_config;
if (HAS_PCH_SPLIT(dev_priv)) {
intel_encoder->disable = pch_disable_hdmi;
intel_encoder->post_disable = pch_post_disable_hdmi;

4
drivers/gpu/drm/i915/display/i9xx_plane.c
View File

@ -8,6 +8,9 @@
#include <drm/drm_blend.h>
#include <drm/drm_fourcc.h>
#include "i915_irq.h"
#include "i915_reg.h"
#include "i9xx_plane.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_de.h"
@ -15,7 +18,6 @@
#include "intel_fb.h"
#include "intel_fbc.h"
#include "intel_sprite.h"
#include "i9xx_plane.h"
/* Primary plane formats for gen <= 3 */
static const u32 i8xx_primary_formats[] = {

1
drivers/gpu/drm/i915/display/icl_dsi.c
View File

@ -29,6 +29,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_mipi_dsi.h>
#include "i915_reg.h"
#include "icl_dsi.h"
#include "icl_dsi_regs.h"
#include "intel_atomic.h"

2
drivers/gpu/drm/i915/display/icl_dsi_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __ICL_DSI_REGS_H__
#define __ICL_DSI_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
/* Gen11 DSI */
#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \

6
drivers/gpu/drm/i915/display/intel_atomic_plane.c
View File

@ -757,7 +757,7 @@ void intel_plane_update_noarm(struct intel_plane *plane,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_plane_update_noarm(&plane->base, crtc);
trace_intel_plane_update_noarm(plane, crtc);
if (plane->update_noarm)
plane->update_noarm(plane, crtc_state, plane_state);
@ -769,7 +769,7 @@ void intel_plane_update_arm(struct intel_plane *plane,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_plane_update_arm(&plane->base, crtc);
trace_intel_plane_update_arm(plane, crtc);
if (crtc_state->do_async_flip && plane->async_flip)
plane->async_flip(plane, crtc_state, plane_state, true);
@ -782,7 +782,7 @@ void intel_plane_disable_arm(struct intel_plane *plane,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_plane_disable_arm(&plane->base, crtc);
trace_intel_plane_disable_arm(plane, crtc);
plane->disable_arm(plane, crtc_state);
}

28
drivers/gpu/drm/i915/display/intel_audio.c
View File

@ -838,8 +838,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (i915->display.funcs.audio)
i915->display.funcs.audio->audio_codec_enable(encoder,
crtc_state,
conn_state);
crtc_state,
conn_state);
mutex_lock(&i915->display.audio.mutex);
encoder->audio_connector = connector;
@ -854,7 +854,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
pipe = -1;
acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
(int) port, (int) pipe);
(int)port, (int)pipe);
}
intel_lpe_audio_notify(i915, pipe, port, connector->eld,
@ -891,8 +891,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
if (i915->display.funcs.audio)
i915->display.funcs.audio->audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
old_crtc_state,
old_conn_state);
mutex_lock(&i915->display.audio.mutex);
encoder->audio_connector = NULL;
@ -905,7 +905,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
pipe = -1;
acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
(int) port, (int) pipe);
(int)port, (int)pipe);
}
intel_lpe_audio_notify(i915, pipe, port, NULL, 0, false);
@ -1129,10 +1129,10 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev)
static struct intel_encoder *get_saved_enc(struct drm_i915_private *i915,
int port, int pipe)
{
struct intel_encoder *encoder;
/* MST */
if (pipe >= 0) {
struct intel_encoder *encoder;
if (drm_WARN_ON(&i915->drm,
pipe >= ARRAY_SIZE(i915->display.audio.encoder_map)))
return NULL;
@ -1143,7 +1143,7 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *i915,
* MST or not. So it will poll all the port & pipe
* combinations
*/
if (encoder != NULL && encoder->port == port &&
if (encoder && encoder->port == port &&
encoder->type == INTEL_OUTPUT_DP_MST)
return encoder;
}
@ -1153,14 +1153,12 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *i915,
return NULL;
for_each_pipe(i915, pipe) {
struct intel_encoder *encoder;
encoder = i915->display.audio.encoder_map[pipe];
if (encoder == NULL)
continue;
if (encoder->type == INTEL_OUTPUT_DP_MST)
continue;
if (port == encoder->port)
if (encoder && encoder->port == port &&
encoder->type != INTEL_OUTPUT_DP_MST)
return encoder;
}

2
drivers/gpu/drm/i915/display/intel_audio_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __INTEL_AUDIO_REGS_H__
#define __INTEL_AUDIO_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
#define G4X_ELD_VALID REG_BIT(14)

1
drivers/gpu/drm/i915/display/intel_backlight.c
View File

@ -10,6 +10,7 @@
#include <acpi/video.h>
#include "i915_reg.h"
#include "intel_backlight.h"
#include "intel_backlight_regs.h"
#include "intel_connector.h"

2
drivers/gpu/drm/i915/display/intel_backlight_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __INTEL_BACKLIGHT_REGS_H__
#define __INTEL_BACKLIGHT_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)

3
drivers/gpu/drm/i915/display/intel_bw.c
View File

@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
return ret;
}
if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)
if (DISPLAY_VER(dev_priv) < 14 &&
(dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
num_channels *= 2;
qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);

3
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -24,6 +24,7 @@
#include <linux/time.h>
#include "hsw_ips.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_audio.h"
@ -2755,7 +2756,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
if (intel_crtc_needs_modeset(crtc_state))
pipe = INVALID_PIPE;
}

594
drivers/gpu/drm/i915/display/intel_color.c
View File

File diff suppressed because it is too large Load Diff

1
drivers/gpu/drm/i915/display/intel_combo_phy.c
View File

@ -3,6 +3,7 @@
* Copyright © 2018 Intel Corporation
*/
#include "i915_reg.h"
#include "intel_combo_phy.h"
#include "intel_combo_phy_regs.h"
#include "intel_de.h"

2
drivers/gpu/drm/i915/display/intel_connector.h
View File

@ -6,7 +6,7 @@
#ifndef __INTEL_CONNECTOR_H__
#define __INTEL_CONNECTOR_H__
#include "intel_display.h"
#include <linux/types.h>
struct drm_connector;
struct edid;

2
drivers/gpu/drm/i915/display/intel_crt.c
View File

@ -34,6 +34,8 @@
#include <drm/drm_probe_helper.h>
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_crt.h"
#include "intel_crtc.h"

3
drivers/gpu/drm/i915/display/intel_cursor.c
View File

@ -10,12 +10,13 @@
#include <drm/drm_damage_helper.h>
#include <drm/drm_fourcc.h>
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_cursor.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_fb_pin.h"
#include "intel_frontbuffer.h"

102
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -31,6 +31,7 @@
#include <drm/drm_privacy_screen_consumer.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_audio_regs.h"
#include "intel_backlight.h"
@ -56,6 +57,7 @@
#include "intel_hdcp.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
#include "intel_hti.h"
#include "intel_lspcon.h"
#include "intel_mg_phy_regs.h"
#include "intel_pps.h"
@ -846,22 +848,65 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
}
static enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
{
/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
/*
* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
* DC states enabled at the same time, while for driver initiated AUX
* transfers we need the same AUX IOs to be powered but with DC states
* disabled. Accordingly use the AUX power domain here which leaves DC
* states enabled.
* However, for non-A AUX ports the corresponding non-EDP transcoders
* would have already enabled power well 2 and DC_OFF. This means we can
* acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
* specific AUX_IO reference without powering up any extra wells.
* Note that PSR is enabled only on Port A even though this function
* returns the correct domain for other ports too.
* disabled. Accordingly use the AUX_IO_<port> power domain here which
* leaves DC states enabled.
*
* Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
* AUX IO to be enabled, but all these require DC_OFF to be enabled as
* well, so we can acquire a wider AUX_<port> power domain reference
* instead of a specific AUX_IO_<port> reference without powering up any
* extra wells.
*/
return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
intel_aux_power_domain(dig_port);
if (intel_encoder_can_psr(&dig_port->base))
return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
else if (DISPLAY_VER(i915) < 14 &&
(intel_crtc_has_dp_encoder(crtc_state) ||
intel_phy_is_tc(i915, phy)))
return intel_aux_power_domain(dig_port);
else
return POWER_DOMAIN_INVALID;
}
static void
main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum intel_display_power_domain domain =
intel_ddi_main_link_aux_domain(dig_port, crtc_state);
drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
if (domain == POWER_DOMAIN_INVALID)
return;
dig_port->aux_wakeref = intel_display_power_get(i915, domain);
}
static void
main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum intel_display_power_domain domain =
intel_ddi_main_link_aux_domain(dig_port, crtc_state);
intel_wakeref_t wf;
wf = fetch_and_zero(&dig_port->aux_wakeref);
if (!wf)
return;
intel_display_power_put(i915, domain, wf);
}
static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
@ -869,7 +914,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
/*
* TODO: Add support for MST encoders. Atm, the following should never
@ -888,17 +932,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
dig_port->ddi_io_power_domain);
}
/*
* AUX power is only needed for (e)DP mode, and for HDMI mode on TC
* ports.
*/
if (intel_crtc_has_dp_encoder(crtc_state) ||
intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
dig_port->aux_wakeref =
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
}
main_link_aux_power_domain_get(dig_port, crtc_state);
}
void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@ -2737,10 +2771,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
old_conn_state);
if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
intel_display_power_put(dev_priv,
intel_ddi_main_link_aux_domain(dig_port),
fetch_and_zero(&dig_port->aux_wakeref));
main_link_aux_power_domain_put(dig_port, old_crtc_state);
if (is_tc_port)
intel_tc_port_put_link(dig_port);
@ -3061,12 +3092,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
if (is_tc_port)
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
dig_port->aux_wakeref =
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
}
main_link_aux_power_domain_get(dig_port, crtc_state);
if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
/*
@ -4113,12 +4139,6 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
return max_lanes;
}
static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
{
return i915->hti_state & HDPORT_ENABLED &&
i915->hti_state & HDPORT_DDI_USED(phy);
}
static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@ -4247,7 +4267,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
* driver. In that case we should skip initializing the corresponding
* outputs.
*/
if (hti_uses_phy(dev_priv, phy)) {
if (intel_hti_uses_phy(dev_priv, phy)) {
drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
port_name(port), phy_name(phy));
return;

39
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -76,6 +76,7 @@
#include "g4x_hdmi.h"
#include "hsw_ips.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
#include "icl_dsi.h"
#include "intel_acpi.h"
@ -90,6 +91,7 @@
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dp_link_training.h"
#include "intel_dpio_phy.h"
#include "intel_dpt.h"
#include "intel_dsb.h"
#include "intel_fbc.h"
@ -99,6 +101,7 @@
#include "intel_frontbuffer.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
#include "intel_hti.h"
#include "intel_modeset_verify.h"
#include "intel_modeset_setup.h"
#include "intel_overlay.h"
@ -888,7 +891,7 @@ static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
{
struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx;
struct drm_atomic_state *state;
int ret;
@ -944,13 +947,13 @@ void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
return;
}
dev_priv->modeset_restore_state = state;
dev_priv->display.restore.modeset_state = state;
state->acquire_ctx = ctx;
}
void intel_display_finish_reset(struct drm_i915_private *i915)
{
struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx;
struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx;
struct drm_atomic_state *state;
int ret;
@ -961,7 +964,7 @@ void intel_display_finish_reset(struct drm_i915_private *i915)
if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
return;
state = fetch_and_zero(&i915->modeset_restore_state);
state = fetch_and_zero(&i915->display.restore.modeset_state);
if (!state)
goto unlock;
@ -2441,7 +2444,7 @@ int intel_display_suspend(struct drm_device *dev)
drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
ret);
else
dev_priv->modeset_restore_state = state;
dev_priv->display.restore.modeset_state = state;
return ret;
}
@ -4048,20 +4051,19 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display_power_domain_set power_domain_set = { };
bool active;
u32 tmp;
if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
POWER_DOMAIN_PIPE(crtc->pipe)))
return false;
pipe_config->shared_dpll = NULL;
active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
drm_WARN_ON(&dev_priv->drm, active);
active = true;
}
@ -4120,7 +4122,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->ips_linetime =
REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
if (DISPLAY_VER(dev_priv) >= 9)
skl_get_pfit_config(pipe_config);
@ -4151,7 +4153,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
out:
intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
return active;
}
@ -5930,7 +5932,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
return PTR_ERR(crtc_state);
if (!crtc_state->hw.active ||
drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
intel_crtc_needs_modeset(crtc_state))
continue;
drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
@ -8569,7 +8571,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
struct drm_mode_config *mode_config = &i915->drm.mode_config;
drm_mode_config_init(&i915->drm);
INIT_LIST_HEAD(&i915->global_obj_list);
INIT_LIST_HEAD(&i915->display.global.obj_list);
mode_config->min_width = 0;
mode_config->min_height = 0;
@ -8734,12 +8736,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
if (i915->display.cdclk.max_cdclk_freq == 0)
intel_update_max_cdclk(i915);
/*
* If the platform has HTI, we need to find out whether it has reserved
* any display resources before we create our display outputs.
*/
if (INTEL_INFO(i915)->display.has_hti)
i915->hti_state = intel_de_read(i915, HDPORT_STATE);
intel_hti_init(i915);
/* Just disable it once at startup */
intel_vga_disable(i915);
@ -8902,14 +8899,14 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
void intel_display_resume(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
struct drm_atomic_state *state = i915->modeset_restore_state;
struct drm_atomic_state *state = i915->display.restore.modeset_state;
struct drm_modeset_acquire_ctx ctx;
int ret;
if (!HAS_DISPLAY(i915))
return;
i915->modeset_restore_state = NULL;
i915->display.restore.modeset_state = NULL;
if (state)
state->acquire_ctx = &ctx;

39
drivers/gpu/drm/i915/display/intel_display.h
View File

@ -53,6 +53,7 @@ struct intel_digital_port;
struct intel_dp;
struct intel_encoder;
struct intel_initial_plane_config;
struct intel_link_m_n;
struct intel_load_detect_pipe;
struct intel_plane;
struct intel_plane_state;
@ -61,24 +62,6 @@ struct intel_remapped_info;
struct intel_rotation_info;
struct pci_dev;
enum i915_gpio {
GPIOA,
GPIOB,
GPIOC,
GPIOD,
GPIOE,
GPIOF,
GPIOG,
GPIOH,
__GPIOI_UNUSED,
GPIOJ,
GPIOK,
GPIOL,
GPIOM,
GPION,
GPIOO,
};
/*
* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
* rest have consecutive values and match the enum values of transcoders
@ -279,17 +262,6 @@ enum tc_port_mode {
TC_PORT_LEGACY,
};
enum dpio_channel {
DPIO_CH0,
DPIO_CH1
};
enum dpio_phy {
DPIO_PHY0,
DPIO_PHY1,
DPIO_PHY2,
};
enum aux_ch {
AUX_CH_A,
AUX_CH_B,
@ -316,15 +288,6 @@ enum aux_ch {
#define aux_ch_name(a) ((a) + 'A')
/* Used by dp and fdi links */
struct intel_link_m_n {
u32 tu;
u32 data_m;
u32 data_n;
u32 link_m;
u32 link_n;
};
enum phy {
PHY_NONE = -1,

21
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -14,6 +14,7 @@
#include <linux/workqueue.h>
#include <drm/drm_connector.h>
#include <drm/drm_modeset_lock.h>
#include "intel_cdclk.h"
#include "intel_display.h"
@ -344,6 +345,10 @@ struct intel_display {
u32 rx_config;
} fdi;
struct {
struct list_head obj_list;
} global;
struct {
/*
* Base address of where the gmbus and gpio blocks are located
@ -370,6 +375,16 @@ struct intel_display {
struct mutex comp_mutex;
} hdcp;
struct {
/*
* HTI (aka HDPORT) state read during initial hw readout. Most
* platforms don't have HTI, so this will just stay 0. Those
* that do will use this later to figure out which PLLs and PHYs
* are unavailable for driver usage.
*/
u32 state;
} hti;
struct {
struct i915_power_domains domains;
@ -396,6 +411,12 @@ struct intel_display {
unsigned long mask;
} quirks;
struct {
/* restore state for suspend/resume and display reset */
struct drm_atomic_state *modeset_state;
struct drm_modeset_acquire_ctx reset_ctx;
} restore;
struct {
enum {
I915_SAGV_UNKNOWN = 0,

2
drivers/gpu/drm/i915/display/intel_display_debugfs.c
View File

@ -9,6 +9,8 @@
#include <drm/drm_fourcc.h>
#include "i915_debugfs.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_debugfs.h"
#include "intel_display_power.h"

42
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -129,6 +129,18 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUDIO_MMIO";
case POWER_DOMAIN_AUDIO_PLAYBACK:
return "AUDIO_PLAYBACK";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_IO_B:
return "AUX_IO_B";
case POWER_DOMAIN_AUX_IO_C:
return "AUX_IO_C";
case POWER_DOMAIN_AUX_IO_D:
return "AUX_IO_D";
case POWER_DOMAIN_AUX_IO_E:
return "AUX_IO_E";
case POWER_DOMAIN_AUX_IO_F:
return "AUX_IO_F";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@ -153,8 +165,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_USBC5";
case POWER_DOMAIN_AUX_USBC6:
return "AUX_USBC6";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT1:
return "AUX_TBT1";
case POWER_DOMAIN_AUX_TBT2:
@ -2289,6 +2299,7 @@ struct intel_ddi_port_domains {
enum intel_display_power_domain ddi_lanes;
enum intel_display_power_domain ddi_io;
enum intel_display_power_domain aux_io;
enum intel_display_power_domain aux_legacy_usbc;
enum intel_display_power_domain aux_tbt;
};
@ -2303,6 +2314,7 @@ i9xx_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
.aux_io = POWER_DOMAIN_AUX_IO_A,
.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
.aux_tbt = POWER_DOMAIN_INVALID,
},
@ -2318,6 +2330,7 @@ d11_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
.aux_io = POWER_DOMAIN_AUX_IO_A,
.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
.aux_tbt = POWER_DOMAIN_INVALID,
}, {
@ -2328,6 +2341,7 @@ d11_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
.aux_io = POWER_DOMAIN_AUX_IO_C,
.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
.aux_tbt = POWER_DOMAIN_AUX_TBT1,
},
@ -2343,6 +2357,7 @@ d12_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
.aux_io = POWER_DOMAIN_AUX_IO_A,
.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
.aux_tbt = POWER_DOMAIN_INVALID,
}, {
@ -2353,6 +2368,7 @@ d12_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
.aux_io = POWER_DOMAIN_INVALID,
.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
.aux_tbt = POWER_DOMAIN_AUX_TBT1,
},
@ -2368,6 +2384,7 @@ d13_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
.aux_io = POWER_DOMAIN_AUX_IO_A,
.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
.aux_tbt = POWER_DOMAIN_INVALID,
}, {
@ -2378,6 +2395,7 @@ d13_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
.aux_io = POWER_DOMAIN_INVALID,
.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
.aux_tbt = POWER_DOMAIN_AUX_TBT1,
}, {
@ -2388,6 +2406,7 @@ d13_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
.aux_io = POWER_DOMAIN_AUX_IO_D,
.aux_legacy_usbc = POWER_DOMAIN_AUX_D,
.aux_tbt = POWER_DOMAIN_INVALID,
},
@ -2433,7 +2452,7 @@ intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
{
const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_io == POWER_DOMAIN_INVALID)
if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_PORT_DDI_IO_A;
return domains->ddi_io + (int)(port - domains->port_start);
@ -2444,7 +2463,7 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
{
const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_lanes == POWER_DOMAIN_INVALID)
if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_PORT_DDI_LANES_A;
return domains->ddi_lanes + (int)(port - domains->port_start);
@ -2465,12 +2484,23 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
return NULL;
}
enum intel_display_power_domain
intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
{
const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_AUX_IO_A;
return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
}
enum intel_display_power_domain
intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
{
const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)
if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_AUX_A;
return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
@ -2481,7 +2511,7 @@ intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch au
{
const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_tbt == POWER_DOMAIN_INVALID)
if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
return POWER_DOMAIN_AUX_TBT1;
return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);

15
drivers/gpu/drm/i915/display/intel_display_power.h
View File

@ -6,11 +6,12 @@
#ifndef __INTEL_DISPLAY_POWER_H__
#define __INTEL_DISPLAY_POWER_H__
#include "intel_runtime_pm.h"
#include "intel_wakeref.h"
enum aux_ch;
enum dpio_channel;
enum dpio_phy;
enum i915_drm_suspend_mode;
enum port;
struct drm_i915_private;
struct i915_power_well;
@ -76,6 +77,14 @@ enum intel_display_power_domain {
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_IO_D,
POWER_DOMAIN_AUX_IO_E,
POWER_DOMAIN_AUX_IO_F,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
@ -90,8 +99,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
@ -249,6 +256,8 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
enum intel_display_power_domain
intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
enum intel_display_power_domain
intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
enum intel_display_power_domain
intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
enum intel_display_power_domain
intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);

69
drivers/gpu/drm/i915/display/intel_display_power_map.c
View File

@ -170,6 +170,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_GMBUS,
@ -179,6 +181,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
POWER_DOMAIN_PORT_DDI_LANES_B,
POWER_DOMAIN_PORT_DDI_LANES_C,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
@ -186,6 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
POWER_DOMAIN_PORT_DDI_LANES_B,
POWER_DOMAIN_PORT_DDI_LANES_C,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
@ -243,6 +249,9 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_IO_D,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
@ -252,12 +261,15 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
POWER_DOMAIN_PORT_DDI_LANES_B,
POWER_DOMAIN_PORT_DDI_LANES_C,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
POWER_DOMAIN_PORT_DDI_LANES_D,
POWER_DOMAIN_AUX_IO_D,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_INIT);
@ -305,6 +317,9 @@ static const struct i915_power_well_desc_list chv_power_wells[] = {
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_MMIO, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_IO_B, \
POWER_DOMAIN_AUX_IO_C, \
POWER_DOMAIN_AUX_IO_D, \
POWER_DOMAIN_AUX_B, \
POWER_DOMAIN_AUX_C, \
POWER_DOMAIN_AUX_D
@ -318,6 +333,7 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
@ -407,6 +423,8 @@ static const struct i915_power_well_desc_list skl_power_wells[] = {
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_MMIO, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_IO_B, \
POWER_DOMAIN_AUX_IO_C, \
POWER_DOMAIN_AUX_B, \
POWER_DOMAIN_AUX_C
@ -420,16 +438,20 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
POWER_DOMAIN_PORT_DDI_LANES_A,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
POWER_DOMAIN_PORT_DDI_LANES_B,
POWER_DOMAIN_PORT_DDI_LANES_C,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
@ -483,6 +505,8 @@ static const struct i915_power_well_desc_list bxt_power_wells[] = {
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_MMIO, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_IO_B, \
POWER_DOMAIN_AUX_IO_C, \
POWER_DOMAIN_AUX_B, \
POWER_DOMAIN_AUX_C
@ -496,6 +520,7 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
@ -504,29 +529,34 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
POWER_DOMAIN_PORT_DDI_LANES_A,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
POWER_DOMAIN_PORT_DDI_LANES_B,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
POWER_DOMAIN_PORT_DDI_LANES_C,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
@ -617,6 +647,11 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_MMIO, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_IO_B, \
POWER_DOMAIN_AUX_IO_C, \
POWER_DOMAIN_AUX_IO_D, \
POWER_DOMAIN_AUX_IO_E, \
POWER_DOMAIN_AUX_IO_F, \
POWER_DOMAIN_AUX_B, \
POWER_DOMAIN_AUX_C, \
POWER_DOMAIN_AUX_D, \
@ -658,13 +693,23 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_IO_A);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_A);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
POWER_DOMAIN_AUX_IO_B,
POWER_DOMAIN_AUX_B);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
POWER_DOMAIN_AUX_IO_C,
POWER_DOMAIN_AUX_C);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
POWER_DOMAIN_AUX_IO_D,
POWER_DOMAIN_AUX_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
POWER_DOMAIN_AUX_IO_E,
POWER_DOMAIN_AUX_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
POWER_DOMAIN_AUX_IO_F,
POWER_DOMAIN_AUX_F);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
@ -816,6 +861,7 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
@ -1012,6 +1058,7 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
static const struct i915_power_well_desc rkl_power_wells_main[] = {
@ -1094,6 +1141,7 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
@ -1215,6 +1263,9 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
POWER_DOMAIN_PORT_DDI_LANES_TC4, \
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_IO_C, \
POWER_DOMAIN_AUX_IO_D, \
POWER_DOMAIN_AUX_IO_E, \
POWER_DOMAIN_AUX_C, \
POWER_DOMAIN_AUX_D, \
POWER_DOMAIN_AUX_E, \
@ -1255,6 +1306,7 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
static const struct i915_power_well_desc xelpd_power_wells_main[] = {
@ -1376,6 +1428,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,

2
drivers/gpu/drm/i915/display/intel_display_power_well.h
View File

@ -7,8 +7,8 @@
#include <linux/types.h>
#include "intel_display.h"
#include "intel_display_power.h"
#include "intel_dpio_phy.h"
struct drm_i915_private;
struct i915_power_well;

53
drivers/gpu/drm/i915/display/intel_display_reg_defs.h Normal file
View File

@ -0,0 +1,53 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_DISPLAY_REG_DEFS_H__
#define __INTEL_DISPLAY_REG_DEFS_H__
#include "i915_reg_defs.h"
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
#define VLV_DISPLAY_BASE 0x180000
/*
* Named helper wrappers around _PICK_EVEN() and _PICK().
*/
#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
/*
* Device info offset array based helpers for groups of registers with unevenly
* spaced base offsets.
*/
#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */

206
drivers/gpu/drm/i915/display/intel_display_trace.h
View File

@ -18,11 +18,15 @@
#include "intel_crtc.h"
#include "intel_display_types.h"
#define __dev_name_i915(i915) dev_name((i915)->drm.dev)
#define __dev_name_kms(obj) dev_name((obj)->base.dev->dev)
TRACE_EVENT(intel_pipe_enable,
TP_PROTO(struct intel_crtc *crtc),
TP_ARGS(crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__array(u32, frame, 3)
__array(u32, scanline, 3)
__field(enum pipe, pipe)
@ -30,6 +34,7 @@ TRACE_EVENT(intel_pipe_enable,
TP_fast_assign(
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *it__;
__assign_str(dev, __dev_name_kms(crtc));
for_each_intel_crtc(&dev_priv->drm, it__) {
__entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
__entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__);
@ -37,8 +42,8 @@ TRACE_EVENT(intel_pipe_enable,
__entry->pipe = crtc->pipe;
),
TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
pipe_name(__entry->pipe),
TP_printk("dev %s, pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame[PIPE_A], __entry->scanline[PIPE_A],
__entry->frame[PIPE_B], __entry->scanline[PIPE_B],
__entry->frame[PIPE_C], __entry->scanline[PIPE_C])
@ -49,6 +54,7 @@ TRACE_EVENT(intel_pipe_disable,
TP_ARGS(crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__array(u32, frame, 3)
__array(u32, scanline, 3)
__field(enum pipe, pipe)
@ -57,6 +63,7 @@ TRACE_EVENT(intel_pipe_disable,
TP_fast_assign(
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *it__;
__assign_str(dev, __dev_name_kms(crtc));
for_each_intel_crtc(&dev_priv->drm, it__) {
__entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
__entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__);
@ -64,8 +71,8 @@ TRACE_EVENT(intel_pipe_disable,
__entry->pipe = crtc->pipe;
),
TP_printk("pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
pipe_name(__entry->pipe),
TP_printk("dev %s, pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame[PIPE_A], __entry->scanline[PIPE_A],
__entry->frame[PIPE_B], __entry->scanline[PIPE_B],
__entry->frame[PIPE_C], __entry->scanline[PIPE_C])
@ -76,6 +83,7 @@ TRACE_EVENT(intel_pipe_crc,
TP_ARGS(crtc, crcs),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -83,16 +91,19 @@ TRACE_EVENT(intel_pipe_crc,
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
memcpy(__entry->crcs, crcs, sizeof(__entry->crcs));
),
TP_printk("pipe %c, frame=%u, scanline=%u crc=%08x %08x %08x %08x %08x",
pipe_name(__entry->pipe), __entry->frame, __entry->scanline,
__entry->crcs[0], __entry->crcs[1], __entry->crcs[2],
__entry->crcs[3], __entry->crcs[4])
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u crc=%08x %08x %08x %08x %08x",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
__entry->crcs[0], __entry->crcs[1],
__entry->crcs[2], __entry->crcs[3],
__entry->crcs[4])
);
TRACE_EVENT(intel_cpu_fifo_underrun,
@ -100,6 +111,7 @@ TRACE_EVENT(intel_cpu_fifo_underrun,
TP_ARGS(dev_priv, pipe),
TP_STRUCT__entry(
__string(dev, __dev_name_i915(dev_priv))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -107,13 +119,14 @@ TRACE_EVENT(intel_cpu_fifo_underrun,
TP_fast_assign(
struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe),
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline)
);
@ -122,6 +135,7 @@ TRACE_EVENT(intel_pch_fifo_underrun,
TP_ARGS(dev_priv, pch_transcoder),
TP_STRUCT__entry(
__string(dev, __dev_name_i915(dev_priv))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -130,13 +144,14 @@ TRACE_EVENT(intel_pch_fifo_underrun,
TP_fast_assign(
enum pipe pipe = pch_transcoder;
struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
__assign_str(dev, __dev_name_i915(dev_priv));
__entry->pipe = pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pch transcoder %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe),
TP_printk("dev %s, pch transcoder %c, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline)
);
@ -145,6 +160,7 @@ TRACE_EVENT(intel_memory_cxsr,
TP_ARGS(dev_priv, old, new),
TP_STRUCT__entry(
__string(dev, __dev_name_i915(dev_priv))
__array(u32, frame, 3)
__array(u32, scanline, 3)
__field(bool, old)
@ -153,6 +169,7 @@ TRACE_EVENT(intel_memory_cxsr,
TP_fast_assign(
struct intel_crtc *crtc;
__assign_str(dev, __dev_name_i915(dev_priv));
for_each_intel_crtc(&dev_priv->drm, crtc) {
__entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc);
__entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc);
@ -161,8 +178,8 @@ TRACE_EVENT(intel_memory_cxsr,
__entry->new = new;
),
TP_printk("%s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
str_on_off(__entry->old), str_on_off(__entry->new),
TP_printk("dev %s, cxsr %s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
__get_str(dev), str_on_off(__entry->old), str_on_off(__entry->new),
__entry->frame[PIPE_A], __entry->scanline[PIPE_A],
__entry->frame[PIPE_B], __entry->scanline[PIPE_B],
__entry->frame[PIPE_C], __entry->scanline[PIPE_C])
@ -173,6 +190,7 @@ TRACE_EVENT(g4x_wm,
TP_ARGS(crtc, wm),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -191,6 +209,7 @@ TRACE_EVENT(g4x_wm,
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
@ -208,8 +227,9 @@ TRACE_EVENT(g4x_wm,
__entry->fbc = wm->fbc_en;
),
TP_printk("pipe %c, frame=%u, scanline=%u, wm %d/%d/%d, sr %s/%d/%d/%d, hpll %s/%d/%d/%d, fbc %s",
pipe_name(__entry->pipe), __entry->frame, __entry->scanline,
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, wm %d/%d/%d, sr %s/%d/%d/%d, hpll %s/%d/%d/%d, fbc %s",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
__entry->primary, __entry->sprite, __entry->cursor,
str_yes_no(__entry->cxsr), __entry->sr_plane, __entry->sr_cursor, __entry->sr_fbc,
str_yes_no(__entry->hpll), __entry->hpll_plane, __entry->hpll_cursor, __entry->hpll_fbc,
@ -221,6 +241,7 @@ TRACE_EVENT(vlv_wm,
TP_ARGS(crtc, wm),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -235,6 +256,7 @@ TRACE_EVENT(vlv_wm,
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
@ -248,9 +270,10 @@ TRACE_EVENT(vlv_wm,
__entry->sr_cursor = wm->sr.cursor;
),
TP_printk("pipe %c, frame=%u, scanline=%u, level=%d, cxsr=%d, wm %d/%d/%d/%d, sr %d/%d",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline, __entry->level, __entry->cxsr,
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, level=%d, cxsr=%d, wm %d/%d/%d/%d, sr %d/%d",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
__entry->level, __entry->cxsr,
__entry->primary, __entry->sprite0, __entry->sprite1, __entry->cursor,
__entry->sr_plane, __entry->sr_cursor)
);
@ -260,6 +283,7 @@ TRACE_EVENT(vlv_fifo_size,
TP_ARGS(crtc, sprite0_start, sprite1_start, fifo_size),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -269,6 +293,7 @@ TRACE_EVENT(vlv_fifo_size,
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
@ -277,90 +302,96 @@ TRACE_EVENT(vlv_fifo_size,
__entry->fifo_size = fifo_size;
),
TP_printk("pipe %c, frame=%u, scanline=%u, %d/%d/%d",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline, __entry->sprite0_start,
__entry->sprite1_start, __entry->fifo_size)
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, %d/%d/%d",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
__entry->sprite0_start, __entry->sprite1_start, __entry->fifo_size)
);
TRACE_EVENT(intel_plane_update_noarm,
TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc),
TP_ARGS(plane, crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(plane))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
__array(int, src, 4)
__array(int, dst, 4)
__string(name, plane->name)
__string(name, plane->base.name)
),
TP_fast_assign(
__assign_str(name, plane->name);
__assign_str(dev, __dev_name_kms(plane));
__assign_str(name, plane->base.name);
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst));
memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src));
memcpy(__entry->dst, &plane->base.state->dst, sizeof(__entry->dst));
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
pipe_name(__entry->pipe), __get_str(name),
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline,
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
);
TRACE_EVENT(intel_plane_update_arm,
TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc),
TP_ARGS(plane, crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(plane))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
__array(int, src, 4)
__array(int, dst, 4)
__string(name, plane->name)
__string(name, plane->base.name)
),
TP_fast_assign(
__assign_str(name, plane->name);
__assign_str(dev, __dev_name_kms(plane));
__assign_str(name, plane->base.name);
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst));
memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src));
memcpy(__entry->dst, &plane->base.state->dst, sizeof(__entry->dst));
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
pipe_name(__entry->pipe), __get_str(name),
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline,
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
);
TRACE_EVENT(intel_plane_disable_arm,
TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc),
TP_ARGS(plane, crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(plane))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
__string(name, plane->name)
__string(name, plane->base.name)
),
TP_fast_assign(
__assign_str(name, plane->name);
__assign_str(dev, __dev_name_kms(plane));
__assign_str(name, plane->base.name);
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __get_str(name),
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline)
);
@ -369,6 +400,8 @@ TRACE_EVENT(intel_fbc_activate,
TP_ARGS(plane),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(plane))
__string(name, plane->base.name)
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -377,13 +410,16 @@ TRACE_EVENT(intel_fbc_activate,
TP_fast_assign(
struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev),
plane->pipe);
__assign_str(dev, __dev_name_kms(plane));
__assign_str(name, plane->base.name)
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->frame, __entry->scanline)
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline)
);
TRACE_EVENT(intel_fbc_deactivate,
@ -391,6 +427,8 @@ TRACE_EVENT(intel_fbc_deactivate,
TP_ARGS(plane),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(plane))
__string(name, plane->base.name)
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -399,13 +437,16 @@ TRACE_EVENT(intel_fbc_deactivate,
TP_fast_assign(
struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev),
plane->pipe);
__assign_str(dev, __dev_name_kms(plane));
__assign_str(name, plane->base.name)
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->frame, __entry->scanline)
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline)
);
TRACE_EVENT(intel_fbc_nuke,
@ -413,6 +454,8 @@ TRACE_EVENT(intel_fbc_nuke,
TP_ARGS(plane),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(plane))
__string(name, plane->base.name)
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -421,13 +464,16 @@ TRACE_EVENT(intel_fbc_nuke,
TP_fast_assign(
struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev),
plane->pipe);
__assign_str(dev, __dev_name_kms(plane));
__assign_str(name, plane->base.name)
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->frame, __entry->scanline)
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline)
);
TRACE_EVENT(intel_crtc_vblank_work_start,
@ -435,20 +481,22 @@ TRACE_EVENT(intel_crtc_vblank_work_start,
TP_ARGS(crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline)
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline)
);
TRACE_EVENT(intel_crtc_vblank_work_end,
@ -456,20 +504,22 @@ TRACE_EVENT(intel_crtc_vblank_work_end,
TP_ARGS(crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline)
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline)
);
TRACE_EVENT(intel_pipe_update_start,
@ -477,6 +527,7 @@ TRACE_EVENT(intel_pipe_update_start,
TP_ARGS(crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -485,6 +536,7 @@ TRACE_EVENT(intel_pipe_update_start,
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
@ -492,9 +544,10 @@ TRACE_EVENT(intel_pipe_update_start,
__entry->max = crtc->debug.max_vbl;
),
TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline, __entry->min, __entry->max)
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
__entry->min, __entry->max)
);
TRACE_EVENT(intel_pipe_update_vblank_evaded,
@ -502,6 +555,7 @@ TRACE_EVENT(intel_pipe_update_vblank_evaded,
TP_ARGS(crtc),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
@ -510,6 +564,7 @@ TRACE_EVENT(intel_pipe_update_vblank_evaded,
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = crtc->debug.start_vbl_count;
__entry->scanline = crtc->debug.scanline_start;
@ -517,9 +572,10 @@ TRACE_EVENT(intel_pipe_update_vblank_evaded,
__entry->max = crtc->debug.max_vbl;
),
TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline, __entry->min, __entry->max)
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
__entry->min, __entry->max)
);
TRACE_EVENT(intel_pipe_update_end,
@ -527,56 +583,64 @@ TRACE_EVENT(intel_pipe_update_end,
TP_ARGS(crtc, frame, scanline_end),
TP_STRUCT__entry(
__string(dev, __dev_name_kms(crtc))
__field(enum pipe, pipe)
__field(u32, frame)
__field(u32, scanline)
),
TP_fast_assign(
__assign_str(dev, __dev_name_kms(crtc));
__entry->pipe = crtc->pipe;
__entry->frame = frame;
__entry->scanline = scanline_end;
),
TP_printk("pipe %c, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->frame,
__entry->scanline)
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
__get_str(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline)
);
TRACE_EVENT(intel_frontbuffer_invalidate,
TP_PROTO(unsigned int frontbuffer_bits, unsigned int origin),
TP_ARGS(frontbuffer_bits, origin),
TP_PROTO(struct drm_i915_private *i915,
unsigned int frontbuffer_bits, unsigned int origin),
TP_ARGS(i915, frontbuffer_bits, origin),
TP_STRUCT__entry(
__string(dev, __dev_name_i915(i915))
__field(unsigned int, frontbuffer_bits)
__field(unsigned int, origin)
),
TP_fast_assign(
__assign_str(dev, __dev_name_i915(i915));
__entry->frontbuffer_bits = frontbuffer_bits;
__entry->origin = origin;
),
TP_printk("frontbuffer_bits=0x%08x, origin=%u",
__entry->frontbuffer_bits, __entry->origin)
TP_printk("dev %s, frontbuffer_bits=0x%08x, origin=%u",
__get_str(dev), __entry->frontbuffer_bits, __entry->origin)
);
TRACE_EVENT(intel_frontbuffer_flush,
TP_PROTO(unsigned int frontbuffer_bits, unsigned int origin),
TP_ARGS(frontbuffer_bits, origin),
TP_PROTO(struct drm_i915_private *i915,
unsigned int frontbuffer_bits, unsigned int origin),
TP_ARGS(i915, frontbuffer_bits, origin),
TP_STRUCT__entry(
__string(dev, __dev_name_i915(i915))
__field(unsigned int, frontbuffer_bits)
__field(unsigned int, origin)
),
TP_fast_assign(
__assign_str(dev, __dev_name_i915(i915));
__entry->frontbuffer_bits = frontbuffer_bits;
__entry->origin = origin;
),
TP_printk("frontbuffer_bits=0x%08x, origin=%u",
__entry->frontbuffer_bits, __entry->origin)
TP_printk("dev %s, frontbuffer_bits=0x%08x, origin=%u",
__get_str(dev), __entry->frontbuffer_bits, __entry->origin)
);
#endif /* __INTEL_DISPLAY_TRACE_H__ */

55
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -969,6 +969,15 @@ struct intel_mpllb_state {
u32 mpllb_sscstep;
};
/* Used by dp and fdi links */
struct intel_link_m_n {
u32 tu;
u32 data_m;
u32 data_n;
u32 link_m;
u32 link_n;
};
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@ -1366,6 +1375,7 @@ struct intel_crtc {
u16 vmax_vblank_start;
struct intel_display_power_domain_set enabled_power_domains;
struct intel_display_power_domain_set hw_readout_power_domains;
struct intel_overlay *overlay;
struct intel_crtc_state *config;
@ -1803,51 +1813,6 @@ struct intel_dp_mst_encoder {
struct intel_connector *connector;
};
static inline enum dpio_channel
vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
{
switch (dig_port->base.port) {
default:
MISSING_CASE(dig_port->base.port);
fallthrough;
case PORT_B:
case PORT_D:
return DPIO_CH0;
case PORT_C:
return DPIO_CH1;
}
}
static inline enum dpio_phy
vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
{
switch (dig_port->base.port) {
default:
MISSING_CASE(dig_port->base.port);
fallthrough;
case PORT_B:
case PORT_C:
return DPIO_PHY0;
case PORT_D:
return DPIO_PHY1;
}
}
static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)
{
switch (pipe) {
default:
MISSING_CASE(pipe);
fallthrough;
case PIPE_A:
case PIPE_C:
return DPIO_CH0;
case PIPE_B:
return DPIO_CH1;
}
}
struct intel_load_detect_pipe {
struct drm_atomic_state *restore_state;
};

7
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -46,6 +46,7 @@
#include "g4x_dp.h"
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_backlight.h"
@ -4876,6 +4877,12 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
intel_pps_vdd_off_sync(intel_dp);
/*
* Ensure power off delay is respected on module remove, so that we can
* reduce delays at driver probe. See pps_init_timestamps().
*/
intel_pps_wait_power_cycle(intel_dp);
intel_dp_aux_fini(intel_dp);
}

1
drivers/gpu/drm/i915/display/intel_dp_aux.c
View File

@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_display_types.h"
#include "intel_dp_aux.h"

1
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
View File

@ -11,6 +11,7 @@
#include <drm/display/drm_hdcp_helper.h>
#include <drm/drm_print.h>
#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_types.h"

1
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -29,6 +29,7 @@
#include <drm/drm_probe_helper.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"

43
drivers/gpu/drm/i915/display/intel_dpio_phy.c
View File

@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
@ -655,6 +656,48 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
return mask;
}
enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
{
switch (dig_port->base.port) {
default:
MISSING_CASE(dig_port->base.port);
fallthrough;
case PORT_B:
case PORT_D:
return DPIO_CH0;
case PORT_C:
return DPIO_CH1;
}
}
enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
{
switch (dig_port->base.port) {
default:
MISSING_CASE(dig_port->base.port);
fallthrough;
case PORT_B:
case PORT_C:
return DPIO_PHY0;
case PORT_D:
return DPIO_PHY1;
}
}
enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
{
switch (pipe) {
default:
MISSING_CASE(pipe);
fallthrough;
case PIPE_A:
case PIPE_C:
return DPIO_CH0;
case PIPE_B:
return DPIO_CH1;
}
}
void chv_set_phy_signal_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 deemph_reg_value, u32 margin_reg_value,

19
drivers/gpu/drm/i915/display/intel_dpio_phy.h
View File

@ -8,13 +8,24 @@
#include <linux/types.h>
enum dpio_channel;
enum dpio_phy;
enum pipe;
enum port;
struct drm_i915_private;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_encoder;
enum dpio_channel {
DPIO_CH0,
DPIO_CH1,
};
enum dpio_phy {
DPIO_PHY0,
DPIO_PHY1,
DPIO_PHY2,
};
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
@ -30,6 +41,10 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
u8 lane_lat_optim_mask);
u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
enum dpio_channel vlv_pipe_to_channel(enum pipe pipe);
void chv_set_phy_signal_level(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 deemph_reg_value, u32 margin_reg_value,

2
drivers/gpu/drm/i915/display/intel_dpll.c
View File

@ -6,10 +6,12 @@
#include <linux/kernel.h>
#include <linux/string_helpers.h>
#include "i915_reg.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_lvds.h"
#include "intel_panel.h"

12
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
View File

@ -23,6 +23,7 @@
#include <linux/string_helpers.h>
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dkl_phy.h"
@ -30,6 +31,7 @@
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_dpll_mgr.h"
#include "intel_hti.h"
#include "intel_mg_phy_regs.h"
#include "intel_pch_refclk.h"
#include "intel_tc.h"
@ -3163,14 +3165,6 @@ static void icl_update_active_dpll(struct intel_atomic_state *state,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
}
static u32 intel_get_hti_plls(struct drm_i915_private *i915)
{
if (!(i915->hti_state & HDPORT_ENABLED))
return 0;
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
}
static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@ -3245,7 +3239,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
}
/* Eliminate DPLLs from consideration if reserved by HTI */
dpll_mask &= ~intel_get_hti_plls(dev_priv);
dpll_mask &= ~intel_hti_dpll_mask(dev_priv);
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,

1
drivers/gpu/drm/i915/display/intel_drrs.c
View File

@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_de.h"
#include "intel_display_types.h"

1
drivers/gpu/drm/i915/display/intel_dsb.c
View File

@ -7,6 +7,7 @@
#include "gem/i915_gem_internal.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dsb.h"

1
drivers/gpu/drm/i915/display/intel_dvo.c
View File

@ -32,6 +32,7 @@
#include <drm/drm_crtc.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_de.h"
#include "intel_display_types.h"

8
drivers/gpu/drm/i915/display/intel_dvo_dev.h
View File

@ -23,12 +23,12 @@
#ifndef __INTEL_DVO_DEV_H__
#define __INTEL_DVO_DEV_H__
#include <linux/i2c.h>
#include <drm/drm_crtc.h>
#include "i915_reg_defs.h"
enum drm_connector_status;
struct drm_display_mode;
struct i2c_adapter;
struct intel_dvo_device {
const char *name;
int type;

2
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@ -1183,7 +1183,7 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
if (intel_crtc_needs_modeset(new_crtc_state))
return false;
if (!intel_fbc_is_ok(old_plane_state) ||

1
drivers/gpu/drm/i915/display/intel_fdi.c
View File

@ -5,6 +5,7 @@
#include <linux/string_helpers.h>
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_ddi.h"

3
drivers/gpu/drm/i915/display/intel_fifo_underrun.h
View File

@ -8,9 +8,8 @@
#include <linux/types.h>
#include "intel_display.h"
struct drm_i915_private;
enum pipe;
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
enum pipe pipe, bool enable);

4
drivers/gpu/drm/i915/display/intel_frontbuffer.c
View File

@ -88,7 +88,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
if (!frontbuffer_bits)
return;
trace_intel_frontbuffer_flush(frontbuffer_bits, origin);
trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin);
might_sleep();
intel_drrs_flush(i915, frontbuffer_bits);
@ -176,7 +176,7 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
spin_unlock(&i915->display.fb_tracking.lock);
}
trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
trace_intel_frontbuffer_invalidate(i915, frontbuffer_bits, origin);
might_sleep();
intel_psr_invalidate(i915, frontbuffer_bits, origin);

4
drivers/gpu/drm/i915/display/intel_global_state.c
View File

@ -45,14 +45,14 @@ void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv,
obj->state = state;
obj->funcs = funcs;
list_add_tail(&obj->head, &dev_priv->global_obj_list);
list_add_tail(&obj->head, &dev_priv->display.global.obj_list);
}
void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv)
{
struct intel_global_obj *obj, *next;
list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) {
list_for_each_entry_safe(obj, next, &dev_priv->display.global.obj_list, head) {
list_del(&obj->head);
drm_WARN_ON(&dev_priv->drm, kref_read(&obj->state->ref) != 1);

2
drivers/gpu/drm/i915/display/intel_global_state.h
View File

@ -27,7 +27,7 @@ struct intel_global_obj {
};
#define intel_for_each_global_obj(obj, dev_priv) \
list_for_each_entry(obj, &(dev_priv)->global_obj_list, head)
list_for_each_entry(obj, &(dev_priv)->display.global.obj_list, head)
#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
for ((__i) = 0; \

22
drivers/gpu/drm/i915/display/intel_gmbus.c
View File

@ -34,6 +34,8 @@
#include <drm/display/drm_hdcp_helper.h>
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_gmbus.h"
@ -49,9 +51,27 @@ struct intel_gmbus {
struct drm_i915_private *i915;
};
enum gmbus_gpio {
GPIOA,
GPIOB,
GPIOC,
GPIOD,
GPIOE,
GPIOF,
GPIOG,
GPIOH,
__GPIOI_UNUSED,
GPIOJ,
GPIOK,
GPIOL,
GPIOM,
GPION,
GPIOO,
};
struct gmbus_pin {
const char *name;
enum i915_gpio gpio;
enum gmbus_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */

2
drivers/gpu/drm/i915/display/intel_hdcp_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __INTEL_HDCP_REGS_H__
#define __INTEL_HDCP_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
/* HDCP Key Registers */
#define HDCP_KEY_CONF _MMIO(0x66c00)

33
drivers/gpu/drm/i915/display/intel_hdmi.c
View File

@ -42,6 +42,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_ddi.h"
@ -2057,13 +2058,6 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc
if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
return false;
/*
* HDMI deep color affects the clocks, so it's only possible
* when not cloning with other encoder types.
*/
if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
return false;
/* Display Wa_1405510057:icl,ehl */
if (intel_hdmi_is_ycbcr420(crtc_state) &&
bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
@ -2190,9 +2184,13 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
}
static enum intel_output_format
intel_hdmi_output_format(struct intel_connector *connector,
intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
struct intel_connector *connector,
bool ycbcr_420_output)
{
if (!crtc_state->has_hdmi_sink)
return INTEL_OUTPUT_FORMAT_RGB;
if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
return INTEL_OUTPUT_FORMAT_YCBCR420;
else
@ -2211,7 +2209,8 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
int ret;
crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
crtc_state->output_format =
intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
drm_dbg_kms(&i915->drm,
@ -2226,13 +2225,19 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
crtc_state->output_format = intel_hdmi_output_format(connector, true);
crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
}
return ret;
}
static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
{
return crtc_state->uapi.encoder_mask &&
!is_power_of_2(crtc_state->uapi.encoder_mask);
}
int intel_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@ -2248,8 +2253,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
return -EINVAL;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
conn_state);
pipe_config->has_hdmi_sink =
intel_has_hdmi_sink(intel_hdmi, conn_state) &&
!intel_hdmi_is_cloned(pipe_config);
if (pipe_config->has_hdmi_sink)
pipe_config->has_infoframe = true;
@ -2257,9 +2263,6 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
pipe_config->pixel_multiplier = 2;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
pipe_config->has_pch_encoder = true;
pipe_config->has_audio =
intel_hdmi_has_audio(encoder, pipe_config, conn_state);

8
drivers/gpu/drm/i915/display/intel_hdmi.h
View File

@ -6,20 +6,20 @@
#ifndef __INTEL_HDMI_H__
#define __INTEL_HDMI_H__
#include <linux/hdmi.h>
#include <linux/types.h>
enum hdmi_infoframe_type;
enum port;
struct drm_connector;
struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_encoder;
struct intel_crtc_state;
struct intel_hdmi;
struct drm_connector_state;
union hdmi_infoframe;
enum port;
void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector);

38
drivers/gpu/drm/i915/display/intel_hti.c Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: MIT
/*
* Copyright © 2022 Intel Corporation
*/
#include "i915_drv.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_hti.h"
#include "intel_hti_regs.h"
void intel_hti_init(struct drm_i915_private *i915)
{
/*
* If the platform has HTI, we need to find out whether it has reserved
* any display resources before we create our display outputs.
*/
if (INTEL_INFO(i915)->display.has_hti)
i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
}
bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
{
return i915->display.hti.state & HDPORT_ENABLED &&
i915->display.hti.state & HDPORT_DDI_USED(phy);
}
u32 intel_hti_dpll_mask(struct drm_i915_private *i915)
{
if (!(i915->display.hti.state & HDPORT_ENABLED))
return 0;
/*
* Note: This is subtle. The values must coincide with what's defined
* for the platform.
*/
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state);
}

18
drivers/gpu/drm/i915/display/intel_hti.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_HTI_H__
#define __INTEL_HTI_H__
#include <linux/types.h>
struct drm_i915_private;
enum phy;
void intel_hti_init(struct drm_i915_private *i915);
bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy);
u32 intel_hti_dpll_mask(struct drm_i915_private *i915);
#endif /* __INTEL_HTI_H__ */

16
drivers/gpu/drm/i915/display/intel_hti_regs.h Normal file
View File

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __INTEL_HTI_REGS_H__
#define __INTEL_HTI_REGS_H__
#include "i915_reg_defs.h"
#define HDPORT_STATE _MMIO(0x45050)
#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
#define HDPORT_ENABLED REG_BIT(0)
#endif /* __INTEL_HTI_REGS_H__ */

2
drivers/gpu/drm/i915/display/intel_lpe_audio.c
View File

@ -71,6 +71,8 @@
#include <drm/intel_lpe_audio.h>
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_lpe_audio.h"
#include "intel_pci_config.h"

1
drivers/gpu/drm/i915/display/intel_lspcon.c
View File

@ -28,6 +28,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"

1
drivers/gpu/drm/i915/display/intel_lvds.c
View File

@ -39,6 +39,7 @@
#include <drm/drm_edid.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_backlight.h"
#include "intel_connector.h"

2
drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __INTEL_MG_PHY_REGS__
#define __INTEL_MG_PHY_REGS__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

1
drivers/gpu/drm/i915/display/intel_modeset_setup.c
View File

@ -10,6 +10,7 @@
#include <drm/drm_atomic_state_helper.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_bw.h"
#include "intel_color.h"

1
drivers/gpu/drm/i915/display/intel_panel.c
View File

@ -31,6 +31,7 @@
#include <linux/kernel.h>
#include <linux/pwm.h>
#include "i915_reg.h"
#include "intel_backlight.h"
#include "intel_connector.h"
#include "intel_de.h"

1
drivers/gpu/drm/i915/display/intel_pch_display.c
View File

@ -4,6 +4,7 @@
*/
#include "g4x_dp.h"
#include "i915_reg.h"
#include "intel_crt.h"
#include "intel_de.h"
#include "intel_display_types.h"

1
drivers/gpu/drm/i915/display/intel_pch_refclk.c
View File

@ -3,6 +3,7 @@
* Copyright © 2021 Intel Corporation
*/
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_panel.h"

3
drivers/gpu/drm/i915/display/intel_pipe_crc.c
View File

@ -24,11 +24,12 @@
*
*/
#include <linux/circ_buf.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_de.h"
#include "intel_display_types.h"

10
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -5,10 +5,12 @@
#include "g4x_dp.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_lvds.h"
#include "intel_pps.h"
@ -1098,7 +1100,13 @@ bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
static void pps_init_timestamps(struct intel_dp *intel_dp)
{
intel_dp->pps.panel_power_off_time = ktime_get_boottime();
/*
* Initialize panel power off time to 0, assuming panel power could have
* been toggled between kernel boot and now only by a previously loaded
* and removed i915, which has already ensured sufficient power off
* delay at module remove.
*/
intel_dp->pps.panel_power_off_time = 0;
intel_dp->pps.last_power_on = jiffies;
intel_dp->pps.last_backlight_off = jiffies;
}

21
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -27,6 +27,7 @@
#include "display/intel_dp.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_de.h"
@ -779,6 +780,7 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
u16 y_granularity = 0;
@ -809,6 +811,10 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
if (y_granularity == 0 || crtc_vdisplay % y_granularity)
return false;
if (crtc_state->dsc.compression_enable &&
vdsc_cfg->slice_height % y_granularity)
return false;
crtc_state->su_y_granularity = y_granularity;
return true;
}
@ -1470,7 +1476,8 @@ unlock:
static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
{
return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 :
PSR2_MAN_TRK_CTL_ENABLE;
}
static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
@ -1482,14 +1489,14 @@ static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_pr
static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
{
return IS_ALDERLAKE_P(dev_priv) ?
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
}
static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
{
return IS_ALDERLAKE_P(dev_priv) ?
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
}
@ -1678,9 +1685,6 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
if (pipe_clip->y2 % y_alignment)
pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
}
/*
@ -2209,8 +2213,11 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_sel_fetch_enabled) {
u32 val;
if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
/* Send one update otherwise lag is observed in screen */
intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
return;
}
val = man_trk_ctl_enable_bit_get(dev_priv) |
man_trk_ctl_partial_frame_bit_get(dev_priv) |

1
drivers/gpu/drm/i915/display/intel_sdvo.c
View File

@ -37,6 +37,7 @@
#include <drm/drm_edid.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_crtc.h"

1
drivers/gpu/drm/i915/display/intel_snps_phy.c
View File

@ -5,6 +5,7 @@
#include <linux/util_macros.h>
#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"

2
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __INTEL_SNPS_PHY_REGS__
#define __INTEL_SNPS_PHY_REGS__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define _SNPS_PHY_A_BASE 0x168000
#define _SNPS_PHY_B_BASE 0x169000

1
drivers/gpu/drm/i915/display/intel_sprite.c
View File

@ -42,6 +42,7 @@
#include <drm/drm_rect.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_vgpu.h"
#include "i9xx_plane.h"
#include "intel_atomic_plane.h"

9
drivers/gpu/drm/i915/display/intel_sprite.h
View File

@ -8,14 +8,13 @@
#include <linux/types.h>
#include "intel_display.h"
struct drm_device;
struct drm_display_mode;
struct drm_file;
struct drm_i915_private;
struct intel_crtc_state;
struct intel_plane_state;
enum pipe;
/*
* FIXME: We should instead only take spinlocks once for the entire update
@ -34,12 +33,6 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
static inline u8 icl_hdr_plane_mask(void)
{
return BIT(PLANE_PRIMARY) |
BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
}
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

2
drivers/gpu/drm/i915/display/intel_tv.c
View File

@ -35,6 +35,8 @@
#include <drm/drm_edid.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_irq.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_de.h"

1
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -10,6 +10,7 @@
#include <drm/display/drm_dsc_helper.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"

1
drivers/gpu/drm/i915/display/intel_vga.c
View File

@ -10,6 +10,7 @@
#include <video/vga.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_vga.h"

1
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -5,6 +5,7 @@
*/
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_vrr.h"

2
drivers/gpu/drm/i915/display/skl_scaler.c
View File

@ -2,6 +2,8 @@
/*
* Copyright © 2020 Intel Corporation
*/
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_fb.h"

7
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -9,6 +9,8 @@
#include <drm/drm_fourcc.h>
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_atomic_plane.h"
#include "intel_de.h"
#include "intel_display_types.h"
@ -246,6 +248,11 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
}
u8 icl_hdr_plane_mask(void)
{
return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
}
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
{
return DISPLAY_VER(dev_priv) >= 11 &&

1
drivers/gpu/drm/i915/display/skl_universal_plane.h
View File

@ -30,6 +30,7 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
enum plane_id plane_id);
u8 icl_hdr_plane_mask(void);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
#endif

2
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -2744,7 +2744,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
* power well the hardware state will go out of sync
* with the software state.
*/
if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
if (!intel_crtc_needs_modeset(new_crtc_state) &&
skl_plane_selected_wm_equals(plane,
&old_crtc_state->wm.skl.optimal,
&new_crtc_state->wm.skl.optimal))

1
drivers/gpu/drm/i915/display/vlv_dsi.c
View File

@ -31,6 +31,7 @@
#include <drm/drm_mipi_dsi.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_backlight.h"
#include "intel_connector.h"

2
drivers/gpu/drm/i915/display/vlv_dsi_regs.h
View File

@ -6,7 +6,7 @@
#ifndef __VLV_DSI_REGS_H__
#define __VLV_DSI_REGS_H__
#include "i915_reg_defs.h"
#include "intel_display_reg_defs.h"
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000

1
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
View File

@ -30,6 +30,7 @@
#include "i915_gem_context.h"
#include "i915_gem_evict.h"
#include "i915_gem_ioctls.h"
#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"

1
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
View File

@ -17,6 +17,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_migrate.h"
#include "i915_reg.h"
#include "i915_ttm_buddy_manager.h"
#include "huge_gem_object.h"

2
drivers/gpu/drm/i915/gt/intel_engine_cs.c
View File

@ -13,6 +13,8 @@
#include "i915_cmd_parser.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_engine.h"

1
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
View File

@ -110,6 +110,7 @@
#include <linux/string_helpers.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "gen8_engine_cs.h"

1
drivers/gpu/drm/i915/gt/intel_gt.c
View File

@ -12,6 +12,7 @@
#include "i915_drv.h"
#include "i915_perf_oa_regs.h"
#include "i915_reg.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
#include "intel_engine_regs.h"

1
drivers/gpu/drm/i915/gt/intel_gt_pm.c
View File

@ -7,6 +7,7 @@
#include <linux/suspend.h>
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_params.h"
#include "intel_context.h"
#include "intel_engine_pm.h"

1
drivers/gpu/drm/i915/gt/intel_gt_regs.h
View File

@ -7,6 +7,7 @@
#define __INTEL_GT_REGS__
#include "i915_reg_defs.h"
#include "display/intel_display_reg_defs.h" /* VLV_DISPLAY_BASE */
#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })

1
drivers/gpu/drm/i915/gt/intel_gtt.c
View File

@ -12,6 +12,7 @@
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_utils.h"
#include "intel_gt.h"

2
drivers/gpu/drm/i915/gt/intel_ring_submission.c
View File

@ -12,7 +12,9 @@
#include "gen6_ppgtt.h"
#include "gen7_renderclear.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_mitigations.h"
#include "i915_reg.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_engine_regs.h"

1
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
#include "intel_engine_regs.h"

1
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
View File

@ -30,6 +30,7 @@
#include "intel_guc_submission.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_trace.h"
/**

2
drivers/gpu/drm/i915/gvt/cfg_space.c
View File

@ -244,7 +244,7 @@ static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
}
/**
* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
* intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
* @vgpu: target vgpu
* @offset: offset
* @p_data: write data ptr

1
drivers/gpu/drm/i915/gvt/cmd_parser.c
View File

@ -37,6 +37,7 @@
#include <linux/slab.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"

2
drivers/gpu/drm/i915/gvt/display.c
View File

@ -36,6 +36,8 @@
#include "i915_reg.h"
#include "gvt.h"
#include "display/intel_dpio_phy.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)
{
u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);

2
drivers/gpu/drm/i915/gvt/dmabuf.h
View File

@ -48,7 +48,7 @@ struct intel_vgpu_fb_info {
struct intel_vgpu_dmabuf_obj *obj;
};
/**
/*
* struct intel_vgpu_dmabuf_obj- Intel vGPU device buffer object
*/
struct intel_vgpu_dmabuf_obj {

2
drivers/gpu/drm/i915/gvt/firmware.c
View File

@ -104,7 +104,7 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
memcpy(p, gvt->firmware.mmio, info->mmio_size);
crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
crc32_start = offsetof(struct gvt_firmware_header, version);
h->crc32 = crc32_le(0, firmware + crc32_start, size - crc32_start);
firmware_attr.size = size;

7
drivers/gpu/drm/i915/gvt/gtt.c
View File

@ -282,11 +282,6 @@ static inline int get_next_pt_type(int type)
return gtt_type_table[type].next_pt_type;
}
static inline int get_pt_type(int type)
{
return gtt_type_table[type].pt_type;
}
static inline int get_entry_type(int type)
{
return gtt_type_table[type].entry_type;
@ -2785,7 +2780,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
* intel_gvt_clean_gtt - clean up mm components of a GVT device
* @gvt: GVT device
*
* This function is called at the driver unloading stage, to clean up the
* This function is called at the driver unloading stage, to clean up
* the mm components of a GVT device.
*
*/

2
drivers/gpu/drm/i915/gvt/gvt.h
View File

@ -227,8 +227,6 @@ struct intel_vgpu {
unsigned long nr_cache_entries;
struct mutex cache_lock;
atomic_t released;
struct kvm_page_track_notifier_node track_node;
#define NR_BKT (1 << 18)
struct hlist_head ptable[NR_BKT];

Some files were not shown because too many files have changed in this diff Show More