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soc: fixes for 6.16, part 2

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There are 18 devicetree fixes for three arm64 plaforms: Qualcomm Snapdragon,
 Rockchips and NXP i.MX. These get updated to more correctly describe the
 hardware, fixing issues with:
 
  - real-time clock on Snapdragon based laptops
  - SD card detection, PCI probing and HDMI/DDC communication on
    Rockchips
  - Ethernet and SPI probing on certain i.MX based boards
  - A regression with the i.MX watchdog
 
 Aside from the devicetree fixes, there are two additional fixes for the
 merged ASPEED LPC snoop driver that saw some changes in 6.16, and one
 additional driver enabled in arm64 defconfig to fix CPU frequency scaling.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'soc-fixes-6.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
 "There are 18 devicetree fixes for three arm64 plaforms: Qualcomm
  Snapdragon, Rockchips and NXP i.MX. These get updated to more
  correctly describe the hardware, fixing issues with:

   - real-time clock on Snapdragon based laptops

   - SD card detection, PCI probing and HDMI/DDC communication on
     Rockchips

   - ethernet and SPI probing on certain i.MX based boards

   - a regression with the i.MX watchdog

  Aside from the devicetree fixes, there are two additional fixes for
  the merged ASPEED LPC snoop driver that saw some changes in 6.16, and
  one additional driver enabled in arm64 defconfig to fix CPU frequency
  scaling"

* tag 'soc-fixes-6.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (21 commits)
  arm64: dts: freescale: imx8mm-verdin: Keep LDO5 always on
  soc: aspeed: lpc-snoop: Don't disable channels that aren't enabled
  soc: aspeed: lpc-snoop: Cleanup resources in stack-order
  arm64: dts: imx95: Correct the DMA interrupter number of pcie0_ep
  arm64: dts: rockchip: Add missing fan-supply to rk3566-quartz64-a
  arm64: dts: rockchip: use cs-gpios for spi1 on ringneck
  arm64: dts: add big-endian property back into watchdog node
  arm64: dts: imx95-15x15-evk: fix the overshoot issue of NETC
  arm64: dts: imx95-19x19-evk: fix the overshoot issue of NETC
  arm64: dts: rockchip: list all CPU supplies on ArmSoM Sige5
  arm64: dts: imx8mp-venice-gw74xx: fix TPM SPI frequency
  arm64: dts: imx8mp-venice-gw73xx: fix TPM SPI frequency
  arm64: dts: imx8mp-venice-gw72xx: fix TPM SPI frequency
  arm64: dts: imx8mp-venice-gw71xx: fix TPM SPI frequency
  arm64: dts: qcom: x1e80100: describe uefi rtc offset
  arm64: dts: qcom: sc8280xp-x13s: describe uefi rtc offset
  arm64: defconfig: Enable Qualcomm CPUCP mailbox driver
  arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi 4B
  arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi CM5
  arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588
  ...
This commit is contained in:
Linus Torvalds 2025-07-15 09:26:33 -07:00
commit 4664a4ddb9
22 changed files with 143 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -687,11 +687,12 @@
};
wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
big-endian;
};
edma0: dma-controller@2c00000 {

1
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@ -464,6 +464,7 @@
};
reg_nvcc_sd: LDO5 {
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-module +V3.3_1.8_SD (LDO5)";

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
View File

@ -70,7 +70,7 @@
tpm@1 {
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
spi-max-frequency = <25000000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
View File

@ -110,7 +110,7 @@
tpm@1 {
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
spi-max-frequency = <25000000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
View File

@ -122,7 +122,7 @@
tpm@1 {
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
spi-max-frequency = <25000000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@ -201,7 +201,7 @@
tpm@0 {
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x0>;
spi-max-frequency = <36000000>;
spi-max-frequency = <25000000>;
};
};

20
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
View File

@ -574,17 +574,17 @@
&scmi_iomuxc {
pinctrl_emdio: emdiogrp {
fsl,pins = <
IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e
IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e
IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins = <
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e
IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
@ -598,10 +598,10 @@
pinctrl_enetc1: enetc1grp {
fsl,pins = <
IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e
IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e
IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e
IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e
IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e
IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e
IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e
IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e
IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e
IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e

12
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -566,17 +566,17 @@
&scmi_iomuxc {
pinctrl_emdio: emdiogrp{
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins = <
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e
IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e

2
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -1708,7 +1708,7 @@
<0x9 0 1 0>;
reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,

2
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -1090,6 +1090,8 @@
};
&pmk8280_rtc {
qcom,uefi-rtc-info;
status = "okay";
};

1
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
View File

@ -224,6 +224,7 @@
reg-names = "rtc", "alarm";
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
qcom,no-alarm; /* alarm owned by ADSP */
qcom,uefi-rtc-info;
};
pmk8550_sdam_2: nvram@7100 {

23
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
View File

@ -379,6 +379,18 @@
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
spi1 {
spi1_csn0_gpio_pin: spi1-csn0-gpio-pin {
rockchip,pins =
<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
spi1_csn1_gpio_pin: spi1-csn1-gpio-pin {
rockchip,pins =
<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
};
&pmu_io_domains {
@ -396,6 +408,17 @@
vqmmc-supply = <&vccio_sd>;
};
&spi1 {
/*
* Hardware CS has a very slow rise time of about 6us,
* causing transmission errors.
* With cs-gpios we have a rise time of about 20ns.
*/
cs-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>, <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_csn0_gpio_pin &spi1_csn1_gpio_pin &spi1_miso &spi1_mosi>;
};
&tsadc {
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
View File

@ -30,6 +30,7 @@
fan: gpio_fan {
compatible = "gpio-fan";
fan-supply = <&vcc12v_dcin>;
gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map =
< 0 0>,

28
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
View File

@ -211,10 +211,38 @@
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac0 {
phy-mode = "rgmii-id";
clock_in_out = "output";

2
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@ -615,7 +615,7 @@
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
linux,pci-domain = <0>;
linux,pci-domain = <1>;
max-link-speed = <2>;
num-ib-windows = <8>;
num-viewport = <8>;

20
arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
View File

@ -578,14 +578,14 @@
hdmim0_tx0_scl: hdmim0-tx0-scl {
rockchip,pins =
/* hdmim0_tx0_scl */
<4 RK_PB7 5 &pcfg_pull_none>;
<4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim0_tx0_sda: hdmim0-tx0-sda {
rockchip,pins =
/* hdmim0_tx0_sda */
<4 RK_PC0 5 &pcfg_pull_none>;
<4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@ -640,14 +640,14 @@
hdmim1_tx0_scl: hdmim1-tx0-scl {
rockchip,pins =
/* hdmim1_tx0_scl */
<0 RK_PD5 11 &pcfg_pull_none>;
<0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx0_sda: hdmim1-tx0-sda {
rockchip,pins =
/* hdmim1_tx0_sda */
<0 RK_PD4 11 &pcfg_pull_none>;
<0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@ -668,14 +668,14 @@
hdmim1_tx1_scl: hdmim1-tx1-scl {
rockchip,pins =
/* hdmim1_tx1_scl */
<3 RK_PC6 5 &pcfg_pull_none>;
<3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx1_sda: hdmim1-tx1-sda {
rockchip,pins =
/* hdmim1_tx1_sda */
<3 RK_PC5 5 &pcfg_pull_none>;
<3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
hdmim2_rx_cec: hdmim2-rx-cec {
@ -709,14 +709,14 @@
hdmim2_tx0_scl: hdmim2-tx0-scl {
rockchip,pins =
/* hdmim2_tx0_scl */
<3 RK_PC7 5 &pcfg_pull_none>;
<3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx0_sda: hdmim2-tx0-sda {
rockchip,pins =
/* hdmim2_tx0_sda */
<3 RK_PD0 5 &pcfg_pull_none>;
<3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@ -730,14 +730,14 @@
hdmim2_tx1_scl: hdmim2-tx1-scl {
rockchip,pins =
/* hdmim2_tx1_scl */
<1 RK_PA4 5 &pcfg_pull_none>;
<1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx1_sda: hdmim2-tx1-sda {
rockchip,pins =
/* hdmim2_tx1_sda */
<1 RK_PA3 5 &pcfg_pull_none>;
<1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/

1
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
View File

@ -321,6 +321,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-sdio;

5
arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
View File

@ -160,14 +160,15 @@
hdmim0_tx1_scl: hdmim0-tx1-scl {
rockchip,pins =
/* hdmim0_tx1_scl */
<2 RK_PB5 4 &pcfg_pull_none>;
<2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>;
};
/omit-if-no-ref/
hdmim0_tx1_sda: hdmim0-tx1-sda {
rockchip,pins =
/* hdmim0_tx1_sda */
<2 RK_PB4 4 &pcfg_pull_none>;
<2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>;
};
};

1
arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
View File

@ -474,6 +474,7 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-sdio;

35
arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
View File

@ -332,6 +332,41 @@
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
bias-disable;
drive-strength = <1>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
bias-disable;
drive-strength = <2>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
bias-disable;
drive-strength = <3>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
bias-disable;
drive-strength = <4>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
bias-disable;
drive-strength = <5>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_output_high: pcfg-output-high {
output-high;

1
arch/arm64/configs/defconfig
View File

@ -1444,6 +1444,7 @@ CONFIG_PLATFORM_MHU=y
CONFIG_BCM2835_MBOX=y
CONFIG_QCOM_APCS_IPC=y
CONFIG_MTK_ADSP_MBOX=m
CONFIG_QCOM_CPUCP_MBOX=m
CONFIG_QCOM_IPCC=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_TEGRA_IOMMU_SMMU=y

13
drivers/soc/aspeed/aspeed-lpc-snoop.c
View File

@ -58,6 +58,7 @@ struct aspeed_lpc_snoop_model_data {
};
struct aspeed_lpc_snoop_channel {
bool enabled;
struct kfifo fifo;
wait_queue_head_t wq;
struct miscdevice miscdev;
@ -190,6 +191,9 @@ static int aspeed_lpc_enable_snoop(struct aspeed_lpc_snoop *lpc_snoop,
const struct aspeed_lpc_snoop_model_data *model_data =
of_device_get_match_data(dev);
if (WARN_ON(lpc_snoop->chan[channel].enabled))
return -EBUSY;
init_waitqueue_head(&lpc_snoop->chan[channel].wq);
/* Create FIFO datastructure */
rc = kfifo_alloc(&lpc_snoop->chan[channel].fifo,
@ -236,6 +240,8 @@ static int aspeed_lpc_enable_snoop(struct aspeed_lpc_snoop *lpc_snoop,
regmap_update_bits(lpc_snoop->regmap, HICRB,
hicrb_en, hicrb_en);
lpc_snoop->chan[channel].enabled = true;
return 0;
err_misc_deregister:
@ -248,6 +254,9 @@ err_free_fifo:
static void aspeed_lpc_disable_snoop(struct aspeed_lpc_snoop *lpc_snoop,
int channel)
{
if (!lpc_snoop->chan[channel].enabled)
return;
switch (channel) {
case 0:
regmap_update_bits(lpc_snoop->regmap, HICR5,
@ -263,8 +272,10 @@ static void aspeed_lpc_disable_snoop(struct aspeed_lpc_snoop *lpc_snoop,
return;
}
kfifo_free(&lpc_snoop->chan[channel].fifo);
lpc_snoop->chan[channel].enabled = false;
/* Consider improving safety wrt concurrent reader(s) */
misc_deregister(&lpc_snoop->chan[channel].miscdev);
kfifo_free(&lpc_snoop->chan[channel].fifo);
}
static int aspeed_lpc_snoop_probe(struct platform_device *pdev)