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i3c: mipi-i3c-hci: Add a quirk to set timing parameters

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The AMD HCI controller is currently unstable at 12.5 MHz. To address this,
a quirk is added to configure the clock rate to 9 MHz as a workaround,
with proportional adjustments to the Open-Drain (OD) and Push-Pull (PP)
values.

Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20240829091713.736217-6-Shyam-sundar.S-k@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Shyam Sundar S K 2024-08-29 14:47:12 +05:30 committed by Alexandre Belloni
parent 216201b3d7
commit 46d4daa517
4 changed files with 42 additions and 2 deletions
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3
drivers/i3c/master/mipi-i3c-hci/Makefile
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@ -3,4 +3,5 @@
obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci.o
mipi-i3c-hci-y := core.o ext_caps.o pio.o dma.o \
cmd_v1.o cmd_v2.o \
dat_v1.o dct_v1.o
dat_v1.o dct_v1.o \
hci_quirks.o

6
drivers/i3c/master/mipi-i3c-hci/core.c
View File

@ -785,6 +785,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
return ret;
}
/* Configure OD and PP timings for AMD platforms */
if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
amd_set_od_pp_timing(hci);
return 0;
}
@ -838,7 +842,7 @@ static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
static const struct acpi_device_id i3c_hci_acpi_match[] = {
{ "AMDI5017", HCI_QUIRK_PIO_MODE },
{ "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING },
{}
};
MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match);

2
drivers/i3c/master/mipi-i3c-hci/hci.h
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@ -141,11 +141,13 @@ struct i3c_hci_dev_data {
/* list of quirks */
#define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */
#define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */
#define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */
/* global functions */
void mipi_i3c_hci_resume(struct i3c_hci *hci);
void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
void amd_set_od_pp_timing(struct i3c_hci *hci);
#endif

33
drivers/i3c/master/mipi-i3c-hci/hci_quirks.c Normal file
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@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* I3C HCI Quirks
*
* Copyright 2024 Advanced Micro Devices, Inc.
*
* Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
* Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
*/
#include <linux/i3c/master.h>
#include "hci.h"
/* Timing registers */
#define HCI_SCL_I3C_OD_TIMING 0x214
#define HCI_SCL_I3C_PP_TIMING 0x218
#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
/* Timing values to configure 9MHz frequency */
#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
#define AMD_SCL_I3C_PP_TIMING 0x00160016
void amd_set_od_pp_timing(struct i3c_hci *hci)
{
u32 data;
reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING);
reg_write(HCI_SCL_I3C_PP_TIMING, AMD_SCL_I3C_PP_TIMING);
data = reg_read(HCI_SDA_HOLD_SWITCH_DLY_TIMING);
/* Configure maximum TX hold time */
data |= W0_MASK(18, 16);
reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
}