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media: camss: csiphy: Move to hardcode CSI Clock Lane number

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QCOM ISPs do not support having a programmable CSI Clock Lane number.

In order to accurately reflect this, the different CSIPHY HW versions
need to have their own register layer for computing lane masks.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Robert Foss 2021-12-06 16:18:10 +01:00 committed by Mauro Carvalho Chehab
parent 4a92fc6e55
commit 4abb21309f
4 changed files with 41 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
View File

@ -16,6 +16,7 @@
#define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n)) #define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n))
#define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n)) #define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n))
#define CAMSS_CSI_PHY_LN_CLK 1
#define CAMSS_CSI_PHY_GLBL_RESET 0x140 #define CAMSS_CSI_PHY_GLBL_RESET 0x140
#define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x144 #define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x144
#define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x164 #define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x164
@ -26,6 +27,19 @@
#define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec #define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec
#define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f4 #define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f4
static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
{
u8 lane_mask;
int i;
lane_mask = 1 << CAMSS_CSI_PHY_LN_CLK;
for (i = 0; i < lane_cfg->num_data; i++)
lane_mask |= 1 << lane_cfg->data[i].pos;
return lane_mask;
}
static void csiphy_hw_version_read(struct csiphy_device *csiphy, static void csiphy_hw_version_read(struct csiphy_device *csiphy,
struct device *dev) struct device *dev)
{ {
@ -105,7 +119,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
for (i = 0; i <= c->num_data; i++) { for (i = 0; i <= c->num_data; i++) {
if (i == c->num_data) if (i == c->num_data)
l = c->clk.pos; l = CAMSS_CSI_PHY_LN_CLK;
else else
l = c->data[i].pos; l = c->data[i].pos;
@ -129,7 +143,7 @@ static void csiphy_lanes_disable(struct csiphy_device *csiphy,
for (i = 0; i <= c->num_data; i++) { for (i = 0; i <= c->num_data; i++) {
if (i == c->num_data) if (i == c->num_data)
l = c->clk.pos; l = CAMSS_CSI_PHY_LN_CLK;
else else
l = c->data[i].pos; l = c->data[i].pos;
@ -167,6 +181,7 @@ static irqreturn_t csiphy_isr(int irq, void *dev)
} }
const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = { const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = {
.get_lane_mask = csiphy_get_lane_mask,
.hw_version_read = csiphy_hw_version_read, .hw_version_read = csiphy_hw_version_read,
.reset = csiphy_reset, .reset = csiphy_reset,
.lanes_enable = csiphy_lanes_enable, .lanes_enable = csiphy_lanes_enable,

17
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
View File

@ -43,6 +43,7 @@
#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n)) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n))
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n))
@ -448,6 +449,19 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
} }
} }
static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
{
u8 lane_mask;
int i;
lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
for (i = 0; i < lane_cfg->num_data; i++)
lane_mask |= 1 << lane_cfg->data[i].pos;
return lane_mask;
}
static void csiphy_lanes_enable(struct csiphy_device *csiphy, static void csiphy_lanes_enable(struct csiphy_device *csiphy,
struct csiphy_config *cfg, struct csiphy_config *cfg,
s64 link_freq, u8 lane_mask) s64 link_freq, u8 lane_mask)
@ -461,7 +475,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
val = is_gen2 ? BIT(7) : BIT(c->clk.pos); val = is_gen2 ? BIT(7) : CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
for (i = 0; i < c->num_data; i++) for (i = 0; i < c->num_data; i++)
val |= BIT(c->data[i].pos * 2); val |= BIT(c->data[i].pos * 2);
@ -497,6 +511,7 @@ static void csiphy_lanes_disable(struct csiphy_device *csiphy,
} }
const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
.get_lane_mask = csiphy_get_lane_mask,
.hw_version_read = csiphy_hw_version_read, .hw_version_read = csiphy_hw_version_read,
.reset = csiphy_reset, .reset = csiphy_reset,
.lanes_enable = csiphy_lanes_enable, .lanes_enable = csiphy_lanes_enable,

21
drivers/media/platform/qcom/camss/camss-csiphy.c
View File

@ -230,25 +230,6 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
return 0; return 0;
} }
/*
* csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
* @lane_cfg - CSI2 lane configuration
*
* Return lane mask
*/
static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
{
u8 lane_mask;
int i;
lane_mask = 1 << lane_cfg->clk.pos;
for (i = 0; i < lane_cfg->num_data; i++)
lane_mask |= 1 << lane_cfg->data[i].pos;
return lane_mask;
}
/* /*
* csiphy_stream_on - Enable streaming on CSIPHY module * csiphy_stream_on - Enable streaming on CSIPHY module
* @csiphy: CSIPHY device * @csiphy: CSIPHY device
@ -262,7 +243,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
{ {
struct csiphy_config *cfg = &csiphy->cfg; struct csiphy_config *cfg = &csiphy->cfg;
s64 link_freq; s64 link_freq;
u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); u8 lane_mask = csiphy->ops->get_lane_mask(&cfg->csi2->lane_cfg);
u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats,
csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;

7
drivers/media/platform/qcom/camss/camss-csiphy.h
View File

@ -45,6 +45,13 @@ struct csiphy_config {
struct csiphy_device; struct csiphy_device;
struct csiphy_hw_ops { struct csiphy_hw_ops {
/*
* csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
* @lane_cfg - CSI2 lane configuration
*
* Return lane mask
*/
u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
void (*hw_version_read)(struct csiphy_device *csiphy, void (*hw_version_read)(struct csiphy_device *csiphy,
struct device *dev); struct device *dev);
void (*reset)(struct csiphy_device *csiphy); void (*reset)(struct csiphy_device *csiphy);