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clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
Register compatible and cmu_info data to support clocks. CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C. CMU_MISC, this provides clocks for MISC, GIC and OTP. CMU_HSI0, this provides clocks for PCIE. CMU_HSI1, this provides clocks for USB and MMC. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20241009042110.2379903-3-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Sunyeal Hong
Krzysztof Kozlowski
parent
ac08b52a5f
commit
5e830d3c97
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@ -19,6 +19,10 @@
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/* NOTE: Must be equal to the last clock ID increased by one */
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#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
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#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
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#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
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#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
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#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
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#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
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/* ---- CMU_TOP ------------------------------------------------------------ */
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@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon
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"mout_shared5_pll", 1, 3, 0),
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FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
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"mout_shared5_pll", 1, 4, 0),
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FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
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"oscclk", 1, 2, 0),
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};
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static const struct samsung_cmu_info top_cmu_info __initconst = {
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@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
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.clk_name = "noc",
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};
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/* ---- CMU_PERIC1 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
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#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
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#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
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#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
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#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
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#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
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#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
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static const unsigned long peric1_clk_regs[] __initconst = {
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PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
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PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
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CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
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CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
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CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
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};
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/* List of parent clocks for Muxes in CMU_PERIC1 */
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PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
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PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
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PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
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static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
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MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
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mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
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MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
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mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
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/* USI09 ~ USI17 */
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MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
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MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
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/* USI_I2C */
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MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
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/* USI_I3C */
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MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
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mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
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};
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static const struct samsung_div_clock peric1_div_clks[] __initconst = {
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/* USI09 ~ USI17 */
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DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
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"mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
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"mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
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"mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
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"mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
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"mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
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"mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
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"mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
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"mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
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"mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
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0, 4),
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/* USI_I2C */
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DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
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"mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
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/* USI_I3C */
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DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
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"mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
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};
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static const struct samsung_cmu_info peric1_cmu_info __initconst = {
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.mux_clks = peric1_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
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.div_clks = peric1_div_clks,
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.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
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.nr_clk_ids = CLKS_NR_PERIC1,
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.clk_regs = peric1_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
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.clk_name = "noc",
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};
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/* ---- CMU_MISC --------------------------------------------------------- */
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/* Register Offset definitions for CMU_MISC (0x10020000) */
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#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
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#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
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#define CLK_CON_DIV_CLKCMU_OTP 0x1800
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#define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
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#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
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static const unsigned long misc_clk_regs[] __initconst = {
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PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
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CLK_CON_MUX_MUX_CLK_MISC_GIC,
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CLK_CON_DIV_CLKCMU_OTP,
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CLK_CON_DIV_DIV_CLK_MISC_NOCP,
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CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
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};
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/* List of parent clocks for Muxes in CMU_MISC */
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PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
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PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
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static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
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MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
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mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
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MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
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mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
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};
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static const struct samsung_div_clock misc_div_clks[] __initconst = {
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DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
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"mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
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0, 3),
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};
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static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
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FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
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"oscclk", 1, 10, 0),
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FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
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"oscclk", 1, 2, 0),
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};
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static const struct samsung_cmu_info misc_cmu_info __initconst = {
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.mux_clks = misc_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
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.div_clks = misc_div_clks,
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.nr_div_clks = ARRAY_SIZE(misc_div_clks),
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.fixed_factor_clks = misc_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
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.nr_clk_ids = CLKS_NR_MISC,
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.clk_regs = misc_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
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.clk_name = "noc",
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};
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/* ---- CMU_HSI0 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_HSI0 (0x16000000) */
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#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
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#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
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static const unsigned long hsi0_clk_regs[] __initconst = {
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PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
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CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
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};
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/* List of parent clocks for Muxes in CMU_HSI0 */
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PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
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static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
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MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
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mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
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};
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static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
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DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
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"mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
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0, 4),
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};
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static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
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.mux_clks = hsi0_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
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.div_clks = hsi0_div_clks,
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.nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
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.nr_clk_ids = CLKS_NR_HSI0,
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.clk_regs = hsi0_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
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.clk_name = "noc",
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};
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/* ---- CMU_HSI1 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_HSI1 (0x16400000) */
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#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
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#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
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#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
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#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
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static const unsigned long hsi1_clk_regs[] __initconst = {
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PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
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PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
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PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
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CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
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};
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/* List of parent clocks for Muxes in CMU_HSI1 */
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PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
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PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
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PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
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PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
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static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
|
||||
mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
|
||||
MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
|
||||
mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
|
||||
MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
|
||||
mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
|
||||
MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
|
||||
mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
|
||||
.mux_clks = hsi1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
|
||||
.nr_clk_ids = CLKS_NR_HSI1,
|
||||
.clk_regs = hsi1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
|
||||
.clk_name = "noc",
|
||||
};
|
||||
|
||||
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct samsung_cmu_info *info;
|
||||
|
|
@ -1154,6 +1431,18 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
|
|||
{
|
||||
.compatible = "samsung,exynosautov920-cmu-peric0",
|
||||
.data = &peric0_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-peric1",
|
||||
.data = &peric1_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-misc",
|
||||
.data = &misc_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-hsi0",
|
||||
.data = &hsi0_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-hsi1",
|
||||
.data = &hsi1_cmu_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user