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drm/amd/display: handle invalid connector indices

Browse Source 
[Why]
The function to count the number of valid connectors does not
guarantee that the first n indices are valid, only that there
exist n valid indices. When invalid indices are present, this
results in later valid connectors being missed, as processing
would end after checking n indices.

[How]
 - count valid indices separately from total indices examined
 - add explicit definition of MAX_LINKS

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Aberback 2024-03-15 04:07:42 -04:00 committed by Alex Deucher
parent 8b2cb32cf0
commit 60df562814
8 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
View File

@ -503,7 +503,7 @@ static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc
clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
for (i = 0; i < MAX_PIPES * 2; i++) { for (i = 0; i < MAX_LINKS; i++) {
if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
} }

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View File

@ -548,7 +548,7 @@ static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_l
clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
for (i = 0; i < MAX_PIPES * 2; i++) { for (i = 0; i < MAX_LINKS; i++) {
if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
} }

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
View File

@ -474,7 +474,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d
clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
for (i = 0; i < MAX_PIPES * 2; i++) { for (i = 0; i < MAX_LINKS; i++) {
if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
} }

3
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -212,7 +212,8 @@ static bool create_links(
connectors_num, connectors_num,
num_virtual_links); num_virtual_links);
for (i = 0; i < connectors_num; i++) { // condition loop on link_count to allow skipping invalid indices
for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
struct link_init_data link_init_params = {0}; struct link_init_data link_init_params = {0};
struct dc_link *link; struct dc_link *link;

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -1327,7 +1327,7 @@ struct dc {
struct dc_phy_addr_space_config vm_pa_config; struct dc_phy_addr_space_config vm_pa_config;
uint8_t link_count; uint8_t link_count;
struct dc_link *links[MAX_PIPES * 2]; struct dc_link *links[MAX_LINKS];
struct link_service *link_srv; struct link_service *link_srv;
struct dc_state *current_state; struct dc_state *current_state;

2
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
View File

@ -349,7 +349,7 @@ struct clk_mgr_internal {
enum dm_pp_clocks_state cur_min_clks_state; enum dm_pp_clocks_state cur_min_clks_state;
bool periodic_retraining_disabled; bool periodic_retraining_disabled;
unsigned int cur_phyclk_req_table[MAX_PIPES * 2]; unsigned int cur_phyclk_req_table[MAX_LINKS];
bool smu_present; bool smu_present;
void *wm_range_table; void *wm_range_table;

1
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
View File

@ -44,6 +44,7 @@
*/ */
#define MAX_PIPES 6 #define MAX_PIPES 6
#define MAX_PHANTOM_PIPES (MAX_PIPES / 2) #define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
#define MAX_LINKS (MAX_PIPES * 2)
#define MAX_DIG_LINK_ENCODERS 7 #define MAX_DIG_LINK_ENCODERS 7
#define MAX_DWB_PIPES 1 #define MAX_DWB_PIPES 1
#define MAX_HPO_DP2_ENCODERS 4 #define MAX_HPO_DP2_ENCODERS 4

4
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
View File

@ -166,7 +166,7 @@ static uint8_t get_lowest_dpia_index(struct dc_link *link)
uint8_t idx = 0xFF; uint8_t idx = 0xFF;
int i; int i;
for (i = 0; i < MAX_PIPES * 2; ++i) { for (i = 0; i < MAX_LINKS; ++i) {
if (!dc_struct->links[i] || if (!dc_struct->links[i] ||
dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA) dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
@ -196,7 +196,7 @@ static int get_host_router_total_dp_tunnel_bw(const struct dc *dc, uint8_t hr_in
struct dc_link *link_dpia_primary, *link_dpia_secondary; struct dc_link *link_dpia_primary, *link_dpia_secondary;
int total_bw = 0; int total_bw = 0;
for (uint8_t i = 0; i < (MAX_PIPES * 2) - 1; ++i) { for (uint8_t i = 0; i < MAX_LINKS - 1; ++i) {
if (!dc->links[i] || dc->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA) if (!dc->links[i] || dc->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
continue; continue;