MIRRORS/linux-yocto
1
0
Fork 0
mirror of git://git.yoctoproject.org/linux-yocto.git synced 2025-10-22 15:03:53 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

i.MX arm64 device tree change for 6.16:

Browse Source 
- New board support: TQMa8XxS, TQMa95xxSA, TQMa93xx, MBa91xxCA,
   i.MX943 EVK, Nitrogen8M Plus ENC Carrier, Toradex SMARC i.MX8MP,
   Libra-i.MX 8M Plus FPSC board
 - A couple of imx8mp-tqma8mpql-mba8mp-ras314 board updates that support
   Raspberry Pi Camera V2 and LVDS using device tree overlay
 - A series from Adam Ford that updates i.MX8M Beacon boards for RTC
   capacitive load, HDMI audio, Ethernet PHY, etc.
 - A set of changes from Daniel Baluta that enables i.MX8MP DSP node
   for rproc usage
 - A few changes from Francesco Dolcini that add EEPROM compatible
   fallback for imx8mp-verdin board, add fan PWM configuation for
   imx8mp-toradex-smarc board
 - A series from Frank Li to enable PCIe EP support all i.MX8 devices
   using device tree overlay
 - A change from Laurentiu Mihalcea to enable Sound Open Firmware (SOF)
   support on imx95-19x19-evk board
 - A few changes from Markus Niebel to disable MDIO Open Drain for
   imx93-tqma9352 devices
 - A couple of changes from Max Krummenacher to enable PCIe and SATA
   support for i.MX8 Apalis and Colibri boards
 - A series from Primoz Fiser to enable various devices/functions for
   i.MX93 phycore boards
 - A patch set from Xu Yang to add USB2.0 support for i.MX95 EVK boards
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmghzEsUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM7o7gf+K6yNLsEH7fJ/L1faCYfElURJXg+f
 X3nfCJwlC7rHAa7yFTb8U2Fu/1Tl4Xm8EtBr8RYIiPq3i+K80jRk/Ns9g/YJPIAT
 XrPFVXI9OFWKrYazZVcMvxIDSDS6oB+HjugKb4iJGqktDDvvC+hVc1dzjvyTua39
 N0sU3vOUDMPVfmzUFuedfH181M8MLe2gK3dM8t+5c8asVSogP6XElZG+nLF/2djm
 /ZuBTUePrMLLnVWTSNzbmYZcFxMoK34Bl87yoin47S1zALL9gfxS/VMXFXiJsQ8Q
 c0be/siJQlwSCzmkvrDzuU7Nw5mEboNHM1e7bDEMfdtrZfkA3b7z0bTIVQ==
 =8sq6
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmgh56YACgkQYKtH/8kJ
 Uic7eg//VbLKZM1GQH52y0LRQCpklQRG4l3PjiOJyMAsFEf0GTTEPgNiRNiSv5WS
 kXlsojsS0QulOZdRb2v84fOFmffaG7pq0o4dgN4+iWSbGUvWLb+PM46CMi39DeOD
 lqgRlAVdKkOLxvDnIAEq7ce6/C4EIoIYul4D9CXLF7Jnf/NnGpB5lv8M+Sh1nv5D
 xurEzUlbNuSBbxkw0mgoeiqXaGO3sFeILEV6F67np1Z6QvgeJ6nNDrX5Dd7FlwwV
 eqMWpXMwGHLFok0RYWlBCpFO//hrjQi4T9y+weKEnzI1TRIiDWxH1kUWdNMpGQ5l
 EcbpT42zaQamnqgbC25K+dqpSyZLLWSXZb/DkbaFvDY++riXRIEU9qOrWxBkQ73V
 AWjldmzI8h1mKJKPkvHeo8gY4lmm9aaQSlzELyC8zYo8HJkcsyTQCG31uc/50S0z
 765SoGd4eFTyC1aqwd01sJTqIJpi4nTAObWdCf7ptjaBFrQjliUgjTwbRY0Y8IFr
 erk86QJJw9ti2RdVz4ygKjiwpin7ROBvgzNkjh8Ud/DKYhKX6BAMXKcz38MOYoV/
 jg5V2EJt2U02XzdP2C8pSe1TNlaibMDgvR+KSs/8hlIvokhX/HNm01ET2y/EONbi
 7M0s7sYN4Ii8X39bG5BOh/wRCZo9sLfsdHA2buOWwlQ5NgvyHWM=
 =A7Fy
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt64-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree change for 6.16:

- New board support: TQMa8XxS, TQMa95xxSA, TQMa93xx, MBa91xxCA,
  i.MX943 EVK, Nitrogen8M Plus ENC Carrier, Toradex SMARC i.MX8MP,
  Libra-i.MX 8M Plus FPSC board
- A couple of imx8mp-tqma8mpql-mba8mp-ras314 board updates that support
  Raspberry Pi Camera V2 and LVDS using device tree overlay
- A series from Adam Ford that updates i.MX8M Beacon boards for RTC
  capacitive load, HDMI audio, Ethernet PHY, etc.
- A set of changes from Daniel Baluta that enables i.MX8MP DSP node
  for rproc usage
- A few changes from Francesco Dolcini that add EEPROM compatible
  fallback for imx8mp-verdin board, add fan PWM configuation for
  imx8mp-toradex-smarc board
- A series from Frank Li to enable PCIe EP support all i.MX8 devices
  using device tree overlay
- A change from Laurentiu Mihalcea to enable Sound Open Firmware (SOF)
  support on imx95-19x19-evk board
- A few changes from Markus Niebel to disable MDIO Open Drain for
  imx93-tqma9352 devices
- A couple of changes from Max Krummenacher to enable PCIe and SATA
  support for i.MX8 Apalis and Colibri boards
- A series from Primoz Fiser to enable various devices/functions for
  i.MX93 phycore boards
- A patch set from Xu Yang to add USB2.0 support for i.MX95 EVK boards

* tag 'imx-dt64-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (71 commits)
  arm64: dts: freescale: Add PHYTEC phyBOARD-Nash-i.MX93 support
  arm64: dts: freescale: imx8mp-toradex-smarc: use generic gpio node name
  arm64: dts: freescale: imx8mp-toradex-smarc: add gpio expander
  arm64: dts: freescale: imx8mp-toradex-smarc: add embedded controller
  arm64: dts: freescale: imx8mp-toradex-smarc: add fan PWM configuration
  arm64: dts: imx93-tqma9352-mba91xxca: disable Open Drain for MDIO
  arm64: dt: imx95: Add TQMa95xxSA
  arm64: dts: imx: Align wifi node name with bindings
  arm64: dts: freescale: add initial device tree for TQMa8XxS
  arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add Raspberry Pi Camera V2 overlay
  arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add LVDS device tree overlay
  arm64: dts: freescale: Add minimal dts support for imx943 evk
  arm64: dts: freescale: Add basic dtsi for imx943
  arm64: dts: imx8-colibri: Add PCIe support
  arm64: dts: freescale: imx93-phyboard-segin: Order node alphabetically
  arm64: dts: freescale: imx93-phyboard-segin: Add EQOS Ethernet
  arm64: dts: freescale: imx93-phyboard-segin: Add I2S audio
  arm64: dts: freescale: imx93-phyboard-segin: Add USB support
  arm64: dts: freescale: imx93-phyboard-segin: Add CAN support
  arm64: dts: freescale: imx93-phyboard-segin: Add RTC support
  ...

Link: https://lore.kernel.org/r/20250512103858.50501-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-05-12 14:20:48 +02:00
commit 6c265faf1a
68 changed files with 11066 additions and 183 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -24550,6 +24550,7 @@ F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts*
F: arch/arm64/boot/dts/freescale/imx*mba*.dts*
F: arch/arm64/boot/dts/freescale/imx*tqma*.dts*
F: arch/arm64/boot/dts/freescale/mba*.dtsi
F: arch/arm64/boot/dts/freescale/tqma8*.dtsi
F: arch/arm64/boot/dts/freescale/tqml*.dts*
F: drivers/gpio/gpio-tqmx86.c
F: drivers/mfd/tqmx86.c

40
arch/arm64/boot/dts/freescale/Makefile
View File

@ -104,7 +104,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
@ -112,6 +117,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb
imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo
imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb
@ -200,8 +210,12 @@ imx8mp-kontron-dl-dtbs += imx8mp-kontron-bl-osm-s.dtb imx8mp-kontron-dl.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb
imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
@ -212,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb
@ -237,7 +252,7 @@ imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-
imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo
imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo
imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo
imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo
imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb
@ -247,10 +262,19 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb
imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo
imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo
imx8mp-tqma8mpql-mba8mp-ras314-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo
imx8mp-tqma8mpql-mba8mp-ras314-lvds-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo
imx8mp-tqma8mpql-mba8mp-ras314-lvds-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-imx219.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
@ -284,10 +308,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo
imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
@ -297,12 +322,23 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo
imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb
imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo

6
arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso → arch/arm64/boot/dts/freescale/imx-pcie0-ep.dtso
View File

@ -6,12 +6,10 @@
/dts-v1/;
/plugin/;
&pcie {
&pcie0 {
status = "disabled";
};
&pcie_ep {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
&pcie0_ep {
status = "okay";
};

15
arch/arm64/boot/dts/freescale/imx-pcie1-ep.dtso Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
/plugin/;
&pcie1 {
status = "disabled";
};
&pcie1_ep {
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
View File

@ -104,7 +104,10 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
@ -121,7 +124,10 @@
status = "okay";
};
/* TODO: Apalis SATA1 */
/* Apalis SATA1 */
&sata {
status = "okay";
};
/* Apalis SPDIF1 */
&spdif0 {

10
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
View File

@ -191,7 +191,10 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
@ -208,7 +211,10 @@
status = "okay";
};
/* TODO: Apalis SATA1 */
/* Apalis SATA1 */
&sata {
status = "okay";
};
/* Apalis SPDIF1 */
&spdif0 {

10
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
View File

@ -240,7 +240,10 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
@ -257,7 +260,10 @@
status = "okay";
};
/* TODO: Apalis SATA1 */
/* Apalis SATA1 */
&sata {
status = "okay";
};
/* Apalis SPDIF1 */
&spdif0 {

70
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -339,6 +339,25 @@
pinctrl-0 = <&pinctrl_flexcan3>;
};
&hsio_phy {
fsl,hsio-cfg = "pciea-pcieb-sata";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&hsio_refa_clk {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>;
};
&hsio_refb_clk {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
clocks = <&hsio_refa_clk>;
enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>;
};
/* TODO: Apalis HDMI1 */
&gpu_alert0 {
@ -514,7 +533,10 @@
"MXM3_112",
"MXM3_118",
"MXM3_114",
"MXM3_116";
"MXM3_116",
"",
"",
"MXM3_26";
};
&lsio_gpio1 {
@ -586,15 +608,6 @@
"MXM3_183",
"MXM3_185",
"MXM3_187";
pcie-wifi-hog {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "PCIE_WIFI_CLK";
output-high;
};
};
&lsio_gpio3 {
@ -660,16 +673,6 @@
"MXM3_291",
"MXM3_289",
"MXM3_287";
/* Enable pcie root / sata ref clock unconditionally */
pcie-sata-hog {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "PCIE_SATA_CLK";
output-high;
};
};
&lsio_gpio5 {
@ -771,9 +774,30 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie_switch>;
};
/* TODO: On-module Wi-Fi */
/* On-module Wi-Fi */
&pcieb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>;
phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy";
reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&phyx2_lpcg {
clocks = <&hsio_refa_clk>, <&hsio_refb_clk>,
<&hsio_refa_clk>, <&hsio_per_clk>;
};
/* TODO: Apalis BKL1_PWM */
@ -806,8 +830,6 @@
<722534400>, <45158400>, <11289600>, <49152000>;
};
/* TODO: Apalis SATA1 */
/* Apalis SPDIF1 */
&spdif0 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,

12
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -642,7 +642,7 @@
status = "okay";
};
&pcieb {
&pcie0 {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
@ -652,6 +652,16 @@
status = "okay";
};
&pcie0_ep{
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
status = "disabled";
};
&sai0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;

25
arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
View File

@ -37,15 +37,20 @@
power-domains = <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
};
&pcieb {
#interrupt-cells = <1>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map = <0 0 0 1 &gic 0 47 4>,
<0 0 0 2 &gic 0 48 4>,
<0 0 0 3 &gic 0 49 4>,
<0 0 0 4 &gic 0 50 4>;
interrupt-map-mask = <0 0 0 0x7>;
pcie0: pcie@5f010000 {
#interrupt-cells = <1>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map = <0 0 0 1 &gic 0 47 4>,
<0 0 0 2 &gic 0 48 4>,
<0 0 0 3 &gic 0 49 4>,
<0 0 0 4 &gic 0 50 4>;
interrupt-map-mask = <0 0 0 0x7>;
};
pcie0_ep: pcie-ep@5f010000 {
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
};
};

16
arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps-mb-smarc-2.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include "imx8dxp-tqma8xdps.dtsi"
#include "tqma8xxs-mb-smarc-2.dtsi"
/ {
model = "TQ-Systems i.MX8DXP TQMa8XDPS on MB-SMARC-2";
compatible = "tq,imx8dxp-tqma8xdps-mb-smarc-2", "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp";
};

24
arch/arm64/boot/dts/freescale/imx8dxp-tqma8xdps.dtsi Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include "imx8dxp.dtsi"
#include "tqma8xxs.dtsi"
/ {
model = "TQ-Systems i.MX8DXP TQMa8XDPS";
compatible = "tq,imx8dxp-tqma8xdps", "fsl,imx8dxp";
};
&pmic0_thermal {
cooling-maps {
map0 {
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

1
arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts
View File

@ -124,6 +124,7 @@
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};

18
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
View File

@ -78,6 +78,9 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
@ -233,6 +236,12 @@
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
quartz-load-femtofarads = <12500>;
wakeup-source;
};
};
@ -269,7 +278,7 @@
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
pinctrl-names = "default";
@ -314,6 +323,7 @@
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
@ -349,6 +359,12 @@
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140

13
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -544,6 +544,19 @@
status = "okay";
};
&pcie0_ep {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "disabled";
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";

2
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
View File

@ -186,6 +186,8 @@
reg = <2>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
ti,lvds-vod-swing-clock-microvolt = <200000 600000>;
ti,lvds-vod-swing-data-microvolt = <200000 600000>;
};
};
};

2
arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
View File

@ -306,7 +306,7 @@
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};

6
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@ -528,7 +528,7 @@
};
eeprom@50 {
compatible = "st,24c02";
compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
@ -633,7 +633,7 @@
/* EEPROM on display adapter (MIPI DSI Display Adapter) */
eeprom_display_adapter: eeprom@50 {
compatible = "st,24c02";
compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
status = "disabled";
@ -641,7 +641,7 @@
/* EEPROM on carrier board */
eeprom_carrier_board: eeprom@57 {
compatible = "st,24c02";
compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x57>;
status = "disabled";

4
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -62,7 +62,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -83,7 +82,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -102,7 +100,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -121,7 +118,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;

1
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts
View File

@ -124,6 +124,7 @@
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};

18
arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
View File

@ -88,6 +88,9 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
@ -242,6 +245,12 @@
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
quartz-load-femtofarads = <12500>;
wakeup-source;
};
};
@ -280,7 +289,7 @@
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
pinctrl-names = "default";
@ -325,6 +334,7 @@
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
@ -360,6 +370,12 @@
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140

2
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
View File

@ -265,7 +265,7 @@
non-removable;
status = "okay";
brcmf: bcrmf@1 {
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
pinctrl-names = "default";

2
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@ -300,7 +300,7 @@
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};

4
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -62,7 +62,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -83,7 +82,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -102,7 +100,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -121,7 +118,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;

12
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
View File

@ -257,6 +257,12 @@
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
quartz-load-femtofarads = <12500>;
wakeup-source;
};
};
@ -381,6 +387,12 @@
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1d0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140

2
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -590,7 +590,7 @@
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 { /* muRata 2AE */
brcmf: wifi@1 { /* muRata 2AE */
reg = <1>;
compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
/*

22
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -309,6 +309,16 @@
status = "okay";
};
&dsp_reserved {
status = "okay";
};
&dsp {
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
@ -690,6 +700,10 @@
};
};
&mu2 {
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
@ -697,7 +711,7 @@
status = "okay";
};
&pcie {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
@ -705,6 +719,12 @@
status = "okay";
};
&pcie0_ep {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
status = "disabled";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;

44
arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>
/dts-v1/;
/plugin/;
&backlight_lvds0 {
brightness-levels = <0 8 16 32 64 128 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
num-interpolated-steps = <2>;
pwms = <&pwm1 0 66667 0>;
status = "okay";
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
/*
* The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
* 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
* engine can reach accurate pixel clock of exactly 72.4 MHz.
*/
assigned-clock-rates = <0>, <506800000>;
status = "okay";
};
&panel0_lvds {
compatible = "edt,etml1010g3dra";
status = "okay";
};
&pwm1 {
status = "okay";
};

290
arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts Normal file
View File

@ -0,0 +1,290 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-phycore-fpsc.dtsi"
/ {
compatible = "phytec,imx8mp-libra-rdk-fpsc",
"phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
model = "PHYTEC i.MX8MP Libra RDK FPSC";
backlight_lvds0: backlight0 {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_lvds0>;
pinctrl-names = "default";
power-supply = <&reg_vdd_12v0>;
status = "disabled";
};
chosen {
stdout-path = &uart4;
};
panel0_lvds: panel-lvds {
/* compatible panel in overlay */
backlight = <&backlight_lvds0>;
power-supply = <&reg_vdd_3v3>;
status = "disabled";
port {
panel0_in: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "can1-stby";
gpio = <&gpio_expander 10 GPIO_ACTIVE_LOW>;
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "can2-stby";
gpio = <&gpio_expander 9 GPIO_ACTIVE_LOW>;
};
reg_vdd_12v0: regulator-vdd-12v0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <12000000>;
regulator-min-microvolt = <12000000>;
regulator-name = "VDD_12V0";
};
reg_vdd_1v8: regulator-vdd-1v8 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8";
};
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3";
};
reg_vdd_5v0: regulator-vdd-5v0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "VDD_5V0";
};
};
&eqos {
phy-handle = <&ethphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
};
};
};
/* CAN FD */
&flexcan1 {
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&flexspi {
status = "okay";
spi_nor: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&reg_vdd_1v8>;
};
};
&gpio5 {
gpio-line-names = "", "", "", "", "I2C5_SDA",
"GPIO1", "", "", "", "SPI1_CS",
"", "", "", "SPI2_CS", "I2C1_SCL",
"I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA",
"", "GPIO2", "", "LVDS1_BL_EN", "SPI3_CS",
"", "GPIO3";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
vcc-supply = <&reg_vdd_1v8>;
};
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
leds@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-1 {
type = <PCA9532_TYPE_LED>;
};
led-2 {
type = <PCA9532_TYPE_LED>;
};
led-3 {
type = <PCA9532_TYPE_LED>;
};
};
};
&i2c5 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
status = "okay";
gpio_expander: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3",
"CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2",
"CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV",
"nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE",
"PCIE2_nWAKE", "PCIE2_nALERT_3V3",
"UART1_BT_RS_SEL", "UART1_RS232_485_SEL";
vcc-supply = <&reg_vdd_1v8>;
uart1_bt_rs_sel: bt-rs-hog {
gpios = <14 GPIO_ACTIVE_HIGH>;
gpio-hog;
line-name = "UART1_BT_RS_SEL";
output-low; /* default RS232/RS485 */
};
uart1_rs232_485_sel: rs232-485-hog {
gpios = <15 GPIO_ACTIVE_HIGH>;
gpio-hog;
line-name = "UART1_RS232_485_SEL";
output-high; /* default RS232 */
};
};
};
&iomuxc {
pinctrl_lvds0: lvds0grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x12
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0
>;
};
};
&lvds_bridge {
ports {
port@1 {
ldb_lvds_ch0: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
};
/* Mini PCIe */
&pcie {
reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_vdd_3v3>;
status = "okay";
};
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};
&reg_vdd_io {
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
&rv3028 {
interrupt-parent = <&gpio5>;
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
aux-voltage-chargeable = <1>;
pinctrl-0 = <&pinctrl_rtc>;
pinctrl-names = "default";
trickle-resistor-ohms = <3000>;
wakeup-source;
};
&snvs_pwrkey {
status = "okay";
};
/* debug console */
&uart4 {
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
disable-wp;
status = "okay";
};

452
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-enc-carrier-board.dts Normal file
View File

@ -0,0 +1,452 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Boundary Devices
* Copyright 2025 Collabora Ltd.
*/
/dts-v1/;
#include "imx8mp-nitrogen-som.dtsi"
/ {
model = "Boundary Devices Nitrogen8M Plus ENC Carrier Board";
compatible = "boundary,imx8mp-nitrogen-enc-carrier-board",
"boundary,imx8mp-nitrogen-som", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
reg_usb_vbus: regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_vbus>;
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&ecspi2 {
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi2>;
pinctrl-names = "default";
status = "okay";
};
&gpio1 {
usb-hub-reset-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
line-name = "usb-hub-reset";
output-low;
};
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-0 = <&pinctrl_hdmi>;
pinctrl-names = "default";
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pinctrl_i2c2_pca9546>;
pinctrl-names = "default";
reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
interrupts-extended = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rv3028>;
wakeup-source;
};
};
};
};
&i2c4 {
usb-mux@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupts-extended = <&gpio1 8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_hd3ss3220>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
};
&isp_0 {
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
assigned-clocks = <&clk IMX8MP_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_0 {
fsl,over-current-active-low;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_0>;
usb-role-switch;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
bus-width = <4>;
cd-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x143
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x100
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x119
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x41
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x41
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x41
MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x41
>;
};
pinctrl_i2c2_pca9546: i2c2-pca9546grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x100
>;
};
pinctrl_i2c4_hd3ss3220: i2c4-hd3ss3220grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x03
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x100
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0xd6
MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0xd6
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
>;
};
pinctrl_reg_usb_vbus: reg-usb-vbusgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x100
>;
};
pinctrl_rv3028: rv3028grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x1c0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
>;
};
pinctrl_usb3_0: usb3-0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x116
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4
>;
};
};

409
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi Normal file
View File

@ -0,0 +1,409 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Boundary Devices
* Copyright 2025 Collabora Ltd.
*/
#include "imx8mp.dtsi"
/ {
model = "Boundary Devices Nitrogen8M Plus Som";
compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp";
rfkill-bt {
compatible = "rfkill-gpio";
label = "rfkill-bluetooth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rfkill_bt>;
radio-type = "bluetooth";
shutdown-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
};
rfkill-wlan {
compatible = "rfkill-gpio";
label = "rfkill-wlan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rfkill_wlan>;
radio-type = "wlan";
shutdown-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
eee-broken-1000t;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 15 GPIO_OPEN_DRAIN>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio3>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
regulators {
buck1: BUCK1 {
regulator-name = "VDD_SOC (BUCK1)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDD_ARM (BUCK2)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "VDD_3P3V (BUCK4)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck5: BUCK5 {
regulator-name = "VDD_1P8V (BUCK5)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck6: BUCK6 {
regulator-name = "NVCC_DRAM_1P1V (BUCK6)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
ldo1: LDO1 {
regulator-name = "NVCC_SNVS_1V8 (LDO1)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
ldo3: LDO3 {
regulator-name = "VDDA_1V8 (LDO3)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD1 (LDO5)";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 17 GPIO_OPEN_DRAIN>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 19 GPIO_OPEN_DRAIN>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 21 GPIO_OPEN_DRAIN>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc2 {
bus-width = <4>;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
status = "okay";
};
&usdhc3 {
bus-width = <8>;
non-removable;
no-mmc-hs400;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41
>;
};
pinctrl_rfkill_bt: rfkill-btgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119
>;
};
pinctrl_rfkill_wlan: rfkill-wlangrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x10
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x150
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x150
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x150
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x150
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x150
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x150
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x150
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x150
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x150
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x14
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x154
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x154
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x154
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x154
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x154
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x154
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x154
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x154
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x154
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x12
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x152
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x152
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x152
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x152
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x152
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x152
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x152
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x152
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x152
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

796
arch/arm64/boot/dts/freescale/imx8mp-phycore-fpsc.dtsi Normal file
View File

@ -0,0 +1,796 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
*/
#include <dt-bindings/net/ti-dp83867.h>
#include "imx8mp.dtsi"
/ {
compatible = "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
model = "PHYTEC phyCORE-i.MX8MP FPSC";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x80000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDDSW_SD2";
startup-delay-us = <100>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vdd_io: regulator-vdd-io {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-name = "VDD_IO";
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&ecspi1 { /* FPSC SPI1 */
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
};
&ecspi2 { /* FPSC SPI2 */
pinctrl-0 = <&pinctrl_ecspi2>;
pinctrl-names = "default";
};
&ecspi3 { /* FPSC SPI3 */
pinctrl-0 = <&pinctrl_ecspi3>;
pinctrl-names = "default";
};
&eqos { /* FPSC RGMII2 */
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-names = "default";
};
&fec { /* FPSC GB_ETH1 */
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-names = "default";
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
};
};
};
&flexcan1 { /* FPSC CAN1 */
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default";
};
&flexcan2 { /* FPSC CAN2 */
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
};
&flexspi { /* FPSC QSPI */
pinctrl-0 = <&pinctrl_flexspi>;
pinctrl-names = "default";
};
&gpio1 {
gpio-line-names = "", "", "", "", "",
"", "", "", "PCIE1_nPERST";
};
&gpio2 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "SD2_RESET_B";
};
&gpio3 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "I2C6_SCL",
"I2C6_SDA", "I2C5_SCL";
};
&gpio4 { /* FPSC GPIO */
gpio-line-names = "GPIO6", "RGMII2_nINT", "GPIO7", "GPIO4", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "X_PMIC_IRQ_B", "",
"", "GPIO5", "", "", "RGMII2_EVENT_OUT",
"", "", "RGMII2_EVENT_IN";
pinctrl-0 = <&pinctrl_gpio4>;
pinctrl-names = "default";
};
&gpio5 { /* FPSC GPIO */
gpio-line-names = "", "", "", "", "I2C5_SDA",
"GPIO1", "", "", "", "SPI1_CS",
"", "", "", "SPI2_CS", "I2C1_SCL",
"I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA",
"", "GPIO2", "", "", "SPI3_CS",
"", "GPIO3";
pinctrl-0 = <&pinctrl_gpio5>;
pinctrl-names = "default";
};
&i2c1 { /* FPSC I2C1 */
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
regulators {
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-name = "VDD_SOC (BUCK1)";
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <850000>;
regulator-name = "VDD_ARM (BUCK2)";
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3 (BUCK4)";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8 (BUCK5)";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1155000>;
regulator-min-microvolt = <1045000>;
regulator-name = "NVCC_DRAM_1V1 (BUCK6)";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SNVS_1V8 (LDO1)";
};
ldo3: LDO3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDDA_1V8 (LDO3)";
};
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "NVCC_SD2 (LDO5)";
};
};
};
/* User EEPROM */
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&reg_vdd_io>;
};
/* factory EEPROM */
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
read-only;
vcc-supply = <&reg_vdd_io>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
};
};
&i2c2 { /* FPSC I2C2 */
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c3 { /* FPSC I2C3 */
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c5 { /* FPSC I2C4 */
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-1 = <&pinctrl_i2c5_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c6 { /* FPSC I2C5 */
pinctrl-0 = <&pinctrl_i2c6>;
pinctrl-1 = <&pinctrl_i2c6_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&iomuxc {
pinctrl_flexcan1: can1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN1_TX */
MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN1_RX */
>;
};
pinctrl_flexcan2: can2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN2_TX */
MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 /* CAN2_RX */
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* RGMII2_nINT */
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 /* RGMII2_EVENT_IN */
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10 /* RGMII2_EVENT_OUT */
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 /* RGMII2_MDIO */
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 /* RGMII2_MDC */
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 /* RGMII2_TX_D3 */
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 /* RGMII2_TX_D2 */
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 /* RGMII2_TX_D1 */
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 /* RGMII2_TX_D0 */
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 /* RGMII2_TX_CTL */
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 /* RGMII2_TXC */
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 /* RGMII2_RX_D3 */
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 /* RGMII2_RX_D2 */
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 /* RGMII2_RX_D1 */
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 /* RGMII2_RX_D0 */
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 /* RGMII2_RX_CTL */
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 /* RGMII2_RXC */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 /* QSPI_CE */
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 /* QSPI_CLK */
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 /* QSPI_DATA_0 */
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 /* QSPI_DATA_1 */
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 /* QSPI_DATA_2 */
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 /* QSPI_DATA_3 */
MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82 /* QSPI_DQS */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* GPIO4 */
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 /* GPIO5 */
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x106 /* GPIO6 */
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x106 /* GPIO7 */
>;
};
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* GPIO1 */
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x106 /* GPIO2 */
MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x106 /* GPIO3 */
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x106 /* HDMI_CEC */
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x106 /* HDMI_SCL */
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x106 /* HDMI_SDA */
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x106 /* HDMI_HPD */
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 /* I2C1_SDA_DNU */
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 /* I2C1_SCL_DNU */
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 /* I2C2_SDA */
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 /* I2C2_SCL */
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 /* I2C3_SDA */
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 /* I2C3_SCL */
>;
};
pinctrl_i2c5_gpio: i2c5gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2
>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */
MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */
>;
};
pinctrl_i2c6_gpio: i2c6gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e2
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e2
>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c2 /* I2C5_SDA */
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c2 /* I2C5_SCL */
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x10 /* PCIE1_nCLKREQ */
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* PCIE1_nPERST */
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x106 /* PWM1 */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x106 /* PWM2 */
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x106 /* PWM3 */
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x106 /* PWM4 */
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x106 /* SAI1_MCLK */
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x106 /* SAI1_RX_SYNC */
MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x106 /* SAI1_RX_BCLK */
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x106 /* SAI1_RX_DATA */
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x106 /* SAI1_TX_SYNC */
MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x106 /* SAI1_TX_BCLK */
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x106 /* SAI1_TX_DATA */
>;
};
pinctrl_ecspi1: spi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 /* SPI1_SCLK */
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 /* SPI1_MOSI */
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 /* SPI1_MISO */
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x106 /* SPI1_CS */
>;
};
pinctrl_ecspi2: spi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* SPI2_SCLK */
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* SPI2_MOSI */
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* SPI2_MISO */
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x106 /* SPI2_CS */
>;
};
pinctrl_ecspi3: spi3grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x82 /* SPI3_SCLK */
MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x82 /* SPI3_MOSI */
MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x82 /* SPI3_MISO */
MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x106 /* SPI3_CS */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x140 /* UART2_RXD */
MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x140 /* UART2_TXD */
MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x140 /* UART2_RTS */
MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x140 /* UART2_CTS */
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x140 /* UART1_RXD */
MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x140 /* UART1_TXD */
MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x140 /* UART1_RTS */
MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x140 /* UART1_CTS */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 /* UART3_RXD */
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART3_TXD */
>;
};
pinctrl_usb0: usb0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x106 /* USB1_PWR_EN */
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x106 /* USB1_OC */
MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x106 /* USB1_ID */
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x106 /* USB2_PWR_EN */
MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x106 /* USB2_OC */
MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x106 /* USB2_ID */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x106 /* SDIO_WP */
MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x106 /* SDIO_CD */
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x106 /* SDIO_CLK */
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x106 /* SDIO_CLK */
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x106 /* SDIO_DATA0 */
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x106 /* SDIO_DATA1 */
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x106 /* SDIO_DATA2 */
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x106 /* SDIO_DATA3 */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */
MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDCARD_CLK */
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDCARD_CMD */
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDCARD_DATA0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDCARD_DATA1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDCARD_DATA2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDCARD_DATA3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */
MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDCARD_CLK */
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDCARD_CMD */
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDCARD_DATA0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDCARD_DATA1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDCARD_DATA2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDCARD_DATA3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */
MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDCARD_CLK */
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDCARD_CMD */
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDCARD_DATA0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDCARD_DATA1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDCARD_DATA2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDCARD_DATA3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
>;
};
};
&pcie { /* FPSC PCIE1 */
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
};
&pwm1 { /* FPSC PWM1 */
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";
};
&pwm2 { /* FPSC PWM2 */
pinctrl-0 = <&pinctrl_pwm2>;
pinctrl-names = "default";
};
&pwm3 { /* FPSC PWM3 */
pinctrl-0 = <&pinctrl_pwm3>;
pinctrl-names = "default";
};
&pwm4 { /* FPSC PWM4 */
pinctrl-0 = <&pinctrl_pwm4>;
pinctrl-names = "default";
};
&sai5 { /* FPSC SAI1 */
pinctrl-0 = <&pinctrl_sai5>;
pinctrl-names = "default";
};
&uart2 { /* FPSC UART2 */
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
fsl,dte-mode;
};
&uart3 { /* FPSC UART1 */
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-names = "default";
fsl,dte-mode;
};
&uart4 { /* FPSC UART3 */
pinctrl-0 = <&pinctrl_uart4>;
pinctrl-names = "default";
};
&usb3_0 { /* FPSC USB1 */
pinctrl-0 = <&pinctrl_usb0>;
pinctrl-names = "default";
};
&usb3_1 { /* FPSC USB2 */
pinctrl-0 = <&pinctrl_usb1>;
pinctrl-names = "default";
};
&usdhc1 { /* FPSC SDIO */
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-names = "default";
};
&usdhc2 { /* FPSC SDCARD */
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
sd-uhs-sdr104;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&ldo5>;
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&wdog1 {
pinctrl-0 = <&pinctrl_wdog>;
pinctrl-names = "default";
fsl,ext-reset-output;
status = "okay";
};

304
arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts Normal file
View File

@ -0,0 +1,304 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (C) 2025 Toradex */
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-toradex-smarc.dtsi"
/ {
model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board";
compatible = "toradex,smarc-imx8mp-dev",
"toradex,smarc-imx8mp",
"fsl,imx8mp";
hdmi-connector {
compatible = "hdmi-connector";
label = "J64";
type = "a";
port {
native_hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
reg_carrier_1p8v: regulator-carrier-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-carrier 1V8";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "tdx-smarc-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Microphone Jack", "MICBIAS",
"IN1L", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>;
sound-dai = <&wm8904_1a>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
};
&aud2htx {
status = "okay";
};
/* SMARC SPI0 */
&ecspi1 {
status = "okay";
};
/* SMARC GBE0 */
&eqos {
status = "okay";
};
/* SMARC GBE1 */
&fec {
status = "okay";
};
/* SMARC CAN1 */
&flexcan1 {
status = "okay";
};
/* SMARC CAN0 */
&flexcan2 {
status = "okay";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio7>,
<&pinctrl_gpio8>,
<&pinctrl_gpio9>,
<&pinctrl_gpio10>,
<&pinctrl_gpio11>,
<&pinctrl_gpio12>,
<&pinctrl_gpio13>;
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_dsi_sel>;
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>;
};
&hdmi_pvi {
status = "okay";
};
/* SMARC HDMI */
&hdmi_tx {
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&native_hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
/* SMARC I2C_LCD */
&i2c2 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9543";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
/* I2C on DSI Connector Pins 4/6 */
i2c_dsi_0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* I2C on DSI Connector Pins 52/54 */
i2c_dsi_1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* SMARC I2C_CAM0 */
&i2c3 {
status = "okay";
};
/* SMARC I2C_GP */
&i2c4 {
/* Audio Codec */
wm8904_1a: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>;
clock-names = "mclk";
AVDD-supply = <&reg_carrier_1p8v>;
CPVDD-supply = <&reg_carrier_1p8v>;
DBVDD-supply = <&reg_carrier_1p8v>;
DCVDD-supply = <&reg_carrier_1p8v>;
MICVDD-supply = <&reg_carrier_1p8v>;
};
/* On-Carrier Temperature Sensor */
temperature-sensor@4f {
compatible = "ti,tmp1075";
reg = <0x4f>;
};
/* On-Carrier EEPROM */
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* SMARC I2C_CAM1 */
&i2c5 {
status = "okay";
};
/* SMARC I2C_PM */
&i2c6 {
clock-frequency = <100000>;
status = "okay";
/* Fan controller */
fan_controller: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
#pwm-cells = <2>;
fan {
pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
};
};
/* Current measurement into module VDD */
hwmon@40 {
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <5000>;
};
};
&lcdif3 {
status = "okay";
};
/* SMARC PCIE_A, M2 Key B */
&pcie {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* SMARC LCD1_BKLT_PWM */
&pwm1 {
status = "okay";
};
/* SMARC LCD0_BKLT_PWM */
&pwm2 {
status = "okay";
};
/* SMARC I2S0 */
&sai1 {
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* SMARC HDMI Audio */
&sound_hdmi {
status = "okay";
};
/* SMARC SER0, RS485. Optional M.2 KEY E */
&uart1 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* SMARC SER2 */
&uart2 {
status = "okay";
};
/* SMARC SER1, used as the Linux Console */
&uart4 {
status = "okay";
};
/* SMARC USB0 */
&usb3_0 {
status = "okay";
};
/* SMARC USB1..4 */
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* SMARC SDIO */
&usdhc2 {
status = "okay";
};

1314
arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

107
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso Normal file
View File

@ -0,0 +1,107 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
#include "imx8mp-pinfunc.h"
&{/} {
/*
* The three camera regulators are controlled by a single GPIO. Declare
* a single regulator for the three supplies.
*/
reg_cam: regulator-cam {
compatible = "regulator-fixed";
regulator-name = "reg_cam";
/* pad muxing already done in gpio2grp */
gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vcc_3v3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
cam24m: clock-cam24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "cam24m";
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
camera@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&cam24m>;
VANA-supply = <&reg_cam>;
VDIG-supply = <&reg_cam>;
VDDL-supply = <&reg_cam>;
orientation = <2>;
rotation = <0>;
port {
sony_imx219: endpoint {
remote-endpoint = <&imx8mp_mipi_csi_in>;
clock-lanes = <0>;
clock-noncontinuous;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
};
&isi_0 {
status = "disabled";
ports {
port@0 {
/delete-node/ endpoint;
};
};
};
&isp_0 {
status = "okay";
ports {
port@1 {
isp0_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
remote-endpoint = <&mipi_csi_0_out>;
};
};
};
};
&mipi_csi_0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
imx8mp_mipi_csi_in: endpoint {
remote-endpoint = <&sony_imx219>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&mipi_csi_0_out {
remote-endpoint = <&isp0_in>;
};

6
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@ -657,7 +657,7 @@
};
eeprom@50 {
compatible = "st,24c02";
compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
@ -770,7 +770,7 @@
/* EEPROM on display adapter (MIPI DSI Display Adapter) */
eeprom_display_adapter: eeprom@50 {
compatible = "st,24c02";
compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
status = "disabled";
@ -778,7 +778,7 @@
/* EEPROM on carrier board */
eeprom_carrier_board: eeprom@57 {
compatible = "st,24c02";
compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x57>;
status = "disabled";

30
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/reset/imx8mp-reset-audiomix.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interconnect/fsl,imx8mp.h>
@ -65,7 +66,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -86,7 +86,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -105,7 +104,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -124,7 +122,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -280,7 +277,7 @@
ranges;
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x2000000>;
reg = <0 0x92400000 0 0x1000000>;
no-map;
status = "disabled";
};
@ -1252,6 +1249,7 @@
reg = <0x30e60000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_MU2_ROOT>;
status = "disabled";
};
@ -2155,7 +2153,7 @@
};
};
pcie: pcie@33800000 {
pcie0: pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
@ -2193,7 +2191,7 @@
status = "disabled";
};
pcie_ep: pcie-ep@33800000 {
pcie0_ep: pcie_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mp-pcie-ep";
reg = <0x33800000 0x100000>,
<0x18000000 0x8000000>,
@ -2415,13 +2413,19 @@
};
dsp: dsp@3b6e8000 {
compatible = "fsl,imx8mp-dsp";
compatible = "fsl,imx8mp-hifi4";
reg = <0x3b6e8000 0x88000>;
mbox-names = "txdb0", "txdb1",
"rxdb0", "rxdb1";
mboxes = <&mu2 2 0>, <&mu2 2 1>,
<&mu2 3 0>, <&mu2 3 1>;
memory-region = <&dsp_reserved>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
clock-names = "ipg", "ocram", "core", "debug";
power-domains = <&pgc_audio>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>;
firmware-name = "imx/dsp/hifi4.bin";
resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>;
reset-names = "runstall";
status = "disabled";
};
};

20
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -377,6 +377,16 @@
status = "okay";
};
&pcie0_ep {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
status = "disabled";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
@ -390,6 +400,16 @@
status = "okay";
};
&pcie1_ep {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
status = "disabled";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};

40
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -106,7 +106,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -126,7 +125,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -144,7 +142,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -162,7 +159,6 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
i-cache-size = <0x8000>;
@ -1774,6 +1770,41 @@
status = "disabled";
};
pcie0_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mq-pcie-ep";
reg = <0x33800000 0x100000>,
<0x18000000 0x8000000>,
<0x33900000 0x100000>,
<0x33b00000 0x100000>;
reg-names = "dbi", "addr_space", "dbi2", "atu";
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
linux,pci-domain = <0>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
num-ib-windows = <4>;
num-ob-windows = <4>;
fsl,max-link-speed = <2>;
status = "disabled";
};
pcie1: pcie@33c00000 {
compatible = "fsl,imx8mq-pcie";
reg = <0x33c00000 0x400000>,
@ -1828,6 +1859,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
fsl,max-link-speed = <2>;
linux,pci-domain = <1>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,

10
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi
View File

@ -22,6 +22,10 @@
phy-mode = "rgmii-rxid";
};
&hsio_refa_clk {
enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>;
};
/* TODO: Apalis HDMI1 */
/* Apalis I2C2 (DDC) */
@ -188,12 +192,6 @@
"MXM3_291",
"MXM3_289",
"MXM3_287";
/* Enable pcie root / sata ref clock unconditionally */
pcie-sata-hog {
gpios = <27 GPIO_ACTIVE_HIGH>;
};
};
&lsio_gpio5 {

6
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
View File

@ -12,7 +12,7 @@
#address-cells = <1>;
#size-cells = <1>;
pciea: pcie@5f000000 {
pcie0: pciea: pcie@5f000000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f000000 0x10000>,
<0x4ff00000 0x80000>;
@ -42,7 +42,7 @@
status = "disabled";
};
pciea_ep: pcie-ep@5f000000 {
pcie0_ep: pciea_ep: pcie-ep@5f000000 {
compatible = "fsl,imx8q-pcie-ep";
reg = <0x5f000000 0x00010000>,
<0x40000000 0x10000000>;
@ -61,7 +61,7 @@
status = "disabled";
};
pcieb: pcie@5f010000 {
pcie1: pcieb: pcie@5f010000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f010000 0x10000>,
<0x8ff00000 0x80000>;

22
arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
#include <dt-bindings/phy/phy.h>
/dts-v1/;
/plugin/;
&pcieb {
status = "disabled";
};
&pcieb_ep {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
vpcie-supply = <&reg_pcieb>;
status = "okay";
};

45
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -40,24 +40,6 @@
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reserved-memory {
dsp_vdev0vring0: memory@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: memory@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: memory@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@ -189,6 +171,22 @@
no-map;
};
dsp_vdev0vring0: memory@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: memory@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: memory@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
gpu_reserved: memory@880000000 {
no-map;
reg = <0x8 0x80000000 0 0x10000000>;
@ -539,7 +537,7 @@
status = "okay";
};
&pcieb {
&pcie0 {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
@ -549,6 +547,15 @@
status = "okay";
};
&pcie0_ep {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
vpcie-supply = <&reg_pcieb>;
status = "disabled";
};
&scu_key {
status = "okay";
};

6
arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
View File

@ -38,4 +38,10 @@
power-domains = <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
pcie0: pcie@5f010000 {
};
pcie0_ep: pcie-ep@5f010000 {
};
};

16
arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps-mb-smarc-2.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include "imx8qxp-tqma8xqps.dtsi"
#include "tqma8xxs-mb-smarc-2.dtsi"
/ {
model = "TQ-Systems i.MX8QXP TQMa8XQPS on MB-SMARC-2";
compatible = "tq,imx8qxp-tqma8xqps-mb-smarc-2", "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp";
};

14
arch/arm64/boot/dts/freescale/imx8qxp-tqma8xqps.dtsi Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include "imx8qxp.dtsi"
#include "tqma8xxs.dtsi"
/ {
model = "TQ-Systems i.MX8QXP TQMa8XQPS";
compatible = "tq,imx8qxp-tqma8xqps", "fsl,imx8qxp";
};

29
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
View File

@ -52,6 +52,15 @@
regulator-name = "vref-1v8";
};
reg_module_wifi: regulator-module-wifi {
compatible = "regulator-fixed";
gpio = <&gpio_expander_43 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "Wi-Fi_PDn";
startup-delay-us = <2000>;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -261,6 +270,16 @@
};
};
&hsio_phy {
fsl,hsio-cfg = "pciea-x2-pcieb";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&hsio_refb_clk {
enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>;
};
/* Colibri SPI */
&lpspi2 {
pinctrl-names = "default";
@ -454,7 +473,15 @@
/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
/* TODO on-module PCIe for Wi-Fi */
/* On-module PCIe for Wi-Fi */
&pcieb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* On-module I2S */
&sai0 {

317
arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts Normal file
View File

@ -0,0 +1,317 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Primoz Fiser <primoz.fiser@norik.com>
*
* Product homepage:
* https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/
*/
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
#include "imx93-phycore-som.dtsi"
/ {
model = "PHYTEC phyBOARD-Nash-i.MX93";
compatible = "phytec,imx93-phyboard-nash", "phytec,imx93-phycore-som",
"fsl,imx93";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
rtc0 = &i2c_rtc;
rtc1 = &bbnsm_rtc;
};
chosen {
stdout-path = &lpuart1;
};
flexcan1_tc: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <8000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_tc>;
standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VCC_SD";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
};
reg_vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC1V8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "VREF_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
/* ADC */
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
/* Ethernet */
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
status = "okay";
};
&mdio {
ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
};
/* CAN */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
phys = <&flexcan1_tc>;
status = "okay";
};
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
/* RTC */
i2c_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
trickle-resistor-ohms = <3000>;
wakeup-source;
};
/* EEPROM */
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
vcc-supply = <&reg_vcc_1v8>;
};
};
/* SPI6 */
&lpspi6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi6>;
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
/* TPM */
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
spi-max-frequency = <10000000>;
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* RS-232/RS-485 */
&lpuart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
status = "okay";
};
/* USB */
&usbotg1 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
/* SD-Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
disable-wp;
no-mmc;
no-sdio;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x50e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x50e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1002
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
MX93_PAD_PDM_CLK__CAN1_TX 0x1382
>;
};
pinctrl_flexcan1_tc: flexcan1tcgrp {
fsl,pins = <
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpspi6: lpspi6grp {
fsl,pins = <
MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386
MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe
MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x386
MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x386
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX93_PAD_GPIO_IO17__GPIO2_IO17 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX93_PAD_GPIO_IO08__LPUART7_TX 0x30e
MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e
MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e
MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e
>;
};
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013be
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

243
arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
View File

@ -17,10 +17,38 @@
compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
"fsl,imx93";
aliases {
rtc0 = &i2c_rtc;
rtc1 = &bbnsm_rtc;
};
chosen {
stdout-path = &lpuart1;
};
flexcan1_tc: can-phy0 {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_tc>;
enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
};
reg_sound_1v8: regulator-sound-1v8 {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VCC1V8_AUDIO";
};
reg_sound_3v3: regulator-sound-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC3V3_ANALOG";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
@ -31,6 +59,93 @@
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SD";
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out",
"Speaker", "Speaker";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"Speaker", "SPOP",
"Speaker", "SPOM",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&audio_codec>;
clocks = <&clk IMX93_CLK_SAI1>;
};
};
};
/* Ethernet */
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <50000000>;
status = "okay";
};
&mdio {
ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-id0022.1561";
reg = <2>;
clocks = <&clk IMX93_CLK_ENET_REF_PHY>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
};
};
/* CAN */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
phys = <&flexcan1_tc>;
status = "okay";
};
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
/* Codec */
audio_codec: audio-codec@18 {
compatible = "ti,tlv320aic3007";
reg = <0x18>;
#sound-dai-cells = <0>;
AVDD-supply = <&reg_sound_3v3>;
IOVDD-supply = <&reg_sound_3v3>;
DRVDD-supply = <&reg_sound_3v3>;
DVDD-supply = <&reg_sound_1v8>;
};
/* RTC */
i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
};
};
/* Console */
@ -40,9 +155,28 @@
status = "okay";
};
/* eMMC */
&usdhc1 {
no-1-8-v;
/* Audio */
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <19200000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* USB */
&usbotg1 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
/* SD-Card */
@ -53,6 +187,7 @@
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
no-sdio;
vmmc-supply = <&reg_usdhc2_vmmc>;
@ -60,10 +195,36 @@
};
&iomuxc {
pinctrl_uart1: uart1grp {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000050e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e
MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
MX93_PAD_PDM_CLK__CAN1_TX 0x139e
>;
};
pinctrl_flexcan1_tc: flexcan1tcgrp {
fsl,pins = <
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x31e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
@ -73,45 +234,71 @@
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX93_PAD_UART2_RXD__SAI1_MCLK 0x1202
MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202
MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202
MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x1402
MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x1402
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
>;
};
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp {
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp {
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

165
arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
View File

@ -72,12 +72,107 @@
};
};
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDDQ_0V6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
regulator-boot-on;
regulator-always-on;
};
buck4: BUCK4 {
regulator-name = "VDD_3V3_BUCK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "VDD_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "PMIC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "VDD_0V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
/* EEPROM */
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&buck4>;
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
no-1-8-v;
status = "okay";
};
@ -104,22 +199,70 @@
pinctrl_leds: ledsgrp {
fsl,pins = <
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x11e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001386
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
>;
};

749
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts Normal file
View File

@ -0,0 +1,749 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel
* Author: Alexander Stein
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx93-tqma9352.dtsi"
/{
model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa91xxCA starter kit";
compatible = "tq,imx93-tqma9352-mba91xxca", "tq,imx93-tqma9352", "fsl,imx93";
chassis-type = "embedded";
chosen {
stdout-path = &lpuart1;
};
aliases {
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&tpm2 2 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v0>;
enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
power-supply = <&reg_3v3>;
enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
status = "disabled";
port {
panel_in: endpoint {
};
};
};
fan0: gpio-fan {
compatible = "gpio-fan";
gpios = <&expander2 4 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0>, <10000 1>;
fan-supply = <&reg_12v0>;
#cooling-cells = <2>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
switch-a {
label = "switcha";
linux,code = <BTN_0>;
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
switch-b {
label = "switchb";
linux,code = <BTN_1>;
gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led-2 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
};
lvds_encoder: lvds-encoder {
compatible = "ti,sn75lvds83", "lvds-encoder";
powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
power-supply = <&reg_3v3>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_encoder_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds_encoder_output: endpoint {
};
};
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "V_5V0_MB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "V_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_mpcie_1v5: regulator-mpcie-1v5 {
compatible = "regulator-fixed";
regulator-name = "V_1V5_MPCIE";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_mpcie_3v3: regulator-mpcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MPCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
thermal-zones {
cpu-thermal {
trips {
cpu_active: trip-active0 {
temperature = <40000>;
hysteresis = <5000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&cpu_active>;
cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
&adc1 {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy_eqos: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_fec>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy_fec: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&gpio1 {
gpio-line-names =
/* 00 */ "", "", "", "PMIC_IRQ#",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#",
/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&gpio2 {
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&gpio3 {
gpio-line-names =
/* 00 */ "SD2_CD#", "", "", "",
/* 04 */ "", "", "", "SD2_RST#",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
/* 28 */ "", "", "", "";
};
&gpio4 {
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
};
ptn5110: usb-typec@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
connector {
compatible = "usb-c-connector";
label = "X17";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
typec-power-opmode = "default";
pd-disable;
self-powered;
port {
typec_con_hs: endpoint {
remote-endpoint = <&typec_hs>;
};
};
};
};
eeprom2: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
vcc-supply = <&reg_3v3>;
};
expander0: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pexp_irq>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#",
"MPCIE_1V5_EN", "MPCIE_3V3_EN",
"MPCIE_PERST#", "MPCIE_WDISABLE#",
"BUTTON_A#", "BUTTON_B#";
temp-event-mod-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "TEMP_EVENT_MOD#";
};
mpcie-wake-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
input;
line-name = "MPCIE_WAKE#";
};
/*
* Controls the mPCIE slot reset which is low active as
* reset signal. The output-low states, the signal is
* inactive, e.g. not in reset
*/
mpcie_rst_hog: mpcie-rst-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "MPCIE_PERST#";
};
/*
* Controls the mPCIE slot WDISABLE pin which is low active
* as disable signal. The output-low states, the signal is
* inactive, e.g. not disabled
*/
mpcie_wdisable_hog: mpcie-wdisable-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "MPCIE_WDISABLE#";
};
};
expander1: gpio@71 {
compatible = "nxp,pca9538";
reg = <0x71>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
"USB_RESET#", "",
"WLAN_PD#", "WLAN_W_DISABLE#",
"WLAN_PERST#", "12V_EN";
/*
* Controls the WiFi card PD pin which is low active
* as power down signal. The output-low states, the signal
* is inactive, e.g. not power down
*/
wlan-pd-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_PD#";
};
/*
* Controls the WiFi card disable pin which is low active
* as disable signal. The output-low states, the signal
* is inactive, e.g. not disabled
*/
wlan-wdisable-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_W_DISABLE#";
};
/*
* Controls the WiFi card reset pin which is low active
* as reset signal. The output-low states, the signal
* is inactive, e.g. not in reset
*/
wlan-perst-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_PERST#";
};
};
expander2: gpio@72 {
compatible = "nxp,pca9538";
reg = <0x72>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
"LCD_BLT_EN", "LVDS_SHDN#",
"FAN_PWR_EN", "",
"USER_LED1", "USER_LED2";
};
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcf85063>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
};
&se97_som {
/* TEMP_EVENT# from SoM is connected on mainboard */
interrupt-parent = <&expander0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&tpm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm2>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
typec_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usbotg2 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb424,2517";
reg = <1>;
reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3v3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;
no-mmc;
disable-wp;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e>,
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
<MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>,
/* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>,
<MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>,
<MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>,
<MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>,
<MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>,
/* HYS | PD | FSEL_0 | DSE no drive */
<MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x1400>,
/* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e>,
<MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e>,
<MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e>,
<MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e>,
<MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e>,
/* PD | FSEL_3 | DSE X3 */
<MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e>;
};
pinctrl_eqos_phy: eqosphygrp {
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>;
};
pinctrl_fec: fecgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e>,
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
<MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e>,
/* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000>,
<MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000>,
<MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x1000>,
<MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x1000>,
<MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x1000>,
/* HYS | PD | FSEL_0 | DSE no drive */
<MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x1400>,
/* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e>,
<MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e>,
<MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e>,
<MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e>,
<MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e>,
/* PD | FSEL_3 | DSE X3 */
<MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e>;
};
pinctrl_fec_phy: fecphygrp {
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */
<MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>,
/* PU | FSEL_3 | DSE X4 */
<MX93_PAD_PDM_CLK__CAN1_TX 0x039e>;
};
pinctrl_jtag: jtaggrp {
fsl,pins = <MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>,
<MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>,
<MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>,
<MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */
<MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>,
<MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>;
};
pinctrl_pcf85063: pcf85063grp {
fsl,pins = <MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>;
};
pinctrl_pexp_irq: pexpirqgrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1000>;
};
pinctrl_rgbdisp: rgbdispgrp {
fsl,pins = <MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e>,
<MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e>,
<MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e>,
<MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e>,
<MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e>,
<MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e>,
<MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e>,
<MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e>,
<MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e>,
<MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e>,
<MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e>,
<MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e>,
<MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e>,
<MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e>,
<MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e>,
<MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e>,
<MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e>,
<MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e>,
<MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e>,
<MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e>,
<MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e>,
<MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e>,
<MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x31e>,
<MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x31e>,
<MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x31e>,
<MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x31e>,
<MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x31e>,
<MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x31e>;
};
pinctrl_touch: touchgrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000>;
};
pinctrl_tpm2: tpm2grp {
fsl,pins = <MX93_PAD_I2C2_SCL__TPM2_CH2 0x57e>;
};
pinctrl_typec: typecgrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x1000>;
};
pinctrl_uart1: uart1grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_UART1_RXD__LPUART1_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX93_PAD_UART1_TXD__LPUART1_TX 0x011e>;
};
pinctrl_uart2: uart2grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_UART2_RXD__LPUART2_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX93_PAD_UART2_TXD__LPUART2_TX 0x011e>,
/* FSEL_2 | DSE X4 */
<MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_SD2_CD_B__GPIO3_IO00 0x1000>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_hs: usdhc2hsgrp {
fsl,pins = /* PD | FSEL_3 | DSE X5 */
<MX93_PAD_SD2_CLK__USDHC2_CLK 0x05be>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
/* HYS | PU | FSEL_3 | DSE X3 */
<MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>,
<MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>,
<MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>,
<MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>,
/* FSEL_2 | DSE X3 */
<MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
fsl,pins = /* PD | FSEL_3 | DSE X6 */
<MX93_PAD_SD2_CLK__USDHC2_CLK 0x05fe>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
<MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>,
<MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>,
<MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>,
<MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>,
/* FSEL_2 | DSE X3 */
<MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
};
};

8
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
View File

@ -627,8 +627,8 @@
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
@ -659,8 +659,8 @@
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000

8
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -597,8 +597,8 @@
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
@ -629,8 +629,8 @@
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000

193
arch/arm64/boot/dts/freescale/imx94-clock.h Normal file
View File

@ -0,0 +1,193 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* Copyright 2024-2025 NXP
*/
#ifndef __IMX94_CLOCK_H
#define __IMX94_CLOCK_H
#define IMX94_CLK_EXT 0
#define IMX94_CLK_32K 1
#define IMX94_CLK_24M 2
#define IMX94_CLK_FRO 3
#define IMX94_CLK_SYSPLL1_VCO 4
#define IMX94_CLK_SYSPLL1_PFD0_UNGATED 5
#define IMX94_CLK_SYSPLL1_PFD0 6
#define IMX94_CLK_SYSPLL1_PFD0_DIV2 7
#define IMX94_CLK_SYSPLL1_PFD1_UNGATED 8
#define IMX94_CLK_SYSPLL1_PFD1 9
#define IMX94_CLK_SYSPLL1_PFD1_DIV2 10
#define IMX94_CLK_SYSPLL1_PFD2_UNGATED 11
#define IMX94_CLK_SYSPLL1_PFD2 12
#define IMX94_CLK_SYSPLL1_PFD2_DIV2 13
#define IMX94_CLK_AUDIOPLL1_VCO 14
#define IMX94_CLK_AUDIOPLL1 15
#define IMX94_CLK_AUDIOPLL2_VCO 16
#define IMX94_CLK_AUDIOPLL2 17
#define IMX94_CLK_RESERVED18 18
#define IMX94_CLK_RESERVED19 19
#define IMX94_CLK_RESERVED20 20
#define IMX94_CLK_RESERVED21 21
#define IMX94_CLK_RESERVED22 22
#define IMX94_CLK_RESERVED23 23
#define IMX94_CLK_ENCPLL_VCO 24
#define IMX94_CLK_ENCPLL_PFD0_UNGATED 25
#define IMX94_CLK_ENCPLL_PFD0 26
#define IMX94_CLK_ENCPLL_PFD1_UNGATED 27
#define IMX94_CLK_ENCPLL_PFD1 28
#define IMX94_CLK_ARMPLL_VCO 29
#define IMX94_CLK_ARMPLL_PFD0_UNGATED 30
#define IMX94_CLK_ARMPLL_PFD0 31
#define IMX94_CLK_ARMPLL_PFD1_UNGATED 32
#define IMX94_CLK_ARMPLL_PFD1 33
#define IMX94_CLK_ARMPLL_PFD2_UNGATED 34
#define IMX94_CLK_ARMPLL_PFD2 35
#define IMX94_CLK_ARMPLL_PFD3_UNGATED 36
#define IMX94_CLK_ARMPLL_PFD3 37
#define IMX94_CLK_DRAMPLL_VCO 38
#define IMX94_CLK_DRAMPLL 39
#define IMX94_CLK_HSIOPLL_VCO 40
#define IMX94_CLK_HSIOPLL 41
#define IMX94_CLK_LDBPLL_VCO 42
#define IMX94_CLK_LDBPLL 43
#define IMX94_CLK_EXT1 44
#define IMX94_CLK_EXT2 45
#define IMX94_CLK_ADC 46
#define IMX94_CLK_BUSAON 47
#define IMX94_CLK_CAN1 48
#define IMX94_CLK_GLITCHFILTER 49
#define IMX94_CLK_GPT1 50
#define IMX94_CLK_I3C1SLOW 51
#define IMX94_CLK_LPI2C1 52
#define IMX94_CLK_LPI2C2 53
#define IMX94_CLK_LPSPI1 54
#define IMX94_CLK_LPSPI2 55
#define IMX94_CLK_LPTMR1 56
#define IMX94_CLK_LPUART1 57
#define IMX94_CLK_LPUART2 58
#define IMX94_CLK_M33 59
#define IMX94_CLK_M33SYSTICK 60
#define IMX94_CLK_PDM 61
#define IMX94_CLK_SAI1 62
#define IMX94_CLK_TPM2 63
#define IMX94_CLK_A55 64
#define IMX94_CLK_A55MTRBUS 65
#define IMX94_CLK_A55PERIPH 66
#define IMX94_CLK_DRAMALT 67
#define IMX94_CLK_DRAMAPB 68
#define IMX94_CLK_DISPAPB 69
#define IMX94_CLK_DISPAXI 70
#define IMX94_CLK_DISPPIX 71
#define IMX94_CLK_HSIOACSCAN480M 72
#define IMX94_CLK_HSIOACSCAN80M 73
#define IMX94_CLK_HSIO 74
#define IMX94_CLK_HSIOPCIEAUX 75
#define IMX94_CLK_HSIOPCIETEST160M 76
#define IMX94_CLK_HSIOPCIETEST400M 77
#define IMX94_CLK_HSIOPCIETEST500M 78
#define IMX94_CLK_HSIOPCIETEST50M 79
#define IMX94_CLK_HSIOUSBTEST60M 80
#define IMX94_CLK_BUSM70 81
#define IMX94_CLK_M70 82
#define IMX94_CLK_M70SYSTICK 83
#define IMX94_CLK_BUSM71 84
#define IMX94_CLK_M71 85
#define IMX94_CLK_M71SYSTICK 86
#define IMX94_CLK_BUSNETCMIX 87
#define IMX94_CLK_ECAT 88
#define IMX94_CLK_ENET 89
#define IMX94_CLK_ENETPHYTEST200M 90
#define IMX94_CLK_ENETPHYTEST500M 91
#define IMX94_CLK_ENETPHYTEST667M 92
#define IMX94_CLK_ENETREF 93
#define IMX94_CLK_ENETTIMER1 94
#define IMX94_CLK_ENETTIMER2 95
#define IMX94_CLK_ENETTIMER3 96
#define IMX94_CLK_FLEXIO3 97
#define IMX94_CLK_FLEXIO4 98
#define IMX94_CLK_M33SYNC 99
#define IMX94_CLK_M33SYNCSYSTICK 100
#define IMX94_CLK_MAC0 101
#define IMX94_CLK_MAC1 102
#define IMX94_CLK_MAC2 103
#define IMX94_CLK_MAC3 104
#define IMX94_CLK_MAC4 105
#define IMX94_CLK_MAC5 106
#define IMX94_CLK_NOCAPB 107
#define IMX94_CLK_NOC 108
#define IMX94_CLK_NPUAPB 109
#define IMX94_CLK_NPU 110
#define IMX94_CLK_CCMCKO1 111
#define IMX94_CLK_CCMCKO2 112
#define IMX94_CLK_CCMCKO3 113
#define IMX94_CLK_CCMCKO4 114
#define IMX94_CLK_BISS 115
#define IMX94_CLK_BUSWAKEUP 116
#define IMX94_CLK_CAN2 117
#define IMX94_CLK_CAN3 118
#define IMX94_CLK_CAN4 119
#define IMX94_CLK_CAN5 120
#define IMX94_CLK_ENDAT21 121
#define IMX94_CLK_ENDAT22 122
#define IMX94_CLK_ENDAT31FAST 123
#define IMX94_CLK_ENDAT31SLOW 124
#define IMX94_CLK_FLEXIO1 125
#define IMX94_CLK_FLEXIO2 126
#define IMX94_CLK_GPT2 127
#define IMX94_CLK_GPT3 128
#define IMX94_CLK_GPT4 129
#define IMX94_CLK_HIPERFACE1 130
#define IMX94_CLK_HIPERFACE1SYNC 131
#define IMX94_CLK_HIPERFACE2 132
#define IMX94_CLK_HIPERFACE2SYNC 133
#define IMX94_CLK_I3C2SLOW 134
#define IMX94_CLK_LPI2C3 135
#define IMX94_CLK_LPI2C4 136
#define IMX94_CLK_LPI2C5 137
#define IMX94_CLK_LPI2C6 138
#define IMX94_CLK_LPI2C7 139
#define IMX94_CLK_LPI2C8 140
#define IMX94_CLK_LPSPI3 141
#define IMX94_CLK_LPSPI4 142
#define IMX94_CLK_LPSPI5 143
#define IMX94_CLK_LPSPI6 144
#define IMX94_CLK_LPSPI7 145
#define IMX94_CLK_LPSPI8 146
#define IMX94_CLK_LPTMR2 147
#define IMX94_CLK_LPUART10 148
#define IMX94_CLK_LPUART11 149
#define IMX94_CLK_LPUART12 150
#define IMX94_CLK_LPUART3 151
#define IMX94_CLK_LPUART4 152
#define IMX94_CLK_LPUART5 153
#define IMX94_CLK_LPUART6 154
#define IMX94_CLK_LPUART7 155
#define IMX94_CLK_LPUART8 156
#define IMX94_CLK_LPUART9 157
#define IMX94_CLK_SAI2 158
#define IMX94_CLK_SAI3 159
#define IMX94_CLK_SAI4 160
#define IMX94_CLK_SWOTRACE 161
#define IMX94_CLK_TPM4 162
#define IMX94_CLK_TPM5 163
#define IMX94_CLK_TPM6 164
#define IMX94_CLK_USBPHYBURUNIN 165
#define IMX94_CLK_USDHC1 166
#define IMX94_CLK_USDHC2 167
#define IMX94_CLK_USDHC3 168
#define IMX94_CLK_V2XPK 169
#define IMX94_CLK_WAKEUPAXI 170
#define IMX94_CLK_XSPISLVROOT 171
#define IMX94_CLK_XSPI1 172
#define IMX94_CLK_XSPI2 173
#define IMX94_CLK_SEL_EXT 174
#define IMX94_CLK_SEL_A55C0 175
#define IMX94_CLK_SEL_A55C1 176
#define IMX94_CLK_SEL_A55C2 177
#define IMX94_CLK_SEL_A55C3 178
#define IMX94_CLK_SEL_A55P 179
#define IMX94_CLK_SEL_DRAM 180
#define IMX94_CLK_SEL_TEMPSENSE 181
#define IMX94_CLK_NPU_CGC 182
#endif /* __IMX94_CLOCK_H */

1570
arch/arm64/boot/dts/freescale/imx94-pinfunc.h Normal file
View File

File diff suppressed because it is too large Load Diff

41
arch/arm64/boot/dts/freescale/imx94-power.h Normal file
View File

@ -0,0 +1,41 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright 2024-2025 NXP
*/
#ifndef __IMX94_POWER_H
#define __IMX94_POWER_H
#define IMX94_PD_ANA 0
#define IMX94_PD_AON 1
#define IMX94_PD_BBSM 2
#define IMX94_PD_M71 3
#define IMX94_PD_CCMSRCGPC 4
#define IMX94_PD_A55C0 5
#define IMX94_PD_A55C1 6
#define IMX94_PD_A55C2 7
#define IMX94_PD_A55C3 8
#define IMX94_PD_A55P 9
#define IMX94_PD_DDR 10
#define IMX94_PD_DISPLAY 11
#define IMX94_PD_M70 12
#define IMX94_PD_HSIO_TOP 13
#define IMX94_PD_HSIO_WAON 14
#define IMX94_PD_NETC 15
#define IMX94_PD_NOC 16
#define IMX94_PD_NPU 17
#define IMX94_PD_WAKEUP 18
#define IMX94_PERF_M33 0
#define IMX94_PERF_M33S 1
#define IMX94_PERF_WAKEUP 2
#define IMX94_PERF_M70 3
#define IMX94_PERF_M71 4
#define IMX94_PERF_DRAM 5
#define IMX94_PERF_HSIO 6
#define IMX94_PERF_NPU 7
#define IMX94_PERF_NOC 8
#define IMX94_PERF_A55 9
#define IMX94_PERF_DISP 10
#endif /* __IMX94_POWER_H */

1148
arch/arm64/boot/dts/freescale/imx94.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

195
arch/arm64/boot/dts/freescale/imx943-evk.dts Normal file
View File

@ -0,0 +1,195 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024-2025 NXP
*/
/dts-v1/;
#include "imx943.dtsi"
/ {
compatible = "fsl,imx943-evk", "fsl,imx94";
model = "NXP i.MX943 EVK board";
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_SD2_3V3";
gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7f000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
device_type = "memory";
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&scmi_iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e
IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX94_PAD_SD1_CLK__USDHC1_CLK 0x15fe
IMX94_PAD_SD1_CMD__USDHC1_CMD 0x13fe
IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX94_PAD_SD2_CLK__USDHC2_CLK 0x15fe
IMX94_PAD_SD2_CMD__USDHC2_CMD 0x13fe
IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp {
fsl,pins = <
IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e
>;
};
};
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
bus-width = <4>;
no-mmc;
no-sdio;
cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};

148
arch/arm64/boot/dts/freescale/imx943.dtsi Normal file
View File

@ -0,0 +1,148 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
#include "imx94.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX94_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l0>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x100>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX94_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l1>;
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x200>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX94_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l2>;
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x300>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX94_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l3>;
};
l2_cache_l0: l2-cache-l0 {
compatible = "cache";
cache-size = <65536>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
l2_cache_l1: l2-cache-l1 {
compatible = "cache";
cache-size = <65536>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
l2_cache_l2: l2-cache-l2 {
compatible = "cache";
cache-size = <65536>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
l2_cache_l3: l2-cache-l3 {
compatible = "cache";
cache-size = <65536>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
l3_cache: l3-cache {
compatible = "cache";
cache-size = <1048576>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <3>;
cache-unified;
};
};
};

23
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
View File

@ -136,6 +136,15 @@
startup-delay-us = <20000>;
};
reg_usb_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vcc_12v: regulator-vcc-12v {
compatible = "regulator-fixed";
regulator-max-microvolt = <12000000>;
@ -525,6 +534,13 @@
status = "okay";
};
&pcie0_ep {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
vpcie-supply = <&reg_m2_pwr>;
status = "disabled";
};
&sai1 {
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
@ -1023,6 +1039,13 @@
status = "okay";
};
&usb2 {
dr_mode = "host";
vbus-supply = <&reg_usb_vbus>;
disable-over-current;
status = "okay";
};
&usb3 {
status = "okay";
};

84
arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
#include "imx95-19x19-evk.dts"
/ {
sof_cpu: cm7-cpu@80000000 {
compatible = "fsl,imx95-cm7-sof";
reg = <0x0 0x80000000 0x0 0x6100000>;
reg-names = "sram";
memory-region = <&adma_res>;
memory-region-names = "dma";
mboxes = <&mu7 2 0>, <&mu7 2 1>, <&mu7 3 0>, <&mu7 3 1>;
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
sai3_cpu: port {
sai3_cpu_ep: endpoint {
remote-endpoint = <&wm8962_ep>;
};
};
};
reserved-memory {
adma_res: memory@86100000 {
compatible = "shared-dma-pool";
reg = <0x0 0x86100000 0x0 0x100000>;
no-map;
};
};
sof-sound {
compatible = "audio-graph-card2";
links = <&sai3_cpu>;
label = "audio";
hp-det-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hp>;
widgets = "Headphone", "Headphones",
"Microphone", "Headset Mic";
routing = "Headphones", "HPOUTL",
"Headphones", "HPOUTR",
"Headset Mic", "MICBIAS",
"IN3R", "Headset Mic",
"IN1R", "Headset Mic";
};
sound-wm8962 {
status = "disabled";
};
};
&edma2 {
/* channels 30 and 31 reserved for FW usage */
dma-channel-mask = <0xc0000000>, <0x0>;
};
&sai3 {
status = "disabled";
};
&wm8962 {
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>,
<12288000>;
port {
wm8962_ep: endpoint {
bitclock-master;
frame-master;
remote-endpoint = <&sai3_cpu_ep>;
};
};
};

30
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -145,6 +145,15 @@
off-on-delay-us = <12000>;
};
reg_usb_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&i2c7_pcal6524 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
@ -417,6 +426,13 @@
status = "okay";
};
&pcie0_ep {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
vpcie-supply = <&reg_pcie0>;
status = "disabled";
};
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
@ -425,6 +441,13 @@
status = "okay";
};
&pcie1_ep {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
vpcie-supply = <&reg_slot_pwr>;
status = "disabled";
};
&sai1 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
@ -461,6 +484,13 @@
status = "okay";
};
&usb2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usb3 {
status = "okay";
};

324
arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts Normal file
View File

@ -0,0 +1,324 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx95-tqma9596sa.dtsi"
/ {
model = "TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2";
compatible = "tq,imx95-tqma9596sa-mb-smarc-2", "tq,imx95-tqma9596sa", "fsl,imx95";
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &scmi_bbm;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
};
chosen {
stdout-path = &lpuart7;
};
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&tpm3 0 100000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_12v0>;
status = "disabled";
};
backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pwms = <&tpm4 0 100000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_12v0>;
status = "disabled";
};
panel_lvds0: panel-lvds0 {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
backlight = <&backlight_lvds0>;
power-supply = <&reg_lvds0>;
status = "disabled";
port {
panel_in_lvds0: endpoint {
/* TODO: LVDS0 out */
};
};
};
panel_lvds1: panel-lvds1 {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
backlight = <&backlight_lvds1>;
power-supply = <&reg_lvds1>;
status = "disabled";
port {
panel_in_lvds1: endpoint {
/* TODO: LVDS1 out */
};
};
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "12V0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
reg_lvds0: regulator-lvds0 {
compatible = "regulator-fixed";
regulator-name = "LCD0_VDD_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lvds1: regulator-lvds1 {
compatible = "regulator-fixed";
regulator-name = "LCD1_VDD_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander2 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
audio-codec = <&tlv320aic3x04>;
audio-cpu = <&sai3>;
};
};
&enetc_port0 {
status = "okay";
};
&enetc_port1 {
status = "okay";
};
&expander2 {
pcie1-clk-en-hog {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE1_CLK_EN";
};
pcie2-clk-en-hog {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE2_CLK_EN";
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&lpi2c1 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
iov-supply = <&reg_1v8>;
ldoin-supply = <&reg_3v3>;
};
eeprom2: eeprom@57 {
compatible = "atmel,24c32";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_3v3>;
};
};
&lpspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* SER0 */
&lpuart1 {
status = "disabled";
};
/* SER3 */
&lpuart5 {
status = "okay";
};
/* SER1 */
&lpuart7 {
status = "okay";
};
/* SER2 */
&lpuart8 {
status = "okay";
};
/* X44 mPCIe */
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&pcieclk 1>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* X22 PCIe x1 socket */
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&pcieclk 0>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
status = "okay";
};
&reg_sdvmmc {
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai5 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI5>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
};
/* X4 */
&usb2 {
srp-disable;
hnp-disable;
adp-disable;
/* DR not yet supported */
dr_mode = "peripheral";
disable-over-current;
status = "okay";
};
/* X16 */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
pinctrl-3 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_sdvmmc>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
bus-width = <4>;
status = "okay";
};

698
arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi Normal file
View File

@ -0,0 +1,698 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/usb/pd.h>
#include "imx95.dtsi"
/ {
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
};
memory@80000000 {
device_type = "memory";
/*
* DRAM base addr, size : 2048 MiB DRAM
* should be corrected by bootloader
*/
reg = <0 0x80000000 0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x28000000>;
alloc-ranges = <0 0x80000000 0 0x80000000>;
linux,cma-default;
};
vpu_boot: vpu_boot@a0000000 {
reg = <0 0xa0000000 0 0x100000>;
no-map;
};
};
clk_dp: clk-dp {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "V_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
/* Controlled by system manager */
reg_sdvmmc: regulator-sdvmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdvmmc>;
regulator-name = "SDIO_PWR_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
status = "disabled";
};
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
};
&enetc_port1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc1>;
phy-handle = <&ethphy3>;
phy-mode = "rgmii-id";
};
&netc_timer {
status = "okay";
};
&flexspi1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_flexspi1>;
pinctrl-1 = <&pinctrl_flexspi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
vcc-supply = <&reg_1v8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "GPIO7", "GPIO8",
"", "GPIO9", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>;
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "SLEEP", "GPIO5",
"", "", "GPIO6", "",
"", "", "", "",
"", "", "", "";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1>;
status = "okay";
tmp1075: temperature-sensor@4a {
compatible = "ti,tmp1075";
reg = <0x4a>;
vs-supply = <&reg_1v8>;
};
eeprom_smarc: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&reg_1v8>;
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcf85063>;
interrupt-parent = <&gpio2>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
};
m24c64: eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
vcc-supply = <&reg_1v8>;
};
/* protectable identification memory (part of M24C64-D @50) */
eeprom@58 {
compatible = "atmel,24c64d-wl";
reg = <0x58>;
vcc-supply = <&reg_1v8>;
};
/* protectable identification memory (part of M24C64-D @54) */
eeprom@5c {
compatible = "atmel,24c64d-wl";
reg = <0x5c>;
vcc-supply = <&reg_1v8>;
};
pcieclk: clock-generator@6a {
compatible = "renesas,9fgv0441";
reg = <0x6a>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
imu@6b {
compatible = "st,ism330dhcx";
reg = <0x6b>;
vdd-supply = <&reg_3v3>;
vddio-supply = <&reg_3v3>;
};
/* D23 */
expander2: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
vcc-supply = <&reg_1v8>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO4", "LCD0_BLKT_EN", "LCD0_VDD_EN", "LCD1_BLKT_EN",
"LCD1_VDD_EN", "ENET1_RESET#", "ENET2_RESET#", "GBE0_SDP_DIR",
"GBE1_SDP_DIR", "PCIE1_RST#", "PCIE2_RST#", "DP_BRIDGE_EN",
"HUB_RST#", "QSPI_RESET#", "PCIE1_CLK_EN", "PCIE2_CLK_EN";
};
/* D21 */
expander1: gpio@75 {
compatible = "ti,tca9539";
reg = <0x75>;
vcc-supply = <&reg_1v8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_expander1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
gpio-line-names = "GPIO10", "GPIO11", "GPIO12", "GPIO13",
"CHG_PRSNT#", "CHARGING", "LID", "BATLOW#",
"TEMP_EVENT#", "PGOOD_ARM", "PGOOD_SOC", "PCIE_WAKE#_1V8",
"GPIO0", "GPIO1", "GPIO2", "GPIO3";
};
};
/* I2C_CAM0 */
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
dp_bridge: dp-bridge@f {
compatible = "toshiba,tc9595", "toshiba,tc358767";
reg = <0x0f>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tc9595>;
clock-names = "ref";
clocks = <&clk_dp>;
reset-gpios = <&expander2 11 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio2>;
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
toshiba,hpd-pin = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_dsi_in: endpoint {
/* TODO: DSI out */
data-lanes = <1 2 3 4>;
};
};
};
};
};
/* I2C_CAM1 */
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c4>;
pinctrl-1 = <&pinctrl_lpi2c4>;
status = "okay";
};
/* I2C_LCD */
&lpi2c6 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c6>;
pinctrl-1 = <&pinctrl_lpi2c6>;
status = "okay";
};
/* SER0 */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
};
/* SER3 */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart5>;
};
/* SER1 */
&lpuart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart7>;
};
/* SER2 */
&lpuart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart8>;
};
&netc_blk_ctrl {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio>;
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy0>;
reset-gpios = <&expander2 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio5>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
ethphy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy3>;
reset-gpios = <&expander2 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio5>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
&scmi_bbm {
linux,code = <KEY_POWER>;
};
&tpm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm3>;
};
&tpm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm4>;
};
&tpm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm5>;
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
hub_2_0: hub@1 {
compatible = "usb451,8142";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3v3>;
};
hub_3_0: hub@2 {
compatible = "usb451,8140";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3v3>;
};
};
&usb3_phy {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&wdog3 {
status = "okay";
};
&scmi_iomuxc {
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x1100>;
};
pinctrl_ethphy3: ethphy3grp {
fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x1100>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins = <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x1100>,
<IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x1100>,
<IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x1100>,
<IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x1100>,
<IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x1100>,
<IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x1100>,
<IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x11e>,
<IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x11e>,
<IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x11e>,
<IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x11e>,
<IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x11e>,
<IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x11e>,
<IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x51e>;
};
pinctrl_enetc1: enetc1grp {
fsl,pins = <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x1100>,
<IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x1100>,
<IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x1100>,
<IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x1100>,
<IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x1100>,
<IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x1100>,
<IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x11e>,
<IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x11e>,
<IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x11e>,
<IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x11e>,
<IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x11e>,
<IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x11e>,
<IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>;
};
pinctrl_expander1: expander1grp {
fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x1100>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x1300>,
<IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x31e>;
};
pinctrl_flexcan3: flexcan3grp {
fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x31e>,
<IMX95_PAD_CCM_CLKO4__CAN3_RX 0x1300>;
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x11e>,
<IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x11e>,
<IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x11e>,
<IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x11e>,
<IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x11e>,
<IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x11e>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x111e>,
<IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x111e>,
<IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x111e>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x1100>,
<IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x111e>,
<IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x111e>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x4000191e>,
<IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x4000191e>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x4000191e>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x4000191e>;
};
pinctrl_lpi2c6: lpi2c6grp {
fsl,pins = <IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x4000191e>,
<IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x4000191e>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x51e>,
<IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x51e>,
<IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x51e>,
<IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x51e>,
<IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x51e>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x1300>,
<IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>,
<IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x1300>,
<IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x31e>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e>,
<IMX95_PAD_GPIO_IO01__LPUART5_RX 0x1300>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>,
<IMX95_PAD_GPIO_IO37__LPUART7_RX 0x1300>;
};
pinctrl_lpuart8: lpuart8grp {
fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>,
<IMX95_PAD_GPIO_IO13__LPUART8_RX 0x1300>,
<IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>,
<IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x1300>;
};
pinctrl_mdio: mdiogrp {
fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x51e>,
<IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x51e>;
};
pinctrl_pcf85063: pcf85063grp {
fsl,pins = <IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x1100>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x111e>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x111e>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x51e>,
<IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x51e>,
<IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x1300>,
<IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x51e>,
<IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x51e>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x51e>,
<IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x51e>,
<IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x51e>,
<IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x1300>;
};
pinctrl_sdvmmc: sdvmmcgrp {
fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>;
};
pinctrl_tc9595: tc9595grp {
fsl,pins = <IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x1500>;
};
pinctrl_tpm3: tpm3grp {
fsl,pins = <IMX95_PAD_GPIO_IO04__TPM3_CH0 0x51e>;
};
pinctrl_tpm4: tpm4grp {
fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x51e>;
};
pinctrl_tpm5: tpm4grp {
fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x51e>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x51e>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x31e>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x131e>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x131e>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x131e>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x131e>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
};

30
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -470,6 +470,13 @@
};
};
usbphynop: usbphynop {
compatible = "usb-nop-xceiv";
clocks = <&scmi_clk IMX95_CLK_HSIO>;
clock-names = "main_clk";
#phy-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -1621,6 +1628,29 @@
status = "disabled";
};
usb2: usb@4c200000 {
compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x0 0x4c200000 0x0 0x200>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_32K>;
clock-names = "usb_ctrl_root", "usb_wakeup";
iommus = <&smmu 0xf>;
phys = <&usbphynop>;
power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbmisc: usbmisc@4c200200 {
compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x0 0x4c200200 0x0 0x200>,
<0x0 0x4c010014 0x0 0x04>;
#index-cells = <1>;
};
pcie0: pcie@4c300000 {
compatible = "fsl,imx95-pcie";
reg = <0 0x4c300000 0 0x10000>,

5
arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
View File

@ -153,6 +153,11 @@
gpio-controller;
#gpio-cells = <2>;
};
pca85073a: rtc@51 {
compatible = "nxp,pca85073a";
reg = <0x51>;
};
};
&i2c2 {

194
arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi Normal file
View File

@ -0,0 +1,194 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/ {
aliases {
rtc0 = &rtc1;
rtc1 = &rtc;
};
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight_lvds0>;
/* PWM support still missing */
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v0>;
enable-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight_lvds1>;
/* PWM support still missing */
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v0>;
enable-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
chosen {
stdout-path = &lpuart0;
};
panel_lvds0: panel-lvds0 {
/*
* Display is not fixed, so compatible has to be added from
* DT
*/
backlight = <&backlight_lvds0>;
power-supply = <&reg_lvds0>;
status = "disabled";
port {
panel_in_lvds0: endpoint {
};
};
};
panel_lvds1: panel-lvds1 {
/*
* Display is not fixed, so compatible has to be added from
* DT
*/
backlight = <&backlight_lvds1>;
power-supply = <&reg_lvds1>;
status = "disabled";
port {
panel_in_lvds1: endpoint {
};
};
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "12V0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
ssi-controller = <&sai1>;
audio-codec = <&tlv320aic3x04>;
};
};
&fec1 {
status = "okay";
};
&fec2 {
status = "okay";
};
&flexcan2 {
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&flexcan3 {
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&i2c0 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
iov-supply = <&reg_1v8>;
ldoin-supply = <&reg_3v3>;
};
eeprom2: eeprom@57 {
compatible = "atmel,24c32";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_3v3>;
};
};
&lpspi1 {
status = "okay";
};
&lpuart0 {
status = "okay";
};
&lpuart3 {
status = "okay";
};
&reg_sdvmmc {
off-on-delay-us = <200000>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
over-current-active-low;
dr_mode = "otg";
status = "okay";
};
&usbotg3 {
status = "okay";
};
&usbotg3_cdns3 {
dr_mode = "host";
status = "okay";
};
&usb3_phy {
status = "okay";
};
&usbphy1 {
status = "okay";
};
&usdhc2 {
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sdvmmc>;
no-1-8-v;
no-mmc;
no-sdio;
status = "okay";
};

768
arch/arm64/boot/dts/freescale/tqma8xxs.dtsi Normal file
View File

@ -0,0 +1,768 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include <dt-bindings/net/ti-dp83867.h>
/delete-node/ &encoder_rpc;
/ {
memory@80000000 {
device_type = "memory";
/*
* DRAM base addr, minimal size : 1024 MiB DRAM
* should be corrected by bootloader
*/
reg = <0x00000000 0x80000000 0 0x40000000>;
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_tqma8xxs_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_lvds0: regulator-lvds0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0>;
regulator-name = "LCD0_VDD_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&lsio_gpio1 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lvds1: regulator-lvds1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1>;
regulator-name = "LCD1_VDD_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_sdvmmc: regulator-sdvmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdvmmc>;
regulator-name = "SD1_VMMC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
status = "disabled";
};
reg_vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "MMC0_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vqmmc: regulator-vqmmc {
compatible = "regulator-fixed";
regulator-name = "MMC0_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* global autoconfigured region for contiguous allocations
* must not exceed memory size and region
*/
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x20000000>;
alloc-ranges = <0 0x96000000 0 0x30000000>;
linux,cma-default;
};
decoder_boot: decoder-boot@84000000 {
reg = <0 0x84000000 0 0x2000000>;
no-map;
};
encoder_boot: encoder-boot@86000000 {
reg = <0 0x86000000 0 0x200000>;
no-map;
};
m4_reserved: m4@88000000 {
no-map;
reg = <0 0x88000000 0 0x8000000>;
status = "disabled";
};
vdev0vring0: vdev0vring0@90000000 {
compatible = "shared-dma-pool";
reg = <0 0x90000000 0 0x8000>;
no-map;
status = "disabled";
};
vdev0vring1: vdev0vring1@90008000 {
compatible = "shared-dma-pool";
reg = <0 0x90008000 0 0x8000>;
no-map;
status = "disabled";
};
vdev1vring0: vdev1vring0@90010000 {
compatible = "shared-dma-pool";
reg = <0 0x90010000 0 0x8000>;
no-map;
status = "disabled";
};
vdev1vring1: vdev1vring1@90018000 {
compatible = "shared-dma-pool";
reg = <0 0x90018000 0 0x8000>;
no-map;
status = "disabled";
};
rsc_table: rsc-table@900ff000 {
reg = <0 0x900ff000 0 0x1000>;
no-map;
status = "disabled";
};
vdevbuffer: vdevbuffer@90400000 {
compatible = "shared-dma-pool";
reg = <0 0x90400000 0 0x100000>;
no-map;
status = "disabled";
};
decoder_rpc: decoder-rpc@92000000 {
reg = <0 0x92000000 0 0x100000>;
no-map;
};
encoder_rpc: encoder-rpc@92100000 {
reg = <0 0x92100000 0 0x700000>;
no-map;
};
};
};
/* TQMa8XxS only uses industrial grade, reduce trip points accordingly */
&cpu_alert0 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <100000>;
};
/* end of temperature grade adjustments */
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
mac-address = [ 00 00 00 00 00 00 ];
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&lsio_gpio3 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&lsio_gpio1>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
};
ethphy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&lsio_gpio0 24 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&lsio_gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy3>;
fsl,magic-packet;
mac-address = [ 00 00 00 00 00 00 ];
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <66000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&lsio_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_smarc_fangpio>, <&pinctrl_smarc_mngtpio>;
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"LID", "SLEEP", "CHARGING#", "CHGPRSNT#",
"BATLOW#", "", "", "",
"", "SMARC_GPIO6", "SMARC_GPIO5", "",
"PHY3 RST#", "", "", "SPI0_CS0",
"", "SPI0_CS1", "", "";
};
&lsio_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_smarc_gpio>;
gpio-line-names = "LCD1_BLKT_EN", "LCD1_VDD_EN", "LCD0_BLKT_EN", "LCD0_VDD_EN",
"SMARC_GPIO0", "SMARC_GPIO1", "SMARC_GPIO2", "",
"SMARC_GPIO3", "SMARC_GPIO8", "SMARC_GPIO7", "SMARC_GPIO10",
"SMARC_GPIO9", "SMARC_GPIO4", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&lsio_gpio2 {
gpio-line-names = "RTC_INT#", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&lsio_gpio3 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "PHY0_RST#", "",
"", "", "", "",
"", "", "", "";
};
&lsio_gpio4 {
gpio-line-names = "PCIE_PERST#", "", "PCIE_WAKE#", "USB_OTG1_PWR",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "SDIO_PWR_EN",
"", "SDIO_WP", "SDIO_CD#", "",
"", "", "", "",
"", "", "", "";
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c0>;
pinctrl-1 = <&pinctrl_lpi2c0_gpio>;
scl-gpios = <&lsio_gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&lsio_gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* NXP SE97BTP with temperature sensor + eeprom */
sensor0: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};
eeprom0: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&reg_tqma8xxs_3v3>;
};
rtc1: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
quartz-load-femtofarads = <7000>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
eeprom1: eeprom@53 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
read-only;
vcc-supply = <&reg_tqma8xxs_3v3>;
};
pcieclk: clock-generator@6a {
compatible = "renesas,9fgv0241";
reg = <0x6a>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&lpspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
};
&mu_m0 {
status = "okay";
};
&mu1_m0 {
status = "okay";
};
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&thermal_zones {
pmic0_thermal: pmic0-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vmmc>;
vqmmc-supply = <&reg_vqmmc>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
/* NOTE: CD / WP and VMMC support depends on mainboard */
};
&vpu {
compatible = "nxp,imx8qxp-vpu";
status = "okay";
};
&vpu_core0 {
memory-region = <&decoder_boot>, <&decoder_rpc>;
status = "okay";
};
&vpu_core1 {
memory-region = <&encoder_boot>, <&encoder_rpc>;
status = "okay";
};
&iomuxc {
pinctrl_backlight_lvds0: backlight-lvds0grp {
fsl,pins = <IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021>;
};
pinctrl_backlight_lvds1: backlight-lvds1grp {
fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>;
};
pinctrl_can1: can1grp {
fsl,pins = <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>,
<IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>;
};
pinctrl_can2: can2grp {
fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021>,
<IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000040>,
<IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000040>;
};
pinctrl_ethphy1: ethphy1grp {
fsl,pins = <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000040>,
<IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 0x00000040>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>,
<IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>,
<IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>,
<IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>,
<IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>,
<IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>,
<IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>,
<IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>,
<IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>,
<IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>,
<IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>,
<IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>,
<IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>,
<IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>,
<IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>,
<IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>,
<IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0000004d>,
<IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0000004d>,
<IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0000004d>,
<IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0000004d>,
<IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0000004d>,
<IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0000004d>,
<IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0000004d>,
<IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0000004d>,
<IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0000004d>,
<IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0000004d>,
<IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0000004d>,
<IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0000004d>,
<IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0000004d>,
<IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0000004d>;
};
pinctrl_smarc_gpio: smarcgpiogrp {
fsl,pins = /* SMARC_GPIO0 / CAM0_PWR# */
<IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 0x00000021>,
/* SMARC_GPIO1 / CAM1_PWR# */
<IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 0x00000021>,
/* SMARC_GPIO2 / CAM0_RST# */
<IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 0x00000021>,
/* SMARC_GPIO3 / CAM1_RST# */
<IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x00000021>,
/* SMARC_GPIO4 / HDA_RST# */
<IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000021>,
/* SMARC_GPIO7 */
<IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0x00000021>,
/* SMARC_GPIO8 */
<IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0x00000021>,
/* SMARC_GPIO9 */
<IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 0x00000021>,
/* SMARC_GPIO10 */
<IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 0x00000021>;
};
pinctrl_smarc_fangpio: smarcfangpiogrp {
fsl,pins = /* SMARC_GPIO5 */
<IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x00000021>,
/* SMARC_GPIO6 */
<IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x00000021>;
};
pinctrl_smarc_mngtpio: smarcmngtgpiogrp {
fsl,pins = /* SMARC BATLOW# */
<IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>,
/* SMARC SLEEP */
<IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x00000021>,
/* SMARC CHGPRSNT# */
<IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 0x00000021>,
/* SMARC CHARGING# */
<IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 0x00000021>,
/* SMARC LID */
<IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000021>;
};
pinctrl_lvds0: lbdpanel0grp {
fsl,pins = /* LCD PWR */
<IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x00000021>;
};
pinctrl_lvds1: lbdpanel1grp {
fsl,pins = /* LCD PWR */
<IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x00000021>;
};
pinctrl_lpi2c0: lpi2c0grp {
fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>,
<IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>;
};
pinctrl_lpi2c0_gpio: lpi2c0gpiogrp {
fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0x00000021>,
<IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0x00000021>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>,
<IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>,
<IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>,
<IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX 0x06000020>,
<IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX 0x06000020>;
};
pinctrl_i2c0_mipi_lvds0: mipi-lvds0-i2c0grp {
fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0x06000021>,
<IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0x06000021>;
};
pinctrl_i2c0_gpio_mipi_lvds0: mipi-lvds0-i2c0-gpiogrp {
fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0x0000021>,
<IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0x0000021>;
};
pinctrl_pcieb: pcieagrp {
fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
<IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
};
pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp {
fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000021>;
};
pinctrl_pwm_mipi_lvds1: mipi-lvds1-pwmgrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000021>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000021>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>,
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>,
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>,
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>,
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>,
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>,
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>,
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>,
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>,
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040>;
};
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>;
};
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>;
};
pinctrl_sdvmmc: sdvmmcgrp {
fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021>;
};
pinctrl_spi1: spi1grp {
fsl,pins = /* PD + PDRV Low + INOUT - MEK has 0x0600004c */
<IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x06000041>,
<IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x06000041>,
<IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x06000041>,
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>,
<IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000040>,
<IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040>,
<IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040>,
<IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000040>,
<IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000040>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
<IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>,
<IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
};
pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
};
pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
};
};