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ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950

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WonderMedia WM8850/WM8950 uses an ARM PL310 cache controller for its
L2 cache, add it.

The parameters have been deduced from vendor's U-boot environment
variables, which the downstream code uses to initialize the
controller. They set the following register values:

aux = 0x3e440000
prefetch_ctrl = 0x70000007

Their initialization code also unconditionally sets the flags
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, so encode those too

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250515-wmt-dts-updates-v2-5-246937484cc8@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Alexey Charkov 2025-05-15 22:38:44 +03:00 committed by Krzysztof Kozlowski
parent 1918e51321
commit 6cd594ed96
1 changed files with 14 additions and 0 deletions
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14
arch/arm/boot/dts/vt8500/wm8850.dtsi
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@ -18,6 +18,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
next-level-cache = <&l2_cache>;
};
};
@ -308,5 +309,18 @@
reg = <0xd8004000 0x100>;
interrupts = <10>;
};
l2_cache: cache-controller@d9000000 {
compatible = "arm,pl310-cache";
reg = <0xd9000000 0x1000>;
arm,double-linefill = <1>;
arm,dynamic-clock-gating = <1>;
arm,shared-override;
arm,standby-mode = <1>;
cache-level = <2>;
cache-unified;
prefetch-data = <1>;
prefetch-instr = <1>;
};
};
};