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Samsung SoC drivers for v6.16, part two
Add CPU hotplug support on Google GS101 by toggling respective bits in secondary PMU intr block (Power Management Unit (PMU) Interrupt Generation) from the main PMU driver. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmgm9QsQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD15dgD/4oYhj8BVQP/cpb912oeBiLF3Gu1bKtv/mi rpPPmAirDH+xgwBwPGYH6TitUTv4ah+NKHguLMJCHv3IkYeBBZoT+6RWflDz2lZU lK/n1vcj0X5iWomH5d355xyNqR7SLbqWSHRadCavN9oKk9X46IZyuABnHtLwnaeI evKf+rIbXgyXd1Sa4eDPpepzrOatcWy9mb++gAjLVaCof1EAUcRmUH52rvIjC7eP mv/VKVi4fyEyC3aCss7Lz0P+S9ba1rZ5Sx6iyv/EtT/V7LNpLit1ewDr/uV3LaFi vkoPVovRby5Dc/18HUJBDOJppF35iM34Uto0kZvFZKtrHo8srPbczUQVekTgYr5F W2H0JFB32K02tgWJBSOg1sPPHqnMaUYu8fbX5jax5Tnz3oqnDqSlSJzHnTq/aDNN lhJHxzqb+DTNKZxkXIBhbnQtTBmOI5Mk2L0kt3WwNZuryT5UClSP9jEkvTrqSrym uQwpV4LuNQNHQ7ctvbZKY3/nWRXsU/VEH6oNMIouoUt+5Cok4wMZ9Gx95/by4wLL 51K0773lLrZM3jXP0cHhL+JH0nBS+Bc5w7XViMZSgmXH9W94bi+WzmJYvCBFwqUp BT3BLPL7t2D1+Gya/W0ZkMSxcvQaeuCPkrF4AtpDdFrC756eIJLJOCppfcmVyyLp fhN2H0tdmA== =5fbP -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmguQcQACgkQmmx57+YA GNn0LQ/9G0OZmOouvCPTjOmgB3k3ecBKGQUFtoLerLa5caRQstZT7z8xb1CUzh31 +P1KcRO/2PhkKEhUj7zoIDm2k2kLYq0HeIRKv2mZhcUnQ1Iac11Z++OWcchPUOtV WX/bbp9uX9QcuL0DEfsfoBgdPwXwo04Tg5u/uPluDgvlopbtp8Xq5mXP/TZmaiKY OC6UVIqZBB2l4um+B85L+FUJUqL7jtOiOwKUJs8RUh6GCdPM4r4f/QAFj8oca7Eg pkcjTkIur+dIPFbtuIggy+1pIVE8FIZ0NMr8kJkCfg39ohpdrRZuowu44jBKHP3x azyRM/rTpkOajowpZvNW6Kuxfll/amJRDtpX5/nJYPnfvF/f1ildRSfJxS9Ao4MN FKI7vtnOvjCZ33Z7PVug4zmY8Bj4y93M5jkPxIdUetj6drBDMgmRVDVusdvmlpLj +WcLOkOj+x8rPV/HZ9LVT0I+IhTQqf4KwkorzB6JLb/2i3/F8g2zLCgGPLxIrxPE 0tHUpJe8B6woneenfMw8dbOI5W5eH9HT3P89bTgdkYLqJUTgpErOTvfCjgAdsRDI eigo1X37lCToIYIZ+RJmbS6F5Wvms8SH9n96WaRxMuA4MGx2/o5zjIdvuAgaKa8Y ne6n0rJmUste7T6yKD0Vad+f0B0uuSo1g2H59lJQdq6B67p3vtQ= =u6x7 -----END PGP SIGNATURE----- Merge tag 'samsung-drivers-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers Samsung SoC drivers for v6.16, part two Add CPU hotplug support on Google GS101 by toggling respective bits in secondary PMU intr block (Power Management Unit (PMU) Interrupt Generation) from the main PMU driver. * tag 'samsung-drivers-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: soc: samsung: exynos-pmu: enable CPU hotplug support for gs101 MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation Link: https://lore.kernel.org/r/20250516082037.7248-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7148b42e85
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@ -0,0 +1,35 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Google Power Management Unit (PMU) Interrupt Generation
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description: |
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PMU interrupt generator for handshaking between PMU through interrupts.
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maintainers:
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- Peter Griffin <peter.griffin@linaro.org>
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properties:
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compatible:
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items:
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- const: google,gs101-pmu-intr-gen
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- const: syscon
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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pmu_intr_gen: syscon@17470000 {
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compatible = "google,gs101-pmu-intr-gen", "syscon";
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reg = <0x17470000 0x10000>;
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};
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@ -129,6 +129,11 @@ properties:
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description:
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Node for reboot method
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google,pmu-intr-gen-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to PMU interrupt generation interface.
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required:
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- compatible
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- reg
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@ -189,6 +194,16 @@ allOf:
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properties:
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dp-phy: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- google,gs101-pmu
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then:
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required:
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- google,pmu-intr-gen-syscon
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examples:
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- |
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#include <dt-bindings/clock/exynos5250.h>
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@ -10085,6 +10085,7 @@ L: linux-samsung-soc@vger.kernel.org
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S: Maintained
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C: irc://irc.oftc.net/pixel6-kernel-dev
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F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
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F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml
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F: arch/arm64/boot/dts/exynos/google/
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F: drivers/clk/samsung/clk-gs101.c
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F: drivers/phy/samsung/phy-gs101-ufs.c
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@ -7,6 +7,7 @@
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#include <linux/array_size.h>
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#include <linux/arm-smccc.h>
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#include <linux/cpuhotplug.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/mfd/core.h>
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@ -33,6 +34,7 @@ struct exynos_pmu_context {
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struct device *dev;
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const struct exynos_pmu_data *pmu_data;
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struct regmap *pmureg;
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struct regmap *pmuintrgen;
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};
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void __iomem *pmu_base_addr;
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@ -222,7 +224,8 @@ static const struct regmap_config regmap_smccfg = {
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};
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static const struct exynos_pmu_data gs101_pmu_data = {
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.pmu_secure = true
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.pmu_secure = true,
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.pmu_cpuhp = true,
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};
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/*
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@ -326,6 +329,59 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np,
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}
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EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle);
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/*
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* CPU_INFORM register hint values which are used by
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* EL3 firmware (el3mon).
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*/
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#define CPU_INFORM_CLEAR 0
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#define CPU_INFORM_C2 1
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static int gs101_cpuhp_pmu_online(unsigned int cpu)
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{
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unsigned int cpuhint = smp_processor_id();
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u32 reg, mask;
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/* clear cpu inform hint */
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regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
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CPU_INFORM_CLEAR);
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mask = BIT(cpu);
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regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE,
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mask, (0 << cpu));
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regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, ®);
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regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR,
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reg & mask);
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return 0;
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}
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static int gs101_cpuhp_pmu_offline(unsigned int cpu)
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{
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u32 reg, mask;
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unsigned int cpuhint = smp_processor_id();
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/* set cpu inform hint */
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regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
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CPU_INFORM_C2);
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mask = BIT(cpu);
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regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE,
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mask, BIT(cpu));
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regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®);
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regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR,
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reg & mask);
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mask = (BIT(cpu + 8));
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regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®);
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regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR,
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reg & mask);
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return 0;
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}
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static int exynos_pmu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -378,6 +434,26 @@ static int exynos_pmu_probe(struct platform_device *pdev)
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pmu_context->pmureg = regmap;
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pmu_context->dev = dev;
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if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_cpuhp) {
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pmu_context->pmuintrgen = syscon_regmap_lookup_by_phandle(dev->of_node,
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"google,pmu-intr-gen-syscon");
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if (IS_ERR(pmu_context->pmuintrgen)) {
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/*
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* To maintain support for older DTs that didn't specify syscon phandle
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* just issue a warning rather than fail to probe.
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*/
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dev_warn(&pdev->dev, "pmu-intr-gen syscon unavailable\n");
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} else {
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cpuhp_setup_state(CPUHP_BP_PREPARE_DYN,
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"soc/exynos-pmu:prepare",
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gs101_cpuhp_pmu_online, NULL);
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cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"soc/exynos-pmu:online",
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NULL, gs101_cpuhp_pmu_offline);
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}
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}
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if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
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pmu_context->pmu_data->pmu_init();
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@ -22,6 +22,7 @@ struct exynos_pmu_data {
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const struct exynos_pmu_conf *pmu_config;
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const struct exynos_pmu_conf *pmu_config_extra;
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bool pmu_secure;
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bool pmu_cpuhp;
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void (*pmu_init)(void);
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void (*powerdown_conf)(enum sys_powerdown);
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@ -658,9 +658,20 @@
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#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8)
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/* For Tensor GS101 */
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/* PMU ALIVE */
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#define GS101_SYSIP_DAT0 (0x810)
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#define GS101_CPU0_INFORM (0x860)
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#define GS101_CPU_INFORM(cpu) \
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(GS101_CPU0_INFORM + (cpu*4))
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#define GS101_SYSTEM_CONFIGURATION (0x3A00)
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#define GS101_PHY_CTRL_USB20 (0x3EB0)
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#define GS101_PHY_CTRL_USBDP (0x3EB4)
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/* PMU INTR GEN */
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#define GS101_GRP1_INTR_BID_UPEND (0x0108)
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#define GS101_GRP1_INTR_BID_CLEAR (0x010c)
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#define GS101_GRP2_INTR_BID_ENABLE (0x0200)
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#define GS101_GRP2_INTR_BID_UPEND (0x0208)
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#define GS101_GRP2_INTR_BID_CLEAR (0x020c)
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#endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
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