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mmc: sdhci-pci-gli: GL9767: Fix initializing the UHS-II interface during a power-on

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commit 77a436c93d10d68201bfd4941d1ca3230dfd1f40 upstream.

According to the power structure of IC hardware design for UHS-II
interface, reset control and timing must be added to the initialization
process of powering on the UHS-II interface.

Fixes: 27dd3b8255 ("mmc: sdhci-pci-gli: enable UHS-II mode for GL9767")
Cc: stable@vger.kernel.org # v6.13+
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ben Chuang 2025-09-11 10:42:42 +08:00 committed by Greg Kroah-Hartman
parent 7186d8e8bd
commit 7650c994ce
1 changed files with 67 additions and 1 deletions
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68
drivers/mmc/host/sdhci-pci-gli.c
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@ -283,6 +283,8 @@
#define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb
#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6)
#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1
#define PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN BIT(13)
#define PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE BIT(14)
#define GLI_MAX_TUNING_LOOP 40
@ -1179,6 +1181,65 @@ static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable)
gl9767_vhs_read(pdev);
}
static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert)
{
struct sdhci_pci_slot *slot = sdhci_priv(host);
struct pci_dev *pdev = slot->chip->pdev;
u32 value, set, clr;
if (assert) {
/* Assert reset, set RESETN and clean RESETN_VALUE */
set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
} else {
/* De-assert reset, clean RESETN and set RESETN_VALUE */
set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
}
gl9767_vhs_write(pdev);
pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
value |= set;
pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
value &= ~clr;
pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
gl9767_vhs_read(pdev);
}
static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)
{
u8 pwr = 0;
if (mode != MMC_POWER_OFF) {
pwr = sdhci_get_vdd_value(vdd);
if (!pwr)
WARN(1, "%s: Invalid vdd %#x\n",
mmc_hostname(host->mmc), vdd);
pwr |= SDHCI_VDD2_POWER_180;
}
if (host->pwr == pwr)
return;
host->pwr = pwr;
if (pwr == 0) {
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
} else {
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);
usleep_range(5000, 6250);
/* Assert reset */
sdhci_gl9767_uhs2_phy_reset(host, true);
pwr |= SDHCI_VDD2_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
usleep_range(5000, 6250);
}
}
static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pci_slot *slot = sdhci_priv(host);
@ -1205,6 +1266,11 @@ static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
}
sdhci_enable_clk(host, clk);
if (mmc_card_uhs2(host->mmc))
/* De-assert reset */
sdhci_gl9767_uhs2_phy_reset(host, false);
gl9767_set_low_power_negotiation(pdev, true);
}
@ -1476,7 +1542,7 @@ static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode,
gl9767_vhs_read(pdev);
sdhci_gli_overcurrent_event_enable(host, false);
sdhci_uhs2_set_power(host, mode, vdd);
__gl9767_uhs2_set_power(host, mode, vdd);
sdhci_gli_overcurrent_event_enable(host, true);
} else {
gl9767_vhs_write(pdev);