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Cleanups and fixes

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Merge tag 'mips_6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:
 "Cleanups and fixes"

* tag 'mips_6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: pci-legacy: Override pci_address_to_pio
  MIPS: Loongson64: env: Use str_on_off() helper in prom_lefi_init_env()
  MIPS: migrate to generic rule for built-in DTBs
  mips: fix shmctl/semctl/msgctl syscall for o32
  mips/math-emu: fix emulation of the prefx instruction
  MIPS: Loongson: Add comments for interface_info
  MIPS: Loongson64: remove ROM Size unit in boardinfo
  MIPS: traps: Use str_enabled_disabled() in parity_protection_init()
  MIPS: ftrace: Declare ftrace_get_parent_ra_addr() as static
  Revert "MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT"
  MIPS: Fix the wrong format specifier
  MIPS: Add a blank line after __HEAD
  MIPS: kernel: Rename read/write_c0_ecc to read/writec0_errctl
This commit is contained in:
Linus Torvalds 2025-01-27 09:00:25 -08:00
commit 805ba04cb7
25 changed files with 52 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/mips/Kconfig
View File

@ -29,10 +29,12 @@ config MIPS
select ARCH_WANT_IPC_PARSE_VERSION
select ARCH_WANT_LD_ORPHAN_WARN
select BUILDTIME_TABLE_SORT
select BUILTIN_DTB_ALL if BUILTIN_DTB
select CLONE_BACKWARDS
select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
select CPU_PM if CPU_IDLE || SUSPEND
select GENERIC_ATOMIC64 if !64BIT
select GENERIC_BUILTIN_DTB if BUILTIN_DTB
select GENERIC_CMOS_UPDATE
select GENERIC_CPU_AUTOPROBE
select GENERIC_GETTIMEOFDAY
@ -1084,7 +1086,6 @@ config CSRC_IOASIC
config CSRC_R4K
select CLOCKSOURCE_WATCHDOG if CPU_FREQ
select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
bool
config CSRC_SB1250

3
arch/mips/Makefile
View File

@ -423,9 +423,6 @@ endif
CLEAN_FILES += vmlinux.32 vmlinux.64
# device-trees
core-y += arch/mips/boot/dts/
archprepare:
ifdef CONFIG_MIPS32_N32
@$(kecho) ' Checking missing-syscalls for N32'

2
arch/mips/boot/dts/Makefile
View File

@ -16,5 +16,3 @@ subdir-$(CONFIG_ATH79) += qca
subdir-$(CONFIG_RALINK) += ralink
subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek
subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

2
arch/mips/boot/dts/brcm/Makefile
View File

@ -33,5 +33,3 @@ dtb-$(CONFIG_DT_NONE) += \
bcm97420c.dtb \
bcm97425svmb.dtb \
bcm97435svmb.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/cavium-octeon/Makefile
View File

@ -1,4 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/ingenic/Makefile
View File

@ -5,5 +5,3 @@ dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb
dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb
dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/lantiq/Makefile
View File

@ -1,4 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_DT_EASY50712) += danube_easy50712.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/loongson/Makefile
View File

@ -5,5 +5,3 @@ dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

3
arch/mips/boot/dts/mscc/Makefile
View File

@ -8,6 +8,3 @@ dtb-$(CONFIG_SOC_VCOREIII) += \
ocelot_pcb123.dtb \
serval_pcb105.dtb \
serval_pcb106.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/mti/Makefile
View File

@ -1,5 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/pic32/Makefile
View File

@ -3,5 +3,3 @@ dtb-$(CONFIG_DTB_PIC32_MZDA_SK) += pic32mzda_sk.dtb
dtb-$(CONFIG_DTB_PIC32_NONE) += \
pic32mzda_sk.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/mips/boot/dts/ralink/Makefile
View File

@ -10,5 +10,3 @@ dtb-$(CONFIG_SOC_MT7621) += \
mt7621-gnubee-gb-pc1.dtb \
mt7621-gnubee-gb-pc2.dtb \
mt7621-tplink-hc220-g5-v1.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

8
arch/mips/include/asm/mach-loongson64/boot_param.h
View File

@ -128,10 +128,10 @@ struct irq_source_routing_table {
} __packed;
struct interface_info {
u16 vers; /* version of the specificition */
u16 size;
u8 flag;
char description[64];
u16 vers; /* version of the specification */
u16 size; /* size of this interface */
u8 flag; /* used or unused */
char description[64]; /* description for each change */
} __packed;
#define MAX_RESOURCE_NUMBER 128

4
arch/mips/include/asm/mipsregs.h
View File

@ -2039,8 +2039,8 @@ do { \
#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_errctl() __read_32bit_c0_register($26, 0)
#define write_c0_errctl(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)

2
arch/mips/kernel/cevt-bcm1480.c
View File

@ -103,7 +103,7 @@ void sb1480_clockevent_init(void)
BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
sprintf(name, "bcm1480-counter-%d", cpu);
sprintf(name, "bcm1480-counter-%u", cpu);
cd->name = name;
cd->features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;

2
arch/mips/kernel/ftrace.c
View File

@ -248,7 +248,7 @@ int ftrace_disable_ftrace_graph_caller(void)
#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
static unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
old_parent_ra, unsigned long parent_ra_addr, unsigned long fp)
{
unsigned long sp, ip, tmp;

1
arch/mips/kernel/head.S
View File

@ -60,6 +60,7 @@
.endm
__HEAD
#ifndef CONFIG_NO_EXCEPT_FILL
/*
* Reserved space for exception handlers.

7
arch/mips/kernel/mips-mt.c
View File

@ -122,9 +122,8 @@ void mips_mt_set_cpuoptions(void)
unsigned long ectlval;
unsigned long itcblkgrn;
/* ErrCtl register is known as "ecc" to Linux */
ectlval = read_c0_ecc();
write_c0_ecc(ectlval | (0x1 << 26));
ectlval = read_c0_errctl();
write_c0_errctl(ectlval | (0x1 << 26));
ehb();
#define INDEX_0 (0x80000000)
#define INDEX_8 (0x80000008)
@ -145,7 +144,7 @@ void mips_mt_set_cpuoptions(void)
ehb();
/* Write out to ITU with CACHE op */
cache_op(Index_Store_Tag_D, INDEX_0);
write_c0_ecc(ectlval);
write_c0_errctl(ectlval);
ehb();
printk("Mapped %ld ITC cells starting at 0x%08x\n",
((itcblkgrn & 0x7fe00000) >> 20), itc_base);

4
arch/mips/kernel/spram.c
View File

@ -26,10 +26,6 @@
#define ERRCTL_SPRAM (1 << 28)
/* errctl access */
#define read_c0_errctl(x) read_c0_ecc(x)
#define write_c0_errctl(x) write_c0_ecc(x)
/*
* Different semantics to the set_c0_* function built by __BUILD_SET_C0
*/

6
arch/mips/kernel/syscalls/syscall_o32.tbl
View File

@ -382,15 +382,15 @@
368 o32 io_pgetevents sys_io_pgetevents_time32 compat_sys_io_pgetevents
# room for arch specific calls
393 o32 semget sys_semget
394 o32 semctl sys_semctl compat_sys_semctl
394 o32 semctl sys_old_semctl compat_sys_old_semctl
395 o32 shmget sys_shmget
396 o32 shmctl sys_shmctl compat_sys_shmctl
396 o32 shmctl sys_old_shmctl compat_sys_old_shmctl
397 o32 shmat sys_shmat compat_sys_shmat
398 o32 shmdt sys_shmdt
399 o32 msgget sys_msgget
400 o32 msgsnd sys_msgsnd compat_sys_msgsnd
401 o32 msgrcv sys_msgrcv compat_sys_msgrcv
402 o32 msgctl sys_msgctl compat_sys_msgctl
402 o32 msgctl sys_old_msgctl compat_sys_old_msgctl
403 o32 clock_gettime64 sys_clock_gettime sys_clock_gettime
404 o32 clock_settime64 sys_clock_settime sys_clock_settime
405 o32 clock_adjtime64 sys_clock_adjtime sys_clock_adjtime

47
arch/mips/kernel/traps.c
View File

@ -38,6 +38,7 @@
#include <linux/kdb.h>
#include <linux/irq.h>
#include <linux/perf_event.h>
#include <linux/string_choices.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
@ -1705,10 +1706,10 @@ static inline __init void parity_protection_init(void)
l2parity &= l1parity;
/* Probe L1 ECC support */
cp0_ectl = read_c0_ecc();
write_c0_ecc(cp0_ectl | ERRCTL_PE);
cp0_ectl = read_c0_errctl();
write_c0_errctl(cp0_ectl | ERRCTL_PE);
back_to_back_c0_hazard();
cp0_ectl = read_c0_ecc();
cp0_ectl = read_c0_errctl();
/* Probe L2 ECC support */
gcr_ectl = read_gcr_err_control();
@ -1727,9 +1728,9 @@ static inline __init void parity_protection_init(void)
cp0_ectl |= ERRCTL_PE;
else
cp0_ectl &= ~ERRCTL_PE;
write_c0_ecc(cp0_ectl);
write_c0_errctl(cp0_ectl);
back_to_back_c0_hazard();
WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
WARN_ON(!!(read_c0_errctl() & ERRCTL_PE) != l1parity);
/* Configure L2 ECC checking */
if (l2parity)
@ -1741,8 +1742,8 @@ static inline __init void parity_protection_init(void)
gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
WARN_ON(!!gcr_ectl != l2parity);
pr_info("Cache parity protection %sabled\n",
l1parity ? "en" : "dis");
pr_info("Cache parity protection %s\n",
str_enabled_disabled(l1parity));
return;
}
@ -1761,18 +1762,18 @@ static inline __init void parity_protection_init(void)
unsigned long errctl;
unsigned int l1parity_present, l2parity_present;
errctl = read_c0_ecc();
errctl = read_c0_errctl();
errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
/* probe L1 parity support */
write_c0_ecc(errctl | ERRCTL_PE);
write_c0_errctl(errctl | ERRCTL_PE);
back_to_back_c0_hazard();
l1parity_present = (read_c0_ecc() & ERRCTL_PE);
l1parity_present = (read_c0_errctl() & ERRCTL_PE);
/* probe L2 parity support */
write_c0_ecc(errctl|ERRCTL_L2P);
write_c0_errctl(errctl|ERRCTL_L2P);
back_to_back_c0_hazard();
l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
l2parity_present = (read_c0_errctl() & ERRCTL_L2P);
if (l1parity_present && l2parity_present) {
if (l1parity)
@ -1791,20 +1792,20 @@ static inline __init void parity_protection_init(void)
printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
write_c0_ecc(errctl);
write_c0_errctl(errctl);
back_to_back_c0_hazard();
errctl = read_c0_ecc();
errctl = read_c0_errctl();
printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
if (l1parity_present)
printk(KERN_INFO "Cache parity protection %sabled\n",
(errctl & ERRCTL_PE) ? "en" : "dis");
pr_info("Cache parity protection %s\n",
str_enabled_disabled(errctl & ERRCTL_PE));
if (l2parity_present) {
if (l1parity_present && l1parity)
errctl ^= ERRCTL_L2P;
printk(KERN_INFO "L2 cache parity protection %sabled\n",
(errctl & ERRCTL_L2P) ? "en" : "dis");
pr_info("L2 cache parity protection %s\n",
str_enabled_disabled(errctl & ERRCTL_L2P));
}
}
break;
@ -1812,11 +1813,11 @@ static inline __init void parity_protection_init(void)
case CPU_5KC:
case CPU_5KE:
case CPU_LOONGSON32:
write_c0_ecc(0x80000000);
write_c0_errctl(0x80000000);
back_to_back_c0_hazard();
/* Set the PE bit (bit 31) in the c0_errctl register. */
printk(KERN_INFO "Cache parity protection %sabled\n",
(read_c0_ecc() & 0x80000000) ? "en" : "dis");
pr_info("Cache parity protection %s\n",
str_enabled_disabled(read_c0_errctl() & 0x80000000));
break;
case CPU_20KC:
case CPU_25KF:
@ -1887,8 +1888,8 @@ asmlinkage void do_ftlb(void)
if ((cpu_has_mips_r2_r6) &&
(((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
read_c0_ecc());
pr_err("FTLB error exception, cp0_errctl=0x%08x:\n",
read_c0_errctl());
pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
reg_val = read_c0_cacheerr();
pr_err("c0_cacheerr == %08x\n", reg_val);

2
arch/mips/loongson64/boardinfo.c
View File

@ -21,13 +21,11 @@ static ssize_t boardinfo_show(struct kobject *kobj,
"BIOS Info\n"
"Vendor\t\t\t: %s\n"
"Version\t\t\t: %s\n"
"ROM Size\t\t: %d KB\n"
"Release Date\t\t: %s\n",
strsep(&tmp_board_manufacturer, "-"),
eboard->name,
strsep(&tmp_bios_vendor, "-"),
einter->description,
einter->size,
especial->special_name);
}
static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444,

3
arch/mips/loongson64/env.c
View File

@ -17,6 +17,7 @@
#include <linux/dma-map-ops.h>
#include <linux/export.h>
#include <linux/pci_ids.h>
#include <linux/string_choices.h>
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
@ -162,7 +163,7 @@ void __init prom_lefi_init_env(void)
dma_default_coherent = !eirq_source->dma_noncoherent;
}
pr_info("Firmware: Coherent DMA: %s\n", dma_default_coherent ? "on" : "off");
pr_info("Firmware: Coherent DMA: %s\n", str_on_off(dma_default_coherent));
loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;

2
arch/mips/math-emu/cp1emu.c
View File

@ -1660,7 +1660,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
break;
}
case 0x3:
case 0x7:
if (MIPSInst_FUNC(ir) != pfetch_op)
return SIGILL;

8
arch/mips/pci/pci-legacy.c
View File

@ -29,6 +29,14 @@ static LIST_HEAD(controllers);
static int pci_initialized;
unsigned long pci_address_to_pio(phys_addr_t address)
{
if (address > IO_SPACE_LIMIT)
return (unsigned long)-1;
return (unsigned long) address;
}
/*
* We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the