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RISC-V: KVM: Move copy_sbi_ext_reg_indices() to SBI implementation
The ONE_REG handling of SBI extension enable/disable registers and SBI extension state registers is already under SBI implementation. On similar lines, let's move copy_sbi_ext_reg_indices() under SBI implementation. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250823155947.1354229-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
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@ -77,6 +77,7 @@ void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu,
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unsigned long pc, unsigned long a1);
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void kvm_riscv_vcpu_sbi_load_reset_state(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
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int kvm_riscv_vcpu_reg_indices_sbi_ext(struct kvm_vcpu *vcpu, u64 __user *uindices);
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int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg);
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int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
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@ -86,7 +87,6 @@ int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one_reg *
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int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
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struct kvm_vcpu *vcpu, unsigned long extid);
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bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx);
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int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
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void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu);
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@ -1082,34 +1082,9 @@ static inline unsigned long num_isa_ext_regs(const struct kvm_vcpu *vcpu)
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return copy_isa_ext_reg_indices(vcpu, NULL);
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}
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static int copy_sbi_ext_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
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{
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unsigned int n = 0;
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for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) {
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u64 size = IS_ENABLED(CONFIG_32BIT) ?
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KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
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u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
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KVM_REG_RISCV_SBI_SINGLE | i;
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if (!riscv_vcpu_supports_sbi_ext(vcpu, i))
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continue;
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if (uindices) {
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if (put_user(reg, uindices))
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return -EFAULT;
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uindices++;
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}
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n++;
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}
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return n;
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}
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static unsigned long num_sbi_ext_regs(struct kvm_vcpu *vcpu)
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{
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return copy_sbi_ext_reg_indices(vcpu, NULL);
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return kvm_riscv_vcpu_reg_indices_sbi_ext(vcpu, NULL);
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}
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static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu)
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@ -1237,7 +1212,7 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,
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return ret;
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uindices += ret;
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ret = copy_sbi_ext_reg_indices(vcpu, uindices);
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ret = kvm_riscv_vcpu_reg_indices_sbi_ext(vcpu, uindices);
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if (ret < 0)
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return ret;
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uindices += ret;
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@ -110,7 +110,7 @@ riscv_vcpu_get_sbi_ext(struct kvm_vcpu *vcpu, unsigned long idx)
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return sext;
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}
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bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx)
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static bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx)
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{
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struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
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const struct kvm_riscv_sbi_extension_entry *sext;
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@ -288,6 +288,31 @@ static int riscv_vcpu_get_sbi_ext_multi(struct kvm_vcpu *vcpu,
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return 0;
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}
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int kvm_riscv_vcpu_reg_indices_sbi_ext(struct kvm_vcpu *vcpu, u64 __user *uindices)
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{
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unsigned int n = 0;
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for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) {
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u64 size = IS_ENABLED(CONFIG_32BIT) ?
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KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
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u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
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KVM_REG_RISCV_SBI_SINGLE | i;
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if (!riscv_vcpu_supports_sbi_ext(vcpu, i))
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continue;
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if (uindices) {
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if (put_user(reg, uindices))
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return -EFAULT;
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uindices++;
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}
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n++;
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}
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return n;
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}
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int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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