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drm/panel-samsung-s6e88a0-ams452ef01: Drop custom DSI write macro
There is a macro for this already in the <drm/drm_mipi_dsi.h> header, use that instead and delete the custom DSI write macro defined in the driver. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230107191822.3787147-9-javierm@redhat.com
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@ -28,14 +28,6 @@ s6e88a0_ams452ef01 *to_s6e88a0_ams452ef01(struct drm_panel *panel)
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return container_of(panel, struct s6e88a0_ams452ef01, panel);
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}
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#define dsi_dcs_write_seq(dsi, seq...) do { \
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static const u8 d[] = { seq }; \
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int ret; \
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ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
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if (ret < 0) \
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return ret; \
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} while (0)
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static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 *ctx)
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{
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gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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@ -54,8 +46,8 @@ static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx)
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dsi->mode_flags |= MIPI_DSI_MODE_LPM;
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dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands
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dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity
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mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands
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mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity
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ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
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if (ret < 0) {
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@ -65,23 +57,23 @@ static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx)
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msleep(120);
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// set default brightness/gama
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dsi_dcs_write_seq(dsi, 0xca,
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0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB
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0x80, 0x80, 0x80, // V203 R,G,B
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0x80, 0x80, 0x80, // V151 R,G,B
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0x80, 0x80, 0x80, // V87 R,G,B
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0x80, 0x80, 0x80, // V51 R,G,B
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0x80, 0x80, 0x80, // V35 R,G,B
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0x80, 0x80, 0x80, // V23 R,G,B
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0x80, 0x80, 0x80, // V11 R,G,B
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0x6b, 0x68, 0x71, // V3 R,G,B
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0x00, 0x00, 0x00); // V1 R,G,B
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mipi_dsi_dcs_write_seq(dsi, 0xca,
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0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB
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0x80, 0x80, 0x80, // V203 R,G,B
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0x80, 0x80, 0x80, // V151 R,G,B
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0x80, 0x80, 0x80, // V87 R,G,B
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0x80, 0x80, 0x80, // V51 R,G,B
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0x80, 0x80, 0x80, // V35 R,G,B
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0x80, 0x80, 0x80, // V23 R,G,B
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0x80, 0x80, 0x80, // V11 R,G,B
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0x6b, 0x68, 0x71, // V3 R,G,B
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0x00, 0x00, 0x00); // V1 R,G,B
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// set default Amoled Off Ratio
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dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a);
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dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage
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dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
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dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update
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dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands
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mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a);
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mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage
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mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
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mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update
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mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands
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ret = mipi_dsi_dcs_set_display_on(dsi);
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if (ret < 0) {
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