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This is the bulk of pin control changes for the v6.12 kernel cycle:

Browse Source 
Core changes:
 
 - Add support for "input-schmitt-microvolt" property, as used in the
   Sophgo SoC.
 
 New drivers:
 
 - Mobileye EyeQ5 pin controller, I think this is an automotive SoC.
 
 - Rockchip rk3576 pin control support.
 
 - Sophgo CV1800 series pin controllers: CV1800B, CV1812H and SG2000.
 
 Improvements:
 
 - Gradual improvements to Renesas, Samsung, Qualcomm, Nuvoton
   and a few other drivers.
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Merge tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Add support for "input-schmitt-microvolt" property, as used in the
     Sophgo SoC

  New drivers:

   - Mobileye EyeQ5 pin controller, I think this is an automotive SoC

   - Rockchip rk3576 pin control support

   - Sophgo CV1800 series pin controllers: CV1800B, CV1812H and SG2000

  Improvements:

   - Gradual improvements to Renesas, Samsung, Qualcomm, Nuvoton and a
     few other drivers"

* tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (67 commits)
  pinctrl: intel: Constify struct intel_pinctrl parameter
  pinctrl: Remove redundant null pointer checks in pinctrl_remove_device_debugfs()
  pinctrl: baytrail: Drop duplicate return statement
  pinctrl: intel: Inline intel_gpio_community_irq_handler()
  dt-bindings: pinctrl: qcom: add missing type to GPIO hogs
  pinctrl: madera: Simplify with dev_err_probe()
  pinctrl: k210: Use devm_clk_get_enabled() helpers
  pinctrl: Join split messages and remove double whitespace
  pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases
  pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration
  pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API
  pinctrl: mvebu: Fix devinit_dove_pinctrl_probe function
  pinctrl: sunxi: Use devm_clk_get_enabled() helpers
  pinctrl: sophgo: cv18xx: fix missed __iomem type identifier
  pinctrl: stmfx: Use string_choices API instead of ternary operator
  pinctrl: nomadik: Use kmemdup_array instead of kmemdup for multiple allocation
  pinctrl: intel: Introduce for_each_intel_gpio_group() helper et al.
  pinctrl: intel: Constify intel_get_community() returned object
  pinctrl: intel: Implement high impedance support
  pinctrl: intel: Add __intel_gpio_get_direction() helper
  ...
This commit is contained in:
Linus Torvalds 2024-09-23 13:15:23 -07:00
commit 962ad08780
84 changed files with 6002 additions and 1275 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

242
Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml
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@ -1,242 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mobileye EyeQ5 pin controller
description: >
The EyeQ5 pin controller handles the two pin banks of the system. It belongs
to a system-controller block called OLB.
Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin
muxing supports two functions for each pin: first is GPIO, second is
pin-dependent.
Pins and groups are bijective.
maintainers:
- Grégory Clement <gregory.clement@bootlin.com>
- Théo Lebrun <theo.lebrun@bootlin.com>
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
$ref: pinctrl.yaml#
properties:
compatible:
enum:
- mobileye,eyeq5-pinctrl
reg:
maxItems: 1
patternProperties:
"-pins?$":
type: object
description: Pin muxing configuration.
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
pins: true
function:
enum: [gpio,
# Bank A
timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
spi1, refclk0,
# Bank B
timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
required:
- pins
- function
allOf:
- if:
properties:
function:
const: gpio
then:
properties:
pins:
items: # PA0 - PA28, PB0 - PB22
pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
- if:
properties:
function:
const: timer0
then:
properties:
pins:
items:
enum: [PA0, PA1]
- if:
properties:
function:
const: timer1
then:
properties:
pins:
items:
enum: [PA2, PA3]
- if:
properties:
function:
const: timer2
then:
properties:
pins:
items:
enum: [PA4, PA5]
- if:
properties:
function:
const: timer5
then:
properties:
pins:
items:
enum: [PA6, PA7, PA8, PA9]
- if:
properties:
function:
const: uart0
then:
properties:
pins:
items:
enum: [PA10, PA11]
- if:
properties:
function:
const: uart1
then:
properties:
pins:
items:
enum: [PA12, PA13]
- if:
properties:
function:
const: can0
then:
properties:
pins:
items:
enum: [PA14, PA15]
- if:
properties:
function:
const: can1
then:
properties:
pins:
items:
enum: [PA16, PA17]
- if:
properties:
function:
const: spi0
then:
properties:
pins:
items:
enum: [PA18, PA19, PA20, PA21, PA22]
- if:
properties:
function:
const: spi1
then:
properties:
pins:
items:
enum: [PA23, PA24, PA25, PA26, PA27]
- if:
properties:
function:
const: refclk0
then:
properties:
pins:
items:
enum: [PA28]
- if:
properties:
function:
const: timer3
then:
properties:
pins:
items:
enum: [PB0, PB1]
- if:
properties:
function:
const: timer4
then:
properties:
pins:
items:
enum: [PB2, PB3]
- if:
properties:
function:
const: timer6
then:
properties:
pins:
items:
enum: [PB4, PB5, PB6, PB7]
- if:
properties:
function:
const: uart2
then:
properties:
pins:
items:
enum: [PB8, PB9]
- if:
properties:
function:
const: can2
then:
properties:
pins:
items:
enum: [PB10, PB11]
- if:
properties:
function:
const: spi2
then:
properties:
pins:
items:
enum: [PB12, PB13, PB14, PB15, PB16]
- if:
properties:
function:
const: spi3
then:
properties:
pins:
items:
enum: [PB17, PB18, PB19, PB20, PB21]
- if:
properties:
function:
const: mclk0
then:
properties:
pins:
items:
enum: [PB22]
required:
- compatible
- reg
additionalProperties: false

70
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
View File

@ -71,51 +71,49 @@ patternProperties:
One or more groups of pins to mux to a certain function
items:
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
bu4b, bu5, bu5b, bu6, gpo187 ]
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]
function:
description:
The function that a group of pins is muxed to
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
bu4b, bu5, bu5b, bu6, gpo187 ]
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
bu6, gpo187 ]
dependencies:
groups: [ function ]

3
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
View File

@ -96,6 +96,9 @@ properties:
type: boolean
description: disable schmitt-trigger mode
input-schmitt-microvolt:
description: threshold strength for schmitt-trigger
input-debounce:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Takes the debounce time in usec as argument or 0 to disable

95
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
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@ -1,95 +0,0 @@
Qualcomm APQ8064 TLMM block
Required properties:
- compatible: "qcom,apq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for pins are:
gpio0-gpio89
Valid values for function are:
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,apq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gpio-ranges = <&msmgpio 0 0 90>;
gsbi5_uart_default: gsbi5_uart_default {
mux {
pins = "gpio51", "gpio52";
function = "gsbi5";
};
tx {
pins = "gpio51";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio52";
drive-strength = <2>;
bias-pull-up;
};
};
};

110
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml Normal file
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@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. APQ8064 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,apq8064-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-apq8064-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-apq8064-tlmm-state"
additionalProperties: false
$defs:
qcom-apq8064-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-8][0-9])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a,
gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b,
gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c,
gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3,
gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3,
gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3,
gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan,
sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
ps_hold ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@800000 {
compatible = "qcom,apq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 90>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio52";
function = "gsbi5";
bias-pull-up;
};
tx-pins {
pins = "gpio51";
function = "gsbi5";
bias-disable;
};
};
};

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Qualcomm APQ8084 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,apq8084-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio146,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc2_clk,
sdc2_cmd,
sdc2_data
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
tsif2, uim, uim_batt_alarm
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 147>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
uart2: uart2-default {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. APQ8084 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,apq8084-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-apq8084-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-apq8084-tlmm-state"
additionalProperties: false
$defs:
qcom-apq8084-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6,
blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10,
blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2,
blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7,
blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
cci_timer0, cci_timer1, cci_timer2, cci_timer3,
cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3,
gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2,
gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest,
hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update,
mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1,
pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s,
tsif1, tsif2, uim, uim_batt_alarm ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 147>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio5";
function = "blsp_uart2";
bias-pull-up;
};
tx-pins {
pins = "gpio4";
function = "blsp_uart2";
bias-disable;
};
};
};

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Qualcomm Atheros IPQ4019 TLMM block
This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
Required properties:
- compatible: "qcom,ipq4019-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
drive-strength.
Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
Valid values for qcom,pins are:
gpio0-gpio99
Supports mux, bias and drive-strength
Valid values for qcom,function are:
aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x1000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. IPQ4019 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq4019-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq4019-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq4019-tlmm-state"
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
$defs:
qcom-ipq4019-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-9][0-9])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0,
blsp_spi1, blsp_uart0, blsp_uart1, chip_rst, gpio,
i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7,
led8, led9, led10, led11, mdc, mdio, pcie, pmu,
prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1 ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};

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Qualcomm IPQ8064 TLMM block
Required properties:
- compatible: "qcom,ipq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for qcom,pins are:
gpio0-gpio68
Supports mux, bias, and drive-strength
sdc3_clk, sdc3_cmd, sdc3_data
Supports bias and drive-strength
Valid values for function are:
mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
Example:
pinmux: pinctrl@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 0 69>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 32 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gsbi5_uart_default: gsbi5_uart_default {
mux {
pins = "gpio18", "gpio19";
function = "gsbi5";
};
tx {
pins = "gpio18";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio19";
drive-strength = <2>;
bias-pull-up;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. IPQ8064 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq8064-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq8064-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq8064-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq8064-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$"
- enum: [ sdc3_clk, sdc3_cmd, sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x00800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 69>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart-state {
rx-pins {
pins = "gpio19";
function = "gsbi5";
bias-pull-up;
};
tx-pins {
pins = "gpio18";
function = "gsbi5";
bias-disable;
};
};
};

1
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -425,6 +425,7 @@ patternProperties:
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog

1
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
View File

@ -43,6 +43,7 @@ patternProperties:
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog

1
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View File

@ -25,6 +25,7 @@ properties:
- renesas,pfc-r8a7745 # RZ/G1E
- renesas,pfc-r8a77470 # RZ/G1C
- renesas,pfc-r8a774a1 # RZ/G2M
- renesas,pfc-r8a774a3 # RZ/G2M v3.0
- renesas,pfc-r8a774b1 # RZ/G2N
- renesas,pfc-r8a774c0 # RZ/G2E
- renesas,pfc-r8a774e1 # RZ/G2H

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
View File

@ -45,6 +45,7 @@ properties:
- rockchip,rk3368-pinctrl
- rockchip,rk3399-pinctrl
- rockchip,rk3568-pinctrl
- rockchip,rk3576-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
- rockchip,rv1126-pinctrl

122
Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml Normal file
View File

@ -0,0 +1,122 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo CV1800 Pin Controller
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
enum:
- sophgo,cv1800b-pinctrl
- sophgo,cv1812h-pinctrl
- sophgo,sg2000-pinctrl
- sophgo,sg2002-pinctrl
reg:
items:
- description: pinctrl for system domain
- description: pinctrl for rtc domain
reg-names:
items:
- const: sys
- const: rtc
resets:
maxItems: 1
patternProperties:
'-cfg$':
type: object
description:
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine.
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
Each subnode will list the pins it needs, and how they should
be configured, with regard to muxer configuration, bias, input
enable/disable, input schmitt trigger, slew-rate, drive strength
and bus hold state. In addition, all pins in the same subnode
should have the same power domain. For configuration detail,
refer to https://github.com/sophgo/sophgo-doc/.
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pinmux:
description: |
The list of GPIOs and their mux settings that properties in the
node apply to. This should be set using the GPIOMUX or GPIOMUX2
macro.
bias-pull-up:
type: boolean
bias-pull-down:
type: boolean
drive-strength-microamp:
description: typical current when output high level.
input-schmitt-microvolt:
description: typical threshold for schmitt trigger.
power-source:
description: power supplies at X mV.
enum: [ 1800, 3300 ]
slew-rate:
description: slew rate for output buffer (0 is fast, 1 is slow)
enum: [ 0, 1 ]
bias-bus-hold: true
required:
- pinmux
- power-source
additionalProperties: false
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
pinctrl@3001000 {
compatible = "sophgo,cv1800b-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
input-schmitt-microvolt = <0>;
power-source = <3300>;
slew-rate = <0>;
};
};
};
...

16
drivers/pinctrl/Kconfig
View File

@ -213,6 +213,21 @@ config PINCTRL_EQUILIBRIUM
desired pin functions, configure GPIO attributes for LGM SoC pins.
Pin muxing and pin config settings are retrieved from device tree.
config PINCTRL_EYEQ5
bool "Mobileye EyeQ5 pinctrl driver"
depends on OF
depends on MACH_EYEQ5 || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select AUXILIARY_BUS
default MACH_EYEQ5
help
Pin controller driver for the Mobileye EyeQ5 platform. It does both
pin config & pin muxing. It does not handle GPIO.
Pin muxing supports two functions for each pin: first is GPIO, second
is pin-dependent. Pin config is about bias & drive strength.
config PINCTRL_GEMINI
bool
depends on ARCH_GEMINI
@ -583,6 +598,7 @@ source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/realtek/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sophgo/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/starfive/Kconfig"

2
drivers/pinctrl/Makefile
View File

@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
@ -73,6 +74,7 @@ obj-y += qcom/
obj-$(CONFIG_ARCH_REALTEK) += realtek/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-y += sophgo/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_SOC_STARFIVE) += starfive/

1
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -1280,6 +1280,7 @@ static const struct of_device_id bcm2835_pinctrl_match[] = {
},
{}
};
MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
static int bcm2835_pinctrl_probe(struct platform_device *pdev)
{

9
drivers/pinctrl/cirrus/pinctrl-madera-core.c
View File

@ -1063,12 +1063,9 @@ static int madera_pin_probe(struct platform_device *pdev)
if (pdata->gpio_configs) {
ret = pinctrl_register_mappings(pdata->gpio_configs,
pdata->n_gpio_configs);
if (ret) {
dev_err(priv->dev,
"Failed to register pdata mappings (%d)\n",
ret);
return ret;
}
if (ret)
return dev_err_probe(priv->dev, ret,
"Failed to register pdata mappings\n");
}
ret = pinctrl_enable(priv->pctl);

2
drivers/pinctrl/core.c
View File

@ -1971,7 +1971,7 @@ static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev)
static void pinctrl_init_debugfs(void)
{
debugfs_root = debugfs_create_dir("pinctrl", NULL);
if (IS_ERR(debugfs_root) || !debugfs_root) {
if (IS_ERR(debugfs_root)) {
pr_warn("failed to create debugfs directory\n");
debugfs_root = NULL;
return;

2
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
View File

@ -130,7 +130,7 @@ static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG, input_val);
}
configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);
configs = kmemdup_array(cfg, ncfg, sizeof(unsigned long), GFP_KERNEL);
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_id);

7
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -804,14 +804,14 @@ int imx_pinctrl_probe(struct platform_device *pdev,
}
EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
static int imx_pinctrl_suspend(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
return pinctrl_force_sleep(ipctl->pctl);
}
static int __maybe_unused imx_pinctrl_resume(struct device *dev)
static int imx_pinctrl_resume(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
@ -819,8 +819,7 @@ static int __maybe_unused imx_pinctrl_resume(struct device *dev)
}
const struct dev_pm_ops imx_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
imx_pinctrl_resume)
LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, imx_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);

2
drivers/pinctrl/freescale/pinctrl-imx8mq.c
View File

@ -341,7 +341,7 @@ static struct platform_driver imx8mq_pinctrl_driver = {
.driver = {
.name = "imx8mq-pinctrl",
.of_match_table = imx8mq_pinctrl_of_match,
.pm = &imx_pinctrl_pm_ops,
.pm = pm_sleep_ptr(&imx_pinctrl_pm_ops),
.suppress_bind_attrs = true,
},
.probe = imx8mq_pinctrl_probe,

7
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -560,9 +560,10 @@ static DEFINE_RAW_SPINLOCK(byt_lock);
static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
int reg)
{
struct intel_community *comm = intel_get_community(vg, offset);
const struct intel_community *comm;
u32 reg_offset;
comm = intel_get_community(vg, offset);
if (!comm)
return NULL;
@ -1541,10 +1542,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
}
ret = devm_gpiochip_add_data(vg->dev, gc, vg);
if (ret) {
if (ret)
dev_err(vg->dev, "failed adding byt-gpio chip\n");
return ret;
}
return ret;
}

326
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -70,6 +70,12 @@
#define PADCFG0_PMODE_SHIFT 10
#define PADCFG0_PMODE_MASK GENMASK(13, 10)
#define PADCFG0_PMODE_GPIO 0
#define PADCFG0_GPIODIS_SHIFT 8
#define PADCFG0_GPIODIS_MASK GENMASK(9, 8)
#define PADCFG0_GPIODIS_NONE 0
#define PADCFG0_GPIODIS_OUTPUT 1
#define PADCFG0_GPIODIS_INPUT 2
#define PADCFG0_GPIODIS_FULL 3
#define PADCFG0_GPIORXDIS BIT(9)
#define PADCFG0_GPIOTXDIS BIT(8)
#define PADCFG0_GPIORXSTATE BIT(1)
@ -108,13 +114,30 @@ struct intel_community_context {
#define pin_to_padno(c, p) ((p) - (c)->pin_base)
#define padgroup_offset(g, p) ((p) - (g)->base)
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin)
{
struct intel_community *community;
int i;
#define for_each_intel_pin_community(pctrl, community) \
for (unsigned int __ci = 0; \
__ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \
__ci++) \
for (i = 0; i < pctrl->ncommunities; i++) {
community = &pctrl->communities[i];
#define for_each_intel_community_pad_group(community, grp) \
for (unsigned int __gi = 0; \
__gi < community->ngpps && (grp = &community->gpps[__gi]); \
__gi++) \
#define for_each_intel_pad_group(pctrl, community, grp) \
for_each_intel_pin_community(pctrl, community) \
for_each_intel_community_pad_group(community, grp)
#define for_each_intel_gpio_group(pctrl, community, grp) \
for_each_intel_pad_group(pctrl, community, grp) \
if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
unsigned int pin)
{
const struct intel_community *community;
for_each_intel_pin_community(pctrl, community) {
if (pin >= community->pin_base &&
pin < community->pin_base + community->npins)
return community;
@ -129,11 +152,9 @@ static const struct intel_padgroup *
intel_community_get_padgroup(const struct intel_community *community,
unsigned int pin)
{
int i;
for (i = 0; i < community->ngpps; i++) {
const struct intel_padgroup *padgrp = &community->gpps[i];
const struct intel_padgroup *padgrp;
for_each_intel_community_pad_group(community, padgrp) {
if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
return padgrp;
}
@ -161,7 +182,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
return community->pad_regs + reg + padno * nregs * 4;
}
static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin)
{
const struct intel_community *community;
const struct intel_padgroup *padgrp;
@ -186,7 +207,7 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pi
return !(readl(padown) & PADOWN_MASK(gpp_offset));
}
static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin)
{
const struct intel_community *community;
const struct intel_padgroup *padgrp;
@ -212,7 +233,6 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
/**
* enum - Locking variants of the pad configuration
*
* @PAD_UNLOCKED: pad is fully controlled by the configuration registers
* @PAD_LOCKED: pad configuration registers, except TX state, are locked
* @PAD_LOCKED_TX: pad configuration TX state is locked
@ -229,9 +249,9 @@ enum {
PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
};
static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin)
{
struct intel_community *community;
const struct intel_community *community;
const struct intel_padgroup *padgrp;
unsigned int offset, gpp_offset;
u32 value;
@ -267,19 +287,19 @@ static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
return ret;
}
static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin)
{
return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
}
static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin)
{
return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
}
int intel_get_groups_count(struct pinctrl_dev *pctldev)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->ngroups;
}
@ -287,7 +307,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL);
const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].grp.name;
}
@ -296,7 +316,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL);
int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
const unsigned int **pins, unsigned int *npins)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].grp.pins;
*npins = pctrl->soc->groups[group].grp.npins;
@ -364,7 +384,7 @@ static const struct pinctrl_ops intel_pinctrl_ops = {
int intel_get_functions_count(struct pinctrl_dev *pctldev)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->nfunctions;
}
@ -372,7 +392,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL);
const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->functions[function].func.name;
}
@ -381,7 +401,7 @@ EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL);
int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
const char * const **groups, unsigned int * const ngroups)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->soc->functions[function].func.groups;
*ngroups = pctrl->soc->functions[function].func.ngroups;
@ -429,19 +449,49 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
return 0;
}
static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
{
u32 value;
/**
* enum - Possible pad physical connections
* @PAD_CONNECT_NONE: pad is fully disconnected
* @PAD_CONNECT_INPUT: pad is in input only mode
* @PAD_CONNECT_OUTPUT: pad is in output only mode
* @PAD_CONNECT_FULL: pad is fully connected
*/
enum {
PAD_CONNECT_NONE = 0,
PAD_CONNECT_INPUT = 1,
PAD_CONNECT_OUTPUT = 2,
PAD_CONNECT_FULL = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT,
};
value = readl(padcfg0);
if (input) {
static int __intel_gpio_get_direction(u32 value)
{
switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) {
case PADCFG0_GPIODIS_FULL:
return PAD_CONNECT_NONE;
case PADCFG0_GPIODIS_OUTPUT:
return PAD_CONNECT_INPUT;
case PADCFG0_GPIODIS_INPUT:
return PAD_CONNECT_OUTPUT;
case PADCFG0_GPIODIS_NONE:
return PAD_CONNECT_FULL;
default:
return -ENOTSUPP;
};
}
static u32 __intel_gpio_set_direction(u32 value, bool input, bool output)
{
if (input)
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
} else {
value &= ~PADCFG0_GPIOTXDIS;
else
value |= PADCFG0_GPIORXDIS;
}
writel(value, padcfg0);
if (output)
value &= ~PADCFG0_GPIOTXDIS;
else
value |= PADCFG0_GPIOTXDIS;
return value;
}
static int __intel_gpio_get_gpio_mode(u32 value)
@ -465,8 +515,7 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
value |= PADCFG0_PMODE_GPIO;
/* Disable TX buffer and enable RX (this will be input) */
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
value = __intel_gpio_set_direction(value, true, false);
/* Disable SCI/SMI/NMI generation */
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
@ -512,12 +561,18 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
void __iomem *padcfg0;
u32 value;
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
guard(raw_spinlock_irqsave)(&pctrl->lock);
__intel_gpio_set_direction(padcfg0, input);
value = readl(padcfg0);
if (input)
value = __intel_gpio_set_direction(value, true, false);
else
value = __intel_gpio_set_direction(value, false, true);
writel(value, padcfg0);
return 0;
}
@ -612,6 +667,23 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
return 0;
}
static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 *arg)
{
void __iomem *padcfg0;
u32 value;
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
value = readl(padcfg0);
if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE)
return -EINVAL;
return 0;
}
static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 *arg)
{
@ -655,6 +727,12 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
return ret;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
ret = intel_config_get_high_impedance(pctrl, pin, param, &arg);
if (ret)
return ret;
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
ret = intel_config_get_debounce(pctrl, pin, param, &arg);
if (ret)
@ -753,11 +831,34 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
return 0;
}
static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin)
{
void __iomem *padcfg0;
u32 value;
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
guard(raw_spinlock_irqsave)(&pctrl->lock);
value = readl(padcfg0);
value = __intel_gpio_set_direction(value, false, false);
writel(value, padcfg0);
}
static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
unsigned int pin, unsigned int debounce)
{
void __iomem *padcfg0, *padcfg2;
u32 value0, value2;
unsigned long v;
if (debounce) {
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
if (v < 3 || v > 15)
return -EINVAL;
} else {
v = 0;
}
padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
if (!padcfg2)
@ -770,21 +871,15 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
value0 = readl(padcfg0);
value2 = readl(padcfg2);
/* Disable glitch filter and debouncer */
value0 &= ~PADCFG0_PREGFRXSEL;
value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
if (debounce) {
unsigned long v;
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
if (v < 3 || v > 15)
return -EINVAL;
value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT);
if (v) {
/* Enable glitch filter and debouncer */
value0 |= PADCFG0_PREGFRXSEL;
value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
value2 |= PADCFG2_DEBEN;
} else {
/* Disable glitch filter and debouncer */
value0 &= ~PADCFG0_PREGFRXSEL;
value2 &= ~PADCFG2_DEBEN;
}
writel(value0, padcfg0);
@ -812,6 +907,10 @@ static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
return ret;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
intel_gpio_set_high_impedance(pctrl, pin);
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
ret = intel_config_set_debounce(pctrl, pin,
pinconf_to_config_argument(configs[i]));
@ -854,34 +953,21 @@ static const struct pinctrl_desc intel_pinctrl_desc = {
* Return: a pin number and pointers to the community and pad group, which
* the pin belongs to, or negative error code if translation can't be done.
*/
static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset,
const struct intel_community **community,
const struct intel_padgroup **padgrp)
{
int i;
const struct intel_community *comm;
const struct intel_padgroup *grp;
for (i = 0; i < pctrl->ncommunities; i++) {
const struct intel_community *comm = &pctrl->communities[i];
int j;
for_each_intel_gpio_group(pctrl, comm, grp) {
if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) {
if (community)
*community = comm;
if (padgrp)
*padgrp = grp;
for (j = 0; j < comm->ngpps; j++) {
const struct intel_padgroup *pgrp = &comm->gpps[j];
if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
continue;
if (offset >= pgrp->gpio_base &&
offset < pgrp->gpio_base + pgrp->size) {
int pin;
pin = pgrp->base + offset - pgrp->gpio_base;
if (community)
*community = comm;
if (padgrp)
*padgrp = pgrp;
return pin;
}
return grp->base + offset - grp->gpio_base;
}
}
@ -897,7 +983,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
*
* Return: a GPIO offset, or negative error code if translation can't be done.
*/
static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin)
{
const struct intel_community *community;
const struct intel_padgroup *padgrp;
@ -929,7 +1015,7 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
return -EINVAL;
padcfg0 = readl(reg);
if (!(padcfg0 & PADCFG0_GPIOTXDIS))
if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
return !!(padcfg0 & PADCFG0_GPIORXSTATE);
@ -982,10 +1068,10 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
if (padcfg0 & PADCFG0_PMODE_MASK)
return -EINVAL;
if (padcfg0 & PADCFG0_GPIOTXDIS)
return GPIO_LINE_DIRECTION_IN;
if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
@ -1171,15 +1257,16 @@ static const struct irq_chip intel_gpio_irq_chip = {
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
const struct intel_community *community)
static irqreturn_t intel_gpio_irq(int irq, void *data)
{
struct gpio_chip *gc = &pctrl->chip;
unsigned int gpp;
const struct intel_community *community;
const struct intel_padgroup *padgrp;
struct intel_pinctrl *pctrl = data;
int ret = 0;
for (gpp = 0; gpp < community->ngpps; gpp++) {
const struct intel_padgroup *padgrp = &community->gpps[gpp];
/* Need to check all communities for pending interrupts */
for_each_intel_pad_group(pctrl, community, padgrp) {
struct gpio_chip *gc = &pctrl->chip;
unsigned long pending, enabled;
unsigned int gpp, gpp_offset;
void __iomem *reg, *is;
@ -1203,36 +1290,17 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
ret += pending ? 1 : 0;
}
return ret;
}
static irqreturn_t intel_gpio_irq(int irq, void *data)
{
const struct intel_community *community;
struct intel_pinctrl *pctrl = data;
unsigned int i;
int ret = 0;
/* Need to check all communities for pending interrupts */
for (i = 0; i < pctrl->ncommunities; i++) {
community = &pctrl->communities[i];
ret += intel_gpio_community_irq_handler(pctrl, community);
}
return IRQ_RETVAL(ret);
}
static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
{
int i;
const struct intel_community *community;
for (i = 0; i < pctrl->ncommunities; i++) {
const struct intel_community *community;
for_each_intel_pin_community(pctrl, community) {
void __iomem *reg, *is;
unsigned int gpp;
community = &pctrl->communities[i];
for (gpp = 0; gpp < community->ngpps; gpp++) {
reg = community->regs + community->ie_offset + gpp * 4;
is = community->regs + community->is_offset + gpp * 4;
@ -1257,36 +1325,17 @@ static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
return 0;
}
static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
const struct intel_community *community)
{
int ret = 0, i;
for (i = 0; i < community->ngpps; i++) {
const struct intel_padgroup *gpp = &community->gpps[i];
if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
continue;
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
gpp->gpio_base, gpp->base,
gpp->size);
if (ret)
return ret;
}
return ret;
}
static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int ret, i;
const struct intel_community *community;
const struct intel_padgroup *grp;
int ret;
for (i = 0; i < pctrl->ncommunities; i++) {
struct intel_community *community = &pctrl->communities[i];
ret = intel_gpio_add_community_ranges(pctrl, community);
for_each_intel_gpio_group(pctrl, community, grp) {
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
grp->gpio_base, grp->base,
grp->size);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
return ret;
@ -1299,20 +1348,12 @@ static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
{
const struct intel_community *community;
const struct intel_padgroup *grp;
unsigned int ngpio = 0;
int i, j;
for (i = 0; i < pctrl->ncommunities; i++) {
community = &pctrl->communities[i];
for (j = 0; j < community->ngpps; j++) {
const struct intel_padgroup *gpp = &community->gpps[j];
if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
continue;
if (gpp->gpio_base + gpp->size > ngpio)
ngpio = gpp->gpio_base + gpp->size;
}
for_each_intel_gpio_group(pctrl, community, grp) {
if (grp->gpio_base + grp->size > ngpio)
ngpio = grp->gpio_base + grp->size;
}
return ngpio;
@ -1682,7 +1723,8 @@ EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
static bool __intel_gpio_is_direct_irq(u32 value)
{
return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
return (value & PADCFG0_GPIROUTIOXAPIC) &&
(__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) &&
(__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
}

3
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -264,7 +264,8 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
extern const struct dev_pm_ops intel_pinctrl_pm_ops;
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin);
const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
unsigned int pin);
int intel_get_groups_count(struct pinctrl_dev *pctldev);
const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);

2
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -211,7 +211,7 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
int reg)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
struct intel_community *comm;
const struct intel_community *comm;
int reg_offset;
comm = intel_get_community(lg, offset);

7
drivers/pinctrl/mediatek/pinctrl-paris.c
View File

@ -1044,11 +1044,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev)
hw->nbase = hw->soc->nbase_names;
if (of_find_property(hw->dev->of_node,
"mediatek,rsel-resistance-in-si-unit", NULL))
hw->rsel_si_unit = true;
else
hw->rsel_si_unit = false;
hw->rsel_si_unit = of_property_read_bool(hw->dev->of_node,
"mediatek,rsel-resistance-in-si-unit");
spin_lock_init(&hw->lock);

12
drivers/pinctrl/meson/pinctrl-amlogic-c3.c
View File

@ -375,7 +375,7 @@ static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_3 };
static const unsigned int gen_clk_a4_pins[] = { GPIOA_4 };
static const unsigned int clk12_24_a_pins[] = { GPIOA_5 };
static struct meson_pmx_group c3_periphs_groups[] = {
static const struct meson_pmx_group c3_periphs_groups[] = {
GPIO_GROUP(GPIOE_0),
GPIO_GROUP(GPIOE_1),
GPIO_GROUP(GPIOE_2),
@ -987,7 +987,7 @@ static const char * const lcd_groups[] = {
"lcd_clk_a", "lcd_clk_x", "lcd_hs", "lcd_vs",
};
static struct meson_pmx_func c3_periphs_functions[] = {
static const struct meson_pmx_func c3_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(uart_a),
FUNCTION(uart_b),
@ -1036,7 +1036,7 @@ static struct meson_pmx_func c3_periphs_functions[] = {
FUNCTION(lcd),
};
static struct meson_bank c3_periphs_banks[] = {
static const struct meson_bank c3_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("X", GPIOX_0, GPIOX_13, 40, 53,
0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
@ -1054,7 +1054,7 @@ static struct meson_bank c3_periphs_banks[] = {
0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0),
};
static struct meson_pmx_bank c3_periphs_pmx_banks[] = {
static const struct meson_pmx_bank c3_periphs_pmx_banks[] = {
/* name first last reg offset */
BANK_PMX("B", GPIOB_0, GPIOB_14, 0x00, 0),
BANK_PMX("X", GPIOX_0, GPIOX_13, 0x03, 0),
@ -1065,12 +1065,12 @@ static struct meson_pmx_bank c3_periphs_pmx_banks[] = {
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x02, 0),
};
static struct meson_axg_pmx_data c3_periphs_pmx_banks_data = {
static const struct meson_axg_pmx_data c3_periphs_pmx_banks_data = {
.pmx_banks = c3_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(c3_periphs_pmx_banks),
};
static struct meson_pinctrl_data c3_periphs_pinctrl_data = {
static const struct meson_pinctrl_data c3_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = c3_periphs_pins,
.groups = c3_periphs_groups,

12
drivers/pinctrl/meson/pinctrl-amlogic-t7.c
View File

@ -535,7 +535,7 @@ static const unsigned int i2c0_sck_h_pins[] = { GPIOH_7 };
/* Bank H func3 */
static const unsigned int pcieck_reqn_h_pins[] = { GPIOH_2 };
static struct meson_pmx_group t7_periphs_groups[] = {
static const struct meson_pmx_group t7_periphs_groups[] = {
GPIO_GROUP(GPIOB_0),
GPIO_GROUP(GPIOB_1),
GPIO_GROUP(GPIOB_2),
@ -1443,7 +1443,7 @@ static const char * const mic_mute_groups[] = {
"mic_mute_key", "mic_mute_led",
};
static struct meson_pmx_func t7_periphs_functions[] = {
static const struct meson_pmx_func t7_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
@ -1524,7 +1524,7 @@ static struct meson_pmx_func t7_periphs_functions[] = {
FUNCTION(mic_mute),
};
static struct meson_bank t7_periphs_banks[] = {
static const struct meson_bank t7_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("D", GPIOD_0, GPIOD_12, 57, 69,
0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
@ -1552,7 +1552,7 @@ static struct meson_bank t7_periphs_banks[] = {
0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
};
static struct meson_pmx_bank t7_periphs_pmx_banks[] = {
static const struct meson_pmx_bank t7_periphs_pmx_banks[] = {
/* name first last reg offset */
BANK_PMX("D", GPIOD_0, GPIOD_12, 0x0a, 0),
BANK_PMX("E", GPIOE_0, GPIOE_6, 0x0c, 0),
@ -1568,12 +1568,12 @@ static struct meson_pmx_bank t7_periphs_pmx_banks[] = {
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x09, 0),
};
static struct meson_axg_pmx_data t7_periphs_pmx_banks_data = {
static const struct meson_axg_pmx_data t7_periphs_pmx_banks_data = {
.pmx_banks = t7_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(t7_periphs_pmx_banks),
};
static struct meson_pinctrl_data t7_periphs_pinctrl_data = {
static const struct meson_pinctrl_data t7_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = t7_periphs_pins,
.groups = t7_periphs_groups,

12
drivers/pinctrl/meson/pinctrl-meson-a1.c
View File

@ -339,7 +339,7 @@ static const unsigned int tst_out11_pins[] = { GPIOA_11 };
static const unsigned int mute_key_pins[] = { GPIOA_4 };
static const unsigned int mute_en_pins[] = { GPIOA_5 };
static struct meson_pmx_group meson_a1_periphs_groups[] = {
static const struct meson_pmx_group meson_a1_periphs_groups[] = {
GPIO_GROUP(GPIOP_0),
GPIO_GROUP(GPIOP_1),
GPIO_GROUP(GPIOP_2),
@ -832,7 +832,7 @@ static const char * const mute_groups[] = {
"mute_key", "mute_en",
};
static struct meson_pmx_func meson_a1_periphs_functions[] = {
static const struct meson_pmx_func meson_a1_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(psram),
FUNCTION(pwm_a),
@ -875,7 +875,7 @@ static struct meson_pmx_func meson_a1_periphs_functions[] = {
FUNCTION(mute),
};
static struct meson_bank meson_a1_periphs_banks[] = {
static const struct meson_bank meson_a1_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds*/
BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0,
0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0),
@ -889,7 +889,7 @@ static struct meson_bank meson_a1_periphs_banks[] = {
0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0),
};
static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
static const struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
/* name first lask reg offset */
BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
@ -898,12 +898,12 @@ static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
};
static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
static const struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
.pmx_banks = meson_a1_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
};
static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
static const struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_a1_periphs_pins,
.groups = meson_a1_periphs_groups,

12
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
View File

@ -27,10 +27,10 @@
static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
unsigned int pin,
struct meson_pmx_bank **bank)
const struct meson_pmx_bank **bank)
{
int i;
struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
const struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
for (i = 0; i < pmx->num_pmx_banks; i++)
if (pin >= pmx->pmx_banks[i].first &&
@ -42,7 +42,7 @@ static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
return -EINVAL;
}
static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
static int meson_pmx_calc_reg_and_offset(const struct meson_pmx_bank *bank,
unsigned int pin, unsigned int *reg,
unsigned int *offset)
{
@ -59,10 +59,10 @@ static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
static int meson_axg_pmx_update_function(struct meson_pinctrl *pc,
unsigned int pin, unsigned int func)
{
const struct meson_pmx_bank *bank;
int ret;
int reg;
int offset;
struct meson_pmx_bank *bank;
ret = meson_axg_pmx_get_bank(pc, pin, &bank);
if (ret)
@ -82,8 +82,8 @@ static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev,
int i;
int ret;
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_func *func = &pc->data->funcs[func_num];
struct meson_pmx_group *group = &pc->data->groups[group_num];
const struct meson_pmx_func *func = &pc->data->funcs[func_num];
const struct meson_pmx_group *group = &pc->data->groups[group_num];
struct meson_pmx_axg_data *pmx_data =
(struct meson_pmx_axg_data *)group->data;

2
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
View File

@ -17,7 +17,7 @@ struct meson_pmx_bank {
};
struct meson_axg_pmx_data {
struct meson_pmx_bank *pmx_banks;
const struct meson_pmx_bank *pmx_banks;
unsigned int num_pmx_banks;
};

24
drivers/pinctrl/meson/pinctrl-meson-axg.c
View File

@ -352,7 +352,7 @@ static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
static struct meson_pmx_group meson_axg_periphs_groups[] = {
static const struct meson_pmx_group meson_axg_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
@ -675,7 +675,7 @@ static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
/* gen_clk */
static const unsigned int gen_clk_ee_pins[] = {GPIOAO_13};
static struct meson_pmx_group meson_axg_aobus_groups[] = {
static const struct meson_pmx_group meson_axg_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
@ -955,7 +955,7 @@ static const char * const gen_clk_ee_groups[] = {
"gen_clk_ee",
};
static struct meson_pmx_func meson_axg_periphs_functions[] = {
static const struct meson_pmx_func meson_axg_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
@ -987,7 +987,7 @@ static struct meson_pmx_func meson_axg_periphs_functions[] = {
FUNCTION(tdmc),
};
static struct meson_pmx_func meson_axg_aobus_functions[] = {
static const struct meson_pmx_func meson_axg_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao_a),
FUNCTION(uart_ao_b),
@ -1003,7 +1003,7 @@ static struct meson_pmx_func meson_axg_aobus_functions[] = {
FUNCTION(gen_clk_ee),
};
static struct meson_bank meson_axg_periphs_banks[] = {
static const struct meson_bank meson_axg_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("Z", GPIOZ_0, GPIOZ_10, 14, 24, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
BANK("BOOT", BOOT_0, BOOT_14, 25, 39, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
@ -1012,12 +1012,12 @@ static struct meson_bank meson_axg_periphs_banks[] = {
BANK("Y", GPIOY_0, GPIOY_15, 84, 99, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
};
static struct meson_bank meson_axg_aobus_banks[] = {
static const struct meson_bank meson_axg_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
static const struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
/* name first lask reg offset */
BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
@ -1026,21 +1026,21 @@ static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
};
static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
static const struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
.pmx_banks = meson_axg_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
};
static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
static const struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
};
static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
static const struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
.pmx_banks = meson_axg_aobus_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
};
static struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
static const struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_axg_periphs_pins,
.groups = meson_axg_periphs_groups,
@ -1054,7 +1054,7 @@ static struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.pmx_data = &meson_axg_periphs_pmx_banks_data,
};
static struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
static const struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_axg_aobus_pins,
.groups = meson_axg_aobus_groups,

24
drivers/pinctrl/meson/pinctrl-meson-g12a.c
View File

@ -436,7 +436,7 @@ static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 };
static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 };
static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 };
static struct meson_pmx_group meson_g12a_periphs_groups[] = {
static const struct meson_pmx_group meson_g12a_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
@ -860,7 +860,7 @@ static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 };
/* mclk0_ao */
static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 };
static struct meson_pmx_group meson_g12a_aobus_groups[] = {
static const struct meson_pmx_group meson_g12a_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
@ -1253,7 +1253,7 @@ static const char * const mclk0_ao_groups[] = {
"mclk0_ao",
};
static struct meson_pmx_func meson_g12a_periphs_functions[] = {
static const struct meson_pmx_func meson_g12a_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
@ -1295,7 +1295,7 @@ static struct meson_pmx_func meson_g12a_periphs_functions[] = {
FUNCTION(tdm_c),
};
static struct meson_pmx_func meson_g12a_aobus_functions[] = {
static const struct meson_pmx_func meson_g12a_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao_a),
FUNCTION(uart_ao_b),
@ -1317,7 +1317,7 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = {
FUNCTION(mclk0_ao),
};
static struct meson_bank meson_g12a_periphs_banks[] = {
static const struct meson_bank meson_g12a_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15,
4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0),
@ -1333,7 +1333,7 @@ static struct meson_bank meson_g12a_periphs_banks[] = {
2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0),
};
static struct meson_bank meson_g12a_aobus_banks[] = {
static const struct meson_bank meson_g12a_aobus_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11,
3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0),
@ -1342,7 +1342,7 @@ static struct meson_bank meson_g12a_aobus_banks[] = {
3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0),
};
static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
static const struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
/* name first last reg offset */
BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0),
BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0),
@ -1352,17 +1352,17 @@ static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
};
static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = {
static const struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = {
.pmx_banks = meson_g12a_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks),
};
static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = {
static const struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = {
BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0),
BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16),
};
static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = {
static const struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = {
.pmx_banks = meson_g12a_aobus_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks),
};
@ -1375,7 +1375,7 @@ static int meson_g12a_aobus_parse_dt_extra(struct meson_pinctrl *pc)
return 0;
}
static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
static const struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_g12a_periphs_pins,
.groups = meson_g12a_periphs_groups,
@ -1389,7 +1389,7 @@ static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
.pmx_data = &meson_g12a_periphs_pmx_banks_data,
};
static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = {
static const struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_g12a_aobus_pins,
.groups = meson_g12a_aobus_groups,

16
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
View File

@ -307,7 +307,7 @@ static const unsigned int spdif_out_ao_13_pins[] = { GPIOAO_13 };
static const unsigned int ao_cec_pins[] = { GPIOAO_12 };
static const unsigned int ee_cec_pins[] = { GPIOAO_12 };
static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
static const struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
@ -541,7 +541,7 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GROUP(sdcard_clk, 2, 11),
};
static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
static const struct meson_pmx_group meson_gxbb_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
@ -798,7 +798,7 @@ static const char * const cec_ao_groups[] = {
"ao_cec", "ee_cec",
};
static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
static const struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
@ -829,7 +829,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(tsin_b),
};
static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
static const struct meson_pmx_func meson_gxbb_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
@ -845,7 +845,7 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
FUNCTION(cec_ao),
};
static struct meson_bank meson_gxbb_periphs_banks[] = {
static const struct meson_bank meson_gxbb_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
@ -857,12 +857,12 @@ static struct meson_bank meson_gxbb_periphs_banks[] = {
BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
};
static struct meson_bank meson_gxbb_aobus_banks[] = {
static const struct meson_bank meson_gxbb_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
static const struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_gxbb_periphs_pins,
.groups = meson_gxbb_periphs_groups,
@ -875,7 +875,7 @@ static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
static const struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_gxbb_aobus_pins,
.groups = meson_gxbb_aobus_groups,

16
drivers/pinctrl/meson/pinctrl-meson-gxl.c
View File

@ -301,7 +301,7 @@ static const unsigned int spdif_out_ao_9_pins[] = { GPIOAO_9 };
static const unsigned int ao_cec_pins[] = { GPIOAO_8 };
static const unsigned int ee_cec_pins[] = { GPIOAO_8 };
static struct meson_pmx_group meson_gxl_periphs_groups[] = {
static const struct meson_pmx_group meson_gxl_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
@ -527,7 +527,7 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(pwm_f_clk, 8, 30),
};
static struct meson_pmx_group meson_gxl_aobus_groups[] = {
static const struct meson_pmx_group meson_gxl_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
@ -763,7 +763,7 @@ static const char * const cec_ao_groups[] = {
"ao_cec", "ee_cec",
};
static struct meson_pmx_func meson_gxl_periphs_functions[] = {
static const struct meson_pmx_func meson_gxl_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
@ -793,7 +793,7 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = {
FUNCTION(tsin_b),
};
static struct meson_pmx_func meson_gxl_aobus_functions[] = {
static const struct meson_pmx_func meson_gxl_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
@ -807,7 +807,7 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = {
FUNCTION(cec_ao),
};
static struct meson_bank meson_gxl_periphs_banks[] = {
static const struct meson_bank meson_gxl_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_18, 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
BANK("DV", GPIODV_0, GPIODV_29, 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
@ -818,12 +818,12 @@ static struct meson_bank meson_gxl_periphs_banks[] = {
BANK("CLK", GPIOCLK_0, GPIOCLK_1, 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
};
static struct meson_bank meson_gxl_aobus_banks[] = {
static const struct meson_bank meson_gxl_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_9, 0, 9, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
static const struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_gxl_periphs_pins,
.groups = meson_gxl_periphs_groups,
@ -836,7 +836,7 @@ static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
static const struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_gxl_aobus_pins,
.groups = meson_gxl_aobus_groups,

12
drivers/pinctrl/meson/pinctrl-meson-s4.c
View File

@ -411,7 +411,7 @@ static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 };
static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 };
static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 };
static struct meson_pmx_group meson_s4_periphs_groups[] = {
static const struct meson_pmx_group meson_s4_periphs_groups[] = {
GPIO_GROUP(GPIOE_0),
GPIO_GROUP(GPIOE_1),
@ -1100,7 +1100,7 @@ static const char * const s2_demod_groups[] = {
"s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0",
};
static struct meson_pmx_func meson_s4_periphs_functions[] = {
static const struct meson_pmx_func meson_s4_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(i2c0),
FUNCTION(i2c1),
@ -1160,7 +1160,7 @@ static struct meson_pmx_func meson_s4_periphs_functions[] = {
FUNCTION(s2_demod),
};
static struct meson_bank meson_s4_periphs_banks[] = {
static const struct meson_bank meson_s4_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13,
0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
@ -1180,7 +1180,7 @@ static struct meson_bank meson_s4_periphs_banks[] = {
0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
};
static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
static const struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
/*name first lask reg offset*/
BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0),
BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
@ -1192,12 +1192,12 @@ static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0)
};
static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
static const struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
.pmx_banks = meson_s4_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks),
};
static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
static const struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_s4_periphs_pins,
.groups = meson_s4_periphs_groups,

25
drivers/pinctrl/meson/pinctrl-meson.c
View File

@ -70,7 +70,7 @@ static const unsigned int meson_bit_strides[] = {
* Return: 0 on success, a negative value on error
*/
static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
struct meson_bank **bank)
const struct meson_bank **bank)
{
int i;
@ -94,11 +94,12 @@ static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
* @reg: the computed register offset
* @bit: the computed bit
*/
static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
static void meson_calc_reg_and_bit(const struct meson_bank *bank,
unsigned int pin,
enum meson_reg_type reg_type,
unsigned int *reg, unsigned int *bit)
{
struct meson_reg_desc *desc = &bank->regs[reg_type];
const struct meson_reg_desc *desc = &bank->regs[reg_type];
*bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
*reg = (desc->reg + (*bit / 32)) * 4;
@ -181,7 +182,7 @@ static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
unsigned int reg_type,
bool arg)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit;
int ret;
@ -198,7 +199,7 @@ static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
unsigned int pin,
unsigned int reg_type)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit, val;
int ret;
@ -261,7 +262,7 @@ static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
unsigned int pin)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit = 0;
int ret;
@ -280,7 +281,7 @@ static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
bool pull_up)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit, val = 0;
int ret;
@ -308,7 +309,7 @@ static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
unsigned int pin,
u16 drive_strength_ua)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit, ds_val;
int ret;
@ -399,7 +400,7 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit, val;
int ret, conf;
@ -435,7 +436,7 @@ static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
unsigned int pin,
u16 *drive_strength_ua)
{
struct meson_bank *bank;
const struct meson_bank *bank;
unsigned int reg, bit;
unsigned int val;
int ret;
@ -528,7 +529,7 @@ static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
unsigned long *configs, unsigned num_configs)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_group *group = &pc->data->groups[num_group];
const struct meson_pmx_group *group = &pc->data->groups[num_group];
int i;
dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
@ -587,8 +588,8 @@ static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
struct meson_pinctrl *pc = gpiochip_get_data(chip);
const struct meson_bank *bank;
unsigned int reg, bit, val;
struct meson_bank *bank;
int ret;
ret = meson_get_bank(pc, gpio, &bank);

8
drivers/pinctrl/meson/pinctrl-meson.h
View File

@ -110,15 +110,15 @@ struct meson_bank {
struct meson_pinctrl_data {
const char *name;
const struct pinctrl_pin_desc *pins;
struct meson_pmx_group *groups;
struct meson_pmx_func *funcs;
const struct meson_pmx_group *groups;
const struct meson_pmx_func *funcs;
unsigned int num_pins;
unsigned int num_groups;
unsigned int num_funcs;
struct meson_bank *banks;
const struct meson_bank *banks;
unsigned int num_banks;
const struct pinmux_ops *pmx_ops;
void *pmx_data;
const void *pmx_data;
int (*parse_dt)(struct meson_pinctrl *pc);
};

6
drivers/pinctrl/meson/pinctrl-meson8-pmx.c
View File

@ -32,7 +32,7 @@
static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc,
unsigned int pin, int sel_group)
{
struct meson_pmx_group *group;
const struct meson_pmx_group *group;
struct meson8_pmx_data *pmx_data;
int i, j;
@ -57,8 +57,8 @@ static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
unsigned group_num)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_func *func = &pc->data->funcs[func_num];
struct meson_pmx_group *group = &pc->data->groups[group_num];
const struct meson_pmx_func *func = &pc->data->funcs[func_num];
const struct meson_pmx_group *group = &pc->data->groups[group_num];
struct meson8_pmx_data *pmx_data =
(struct meson8_pmx_data *)group->data;
int i, ret = 0;

16
drivers/pinctrl/meson/pinctrl-meson8.c
View File

@ -405,7 +405,7 @@ static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
static struct meson_pmx_group meson8_cbus_groups[] = {
static const struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
@ -745,7 +745,7 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
GROUP(sdxc_cmd_b, 2, 4),
};
static struct meson_pmx_group meson8_aobus_groups[] = {
static const struct meson_pmx_group meson8_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
@ -1015,7 +1015,7 @@ static const char * const hdmi_cec_ao_groups[] = {
"hdmi_cec_ao"
};
static struct meson_pmx_func meson8_cbus_functions[] = {
static const struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
@ -1051,7 +1051,7 @@ static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(spdif),
};
static struct meson_pmx_func meson8_aobus_functions[] = {
static const struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(remote),
@ -1063,7 +1063,7 @@ static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(hdmi_cec_ao),
};
static struct meson_bank meson8_cbus_banks[] = {
static const struct meson_bank meson8_cbus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
@ -1074,12 +1074,12 @@ static struct meson_bank meson8_cbus_banks[] = {
BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
};
static struct meson_bank meson8_aobus_banks[] = {
static const struct meson_bank meson8_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
static const struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
.name = "cbus-banks",
.pins = meson8_cbus_pins,
.groups = meson8_cbus_groups,
@ -1092,7 +1092,7 @@ static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
static const struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
.name = "ao-bank",
.pins = meson8_aobus_pins,
.groups = meson8_aobus_groups,

16
drivers/pinctrl/meson/pinctrl-meson8b.c
View File

@ -349,7 +349,7 @@ static const unsigned int eth_ref_clk_pins[] = { DIF_3_N };
static const unsigned int eth_mdc_pins[] = { DIF_4_P };
static const unsigned int eth_mdio_en_pins[] = { DIF_4_N };
static struct meson_pmx_group meson8b_cbus_groups[] = {
static const struct meson_pmx_group meson8b_cbus_groups[] = {
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
@ -603,7 +603,7 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {
GROUP(eth_rxd2, 7, 23),
};
static struct meson_pmx_group meson8b_aobus_groups[] = {
static const struct meson_pmx_group meson8b_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
@ -869,7 +869,7 @@ static const char * const tsin_b_groups[] = {
"tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
};
static struct meson_pmx_func meson8b_cbus_functions[] = {
static const struct meson_pmx_func meson8b_cbus_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
@ -903,7 +903,7 @@ static struct meson_pmx_func meson8b_cbus_functions[] = {
FUNCTION(clk_24m),
};
static struct meson_pmx_func meson8b_aobus_functions[] = {
static const struct meson_pmx_func meson8b_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
@ -917,7 +917,7 @@ static struct meson_pmx_func meson8b_aobus_functions[] = {
FUNCTION(hdmi_cec),
};
static struct meson_bank meson8b_cbus_banks[] = {
static const struct meson_bank meson8b_cbus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16),
@ -938,12 +938,12 @@ static struct meson_bank meson8b_cbus_banks[] = {
BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
};
static struct meson_bank meson8b_aobus_banks[] = {
static const struct meson_bank meson8b_aobus_banks[] = {
/* name first lastc irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
static const struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
.name = "cbus-banks",
.pins = meson8b_cbus_pins,
.groups = meson8b_cbus_groups,
@ -956,7 +956,7 @@ static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
static const struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson8b_aobus_pins,
.groups = meson8b_aobus_groups,

42
drivers/pinctrl/mvebu/pinctrl-dove.c
View File

@ -767,7 +767,7 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
struct resource fb_res;
struct mvebu_mpp_ctrl_data *mpp_data;
void __iomem *base;
int i;
int i, ret;
pdev->dev.platform_data = (void *)device_get_match_data(&pdev->dev);
@ -783,13 +783,17 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
clk_prepare_enable(clk);
base = devm_platform_get_and_ioremap_resource(pdev, 0, &mpp_res);
if (IS_ERR(base))
return PTR_ERR(base);
if (IS_ERR(base)) {
ret = PTR_ERR(base);
goto err_probe;
}
mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
sizeof(*mpp_data), GFP_KERNEL);
if (!mpp_data)
return -ENOMEM;
if (!mpp_data) {
ret = -ENOMEM;
goto err_probe;
}
dove_pinctrl_info.control_data = mpp_data;
for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
@ -808,8 +812,10 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
}
mpp4_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mpp4_base))
return PTR_ERR(mpp4_base);
if (IS_ERR(mpp4_base)) {
ret = PTR_ERR(mpp4_base);
goto err_probe;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
if (!res) {
@ -820,8 +826,10 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
}
pmu_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmu_base))
return PTR_ERR(pmu_base);
if (IS_ERR(pmu_base)) {
ret = PTR_ERR(pmu_base);
goto err_probe;
}
gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
if (IS_ERR(gconfmap)) {
@ -831,12 +839,17 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
adjust_resource(&fb_res,
(mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
if (IS_ERR(gc_base))
return PTR_ERR(gc_base);
if (IS_ERR(gc_base)) {
ret = PTR_ERR(gc_base);
goto err_probe;
}
gconfmap = devm_regmap_init_mmio(&pdev->dev,
gc_base, &gc_regmap_config);
if (IS_ERR(gconfmap))
return PTR_ERR(gconfmap);
if (IS_ERR(gconfmap)) {
ret = PTR_ERR(gconfmap);
goto err_probe;
}
}
/* Warn on any missing DT resource */
@ -844,6 +857,9 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
return mvebu_pinctrl_probe(pdev);
err_probe:
clk_disable_unprepare(clk);
return ret;
}
static struct platform_driver dove_pinctrl_driver = {

3
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -716,8 +716,7 @@ static int abx500_dt_add_map_configs(struct pinctrl_map **map,
if (*num_maps == *reserved_maps)
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs), GFP_KERNEL);
if (!dup_configs)
return -ENOMEM;

3
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -601,8 +601,7 @@ static int nmk_dt_add_map_configs(struct pinctrl_map **map,
if (*num_maps == *reserved_maps)
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs), GFP_KERNEL);
if (!dup_configs)
return -ENOMEM;

64
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
View File

@ -241,6 +241,7 @@ static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
break;
case IRQ_TYPE_EDGE_BOTH:
npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
break;
case IRQ_TYPE_LEVEL_LOW:
@ -315,8 +316,8 @@ static struct irq_chip npcmgpio_irqchip = {
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static const int gpi36_pins[] = { 58 };
static const int gpi35_pins[] = { 58 };
static const int gpi36_pins[] = { 36 };
static const int gpi35_pins[] = { 35 };
static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
static const int tp_uart_pins[] = { 50, 51 };
@ -437,7 +438,6 @@ static const int smb4_pins[] = { 28, 29 };
static const int smb4b_pins[] = { 18, 19 };
static const int smb4c_pins[] = { 20, 21 };
static const int smb4d_pins[] = { 22, 23 };
static const int smb4den_pins[] = { 17 };
static const int smb5_pins[] = { 26, 27 };
static const int smb5b_pins[] = { 13, 12 };
static const int smb5c_pins[] = { 15, 14 };
@ -515,7 +515,7 @@ static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
static const int rg2mdio_pins[] = { 216, 217 };
static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
213, 214, 215, 216, 217 };
213, 214, 215, 216, 217, 250 };
static const int iox1_pins[] = { 0, 1, 2, 3 };
static const int iox2_pins[] = { 4, 5, 6, 7 };
@ -570,7 +570,6 @@ static const int spi3cs3_pins[] = { 189 };
static const int ddc_pins[] = { 204, 205, 206, 207 };
static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
static const int lpcclk_pins[] = { 168 };
static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
static const int lkgpo0_pins[] = { 16 };
@ -699,7 +698,6 @@ struct npcm8xx_pingroup {
NPCM8XX_GRP(smb4b), \
NPCM8XX_GRP(smb4c), \
NPCM8XX_GRP(smb4d), \
NPCM8XX_GRP(smb4den), \
NPCM8XX_GRP(smb5), \
NPCM8XX_GRP(smb5b), \
NPCM8XX_GRP(smb5c), \
@ -808,7 +806,6 @@ struct npcm8xx_pingroup {
NPCM8XX_GRP(spi3cs3), \
NPCM8XX_GRP(spi0cs1), \
NPCM8XX_GRP(lpc), \
NPCM8XX_GRP(lpcclk), \
NPCM8XX_GRP(espi), \
NPCM8XX_GRP(lkgpo0), \
NPCM8XX_GRP(lkgpo1), \
@ -948,7 +945,6 @@ NPCM8XX_SFUNC(smb4);
NPCM8XX_SFUNC(smb4b);
NPCM8XX_SFUNC(smb4c);
NPCM8XX_SFUNC(smb4d);
NPCM8XX_SFUNC(smb4den);
NPCM8XX_SFUNC(smb5);
NPCM8XX_SFUNC(smb5b);
NPCM8XX_SFUNC(smb5c);
@ -1056,7 +1052,6 @@ NPCM8XX_SFUNC(spi3cs2);
NPCM8XX_SFUNC(spi3cs3);
NPCM8XX_SFUNC(spi0cs1);
NPCM8XX_SFUNC(lpc);
NPCM8XX_SFUNC(lpcclk);
NPCM8XX_SFUNC(espi);
NPCM8XX_SFUNC(lkgpo0);
NPCM8XX_SFUNC(lkgpo1);
@ -1172,7 +1167,6 @@ static struct npcm8xx_func npcm8xx_funcs[] = {
NPCM8XX_MKFUNC(smb4b),
NPCM8XX_MKFUNC(smb4c),
NPCM8XX_MKFUNC(smb4d),
NPCM8XX_MKFUNC(smb4den),
NPCM8XX_MKFUNC(smb5),
NPCM8XX_MKFUNC(smb5b),
NPCM8XX_MKFUNC(smb5c),
@ -1280,7 +1274,6 @@ static struct npcm8xx_func npcm8xx_funcs[] = {
NPCM8XX_MKFUNC(spi3cs3),
NPCM8XX_MKFUNC(spi0cs1),
NPCM8XX_MKFUNC(lpc),
NPCM8XX_MKFUNC(lpcclk),
NPCM8XX_MKFUNC(espi),
NPCM8XX_MKFUNC(lkgpo0),
NPCM8XX_MKFUNC(lkgpo1),
@ -1347,7 +1340,7 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2b, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, smb4den, I2CSEGSEL, 23, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
@ -1365,6 +1358,8 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(32, spi0cs1, MFSEL1, 3, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(35, gpi35, MFSEL5, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(36, gpi36, MFSEL5, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
@ -1438,10 +1433,10 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
@ -1490,13 +1485,13 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(161, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(162, serirq, MFSEL1, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM8XX_PINCFG(162, clkrun, MFSEL3, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(168, lpcclk, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(168, serirq, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(170, smi, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
@ -1515,22 +1510,22 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(184, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(185, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(186, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(188, gpio1889, MFSEL7, 25, spi3cs2, MFSEL4, 18, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(189, gpio1889, MFSEL7, 25, spi3cs3, MFSEL4, 19, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(190, nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */
NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */
NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, SLEW), /* XX */
NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, SLEW), /* XX */
NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */
NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */
@ -1553,10 +1548,10 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(226, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 12) | SLEW),
NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEWLPC), /* slewlpc ? */
NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), /* slewlpc ? */
NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
@ -1567,7 +1562,8 @@ static const struct npcm8xx_pincfg pincfg[] = {
NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM8XX_PINCFG(250, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
NPCM8XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
@ -1610,6 +1606,8 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = {
PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
PINCTRL_PIN(35, "MCBPCK/GPI35_AHB2PCI_DIS"),
PINCTRL_PIN(36, "SYSBPCK/GPI36"),
PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
@ -2044,7 +2042,7 @@ static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
const unsigned int *pin = &offset;
int mode = fn_gpio;
if (pin[0] >= 183 && pin[0] <= 189)
if ((pin[0] >= 183 && pin[0] <= 189) || pin[0] == 35 || pin[0] == 36)
mode = pincfg[pin[0]].fn0;
npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);

51
drivers/pinctrl/nxp/pinctrl-s32cc.c
View File

@ -2,7 +2,7 @@
/*
* Core driver for the S32 CC (Common Chassis) pin controller
*
* Copyright 2017-2022 NXP
* Copyright 2017-2022,2024 NXP
* Copyright (C) 2022 SUSE LLC
* Copyright 2015-2016 Freescale Semiconductor, Inc.
*/
@ -39,6 +39,11 @@
#define S32_MSCR_ODE BIT(20)
#define S32_MSCR_OBE BIT(21)
enum s32_write_type {
S32_PINCONF_UPDATE_ONLY,
S32_PINCONF_OVERWRITE,
};
static struct regmap_config s32_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@ -431,16 +436,15 @@ static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned int offset,
bool input)
{
unsigned int config;
/* Always enable IBE for GPIOs. This allows us to read the
* actual line value and compare it with the one set.
*/
unsigned int config = S32_MSCR_IBE;
unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE;
if (input) {
/* Disable output buffer and enable input buffer */
config = S32_MSCR_IBE;
} else {
/* Disable input buffer and enable output buffer */
config = S32_MSCR_OBE;
}
/* Enable output buffer */
if (!input)
config |= S32_MSCR_OBE;
return s32_regmap_update(pctldev, offset, mask, config);
}
@ -511,6 +515,10 @@ static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask,
*config |= S32_MSCR_ODE;
*mask |= S32_MSCR_ODE;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
*config &= ~S32_MSCR_ODE;
*mask |= S32_MSCR_ODE;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
if (arg)
*config |= S32_MSCR_OBE;
@ -549,10 +557,11 @@ static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask,
return 0;
}
static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev,
static int s32_pinconf_mscr_write(struct pinctrl_dev *pctldev,
unsigned int pin_id,
unsigned long *configs,
unsigned int num_configs)
unsigned int num_configs,
enum s32_write_type write_type)
{
struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
unsigned int config = 0, mask = 0;
@ -571,10 +580,20 @@ static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev,
return ret;
}
/* If the MSCR configuration has to be written,
* the SSS field should not be touched.
*/
if (write_type == S32_PINCONF_OVERWRITE)
mask = (unsigned int)~S32_MSCR_SSS_MASK;
if (!config && !mask)
return 0;
dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id, config);
if (write_type == S32_PINCONF_OVERWRITE)
dev_dbg(ipctl->dev, "set: pin %u cfg 0x%x\n", pin_id, config);
else
dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id,
config);
return s32_regmap_update(pctldev, pin_id, mask, config);
}
@ -590,8 +609,8 @@ static int s32_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin_id, unsigned long *configs,
unsigned int num_configs)
{
return s32_pinconf_mscr_update(pctldev, pin_id, configs,
num_configs);
return s32_pinconf_mscr_write(pctldev, pin_id, configs,
num_configs, S32_PINCONF_UPDATE_ONLY);
}
static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector,
@ -604,8 +623,8 @@ static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selecto
grp = &info->groups[selector];
for (i = 0; i < grp->data.npins; i++) {
ret = s32_pinconf_mscr_update(pctldev, grp->data.pins[i],
configs, num_configs);
ret = s32_pinconf_mscr_write(pctldev, grp->data.pins[i],
configs, num_configs, S32_PINCONF_OVERWRITE);
if (ret)
return ret;
}

2
drivers/pinctrl/pinconf-generic.c
View File

@ -44,6 +44,7 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_UV, "input schmitt threshold", "uV", true),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
@ -177,6 +178,7 @@ static const struct pinconf_generic_params dt_params[] = {
{ "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
{ "input-schmitt-microvolts", PIN_CONFIG_INPUT_SCHMITT_UV, 0 },
{ "low-power-disable", PIN_CONFIG_MODE_LOW_POWER, 0 },
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },

575
drivers/pinctrl/pinctrl-eyeq5.c Normal file
View File

@ -0,0 +1,575 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl driver for the Mobileye EyeQ5 platform.
*
* The registers are located in a syscon region called OLB. There are two pin
* banks, each being controlled by 5 registers (see enum eq5p_regs) for
* pull-down, pull-up, drive strength and muxing.
*
* For each pin, muxing is between two functions: (0) GPIO or (1) another one
* that is pin-dependent. Functions are declared statically in this driver.
*
* We create pinctrl groups that are 1:1 equivalent to pins: each group has a
* single pin, and its index/selector is the pin number.
*
* We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
*
* Copyright (C) 2024 Mobileye Vision Technologies Ltd.
*/
#include <linux/array_size.h>
#include <linux/auxiliary_bus.h>
#include <linux/bits.h>
#include <linux/bug.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
struct eq5p_pinctrl {
struct pinctrl_desc desc;
void __iomem *base;
};
enum eq5p_bank {
EQ5P_BANK_A,
EQ5P_BANK_B,
EQ5P_BANK_COUNT,
};
enum eq5p_regs {
EQ5P_PD,
EQ5P_PU,
EQ5P_DS_LOW,
EQ5P_DS_HIGH,
EQ5P_IOCR,
EQ5P_REG_COUNT,
};
static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {
[EQ5P_BANK_A] = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
[EQ5P_BANK_B] = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},
};
/*
* Drive strength; two bits per pin.
*/
#define EQ5P_DS_MASK GENMASK(1, 0)
/*
* Comments to the right of each pin are the "signal name" in the datasheet.
*/
static const struct pinctrl_pin_desc eq5p_pins[] = {
/* Bank A */
PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */
PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */
PINCTRL_PIN(2, "PA2"), /* A2_TIMER1_CK */
PINCTRL_PIN(3, "PA3"), /* A3_TIMER1_EOC */
PINCTRL_PIN(4, "PA4"), /* A4_TIMER2_CK */
PINCTRL_PIN(5, "PA5"), /* A5_TIMER2_EOC */
PINCTRL_PIN(6, "PA6"), /* A6_TIMER5_EXT_INCAP1 */
PINCTRL_PIN(7, "PA7"), /* A7_TIMER5_EXT_INCAP2 */
PINCTRL_PIN(8, "PA8"), /* A8_TIMER5_EXT_OUTCMP1 */
PINCTRL_PIN(9, "PA9"), /* A9_TIMER5_EXT_OUTCMP2 */
PINCTRL_PIN(10, "PA10"), /* A10_UART_0_TX */
PINCTRL_PIN(11, "PA11"), /* A11_UART_0_RX */
PINCTRL_PIN(12, "PA12"), /* A12_UART_1_TX */
PINCTRL_PIN(13, "PA13"), /* A13_UART_1_RX */
PINCTRL_PIN(14, "PA14"), /* A14_CAN_0_TX */
PINCTRL_PIN(15, "PA15"), /* A15_CAN_0_RX */
PINCTRL_PIN(16, "PA16"), /* A16_CAN_1_TX */
PINCTRL_PIN(17, "PA17"), /* A17_CAN_1_RX */
PINCTRL_PIN(18, "PA18"), /* A18_SPI_0_DO */
PINCTRL_PIN(19, "PA19"), /* A19_SPI_0_DI */
PINCTRL_PIN(20, "PA20"), /* A20_SPI_0_CK */
PINCTRL_PIN(21, "PA21"), /* A21_SPI_0_CS0 */
PINCTRL_PIN(22, "PA22"), /* A22_SPI_0_CS1 */
PINCTRL_PIN(23, "PA23"), /* A23_SPI_1_DO */
PINCTRL_PIN(24, "PA24"), /* A24_SPI_1_DI */
PINCTRL_PIN(25, "PA25"), /* A25_SPI_1_CK */
PINCTRL_PIN(26, "PA26"), /* A26_SPI_1_CS0 */
PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */
PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */
#define EQ5P_PIN_OFFSET_BANK_B 29
/* Bank B */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */
};
static const char * const gpio_groups[] = {
/* Bank A */
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
"PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
"PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23",
"PA24", "PA25", "PA26", "PA27", "PA28",
/* Bank B */
"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
"PB8", "PB9", "PB10", "PB11", "PB12", "PB13", "PB14", "PB15",
"PB16", "PB17", "PB18", "PB19", "PB20", "PB21", "PB22",
};
/* Groups of functions on bank A */
static const char * const timer0_groups[] = { "PA0", "PA1" };
static const char * const timer1_groups[] = { "PA2", "PA3" };
static const char * const timer2_groups[] = { "PA4", "PA5" };
static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" };
static const char * const uart0_groups[] = { "PA10", "PA11" };
static const char * const uart1_groups[] = { "PA12", "PA13" };
static const char * const can0_groups[] = { "PA14", "PA15" };
static const char * const can1_groups[] = { "PA16", "PA17" };
static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" };
static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" };
static const char * const refclk0_groups[] = { "PA28" };
/* Groups of functions on bank B */
static const char * const timer3_groups[] = { "PB0", "PB1" };
static const char * const timer4_groups[] = { "PB2", "PB3" };
static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" };
static const char * const uart2_groups[] = { "PB8", "PB9" };
static const char * const can2_groups[] = { "PB10", "PB11" };
static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" };
static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" };
static const char * const mclk0_groups[] = { "PB22" };
static const struct pinfunction eq5p_functions[] = {
/* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */
PINCTRL_PINFUNCTION("gpio", gpio_groups, ARRAY_SIZE(gpio_groups)),
#define GPIO_FUNC_SELECTOR 0
/* Bank A functions */
PINCTRL_PINFUNCTION("timer0", timer0_groups, ARRAY_SIZE(timer0_groups)),
PINCTRL_PINFUNCTION("timer1", timer1_groups, ARRAY_SIZE(timer1_groups)),
PINCTRL_PINFUNCTION("timer2", timer2_groups, ARRAY_SIZE(timer2_groups)),
PINCTRL_PINFUNCTION("timer5", timer5_groups, ARRAY_SIZE(timer5_groups)),
PINCTRL_PINFUNCTION("uart0", uart0_groups, ARRAY_SIZE(uart0_groups)),
PINCTRL_PINFUNCTION("uart1", uart1_groups, ARRAY_SIZE(uart1_groups)),
PINCTRL_PINFUNCTION("can0", can0_groups, ARRAY_SIZE(can0_groups)),
PINCTRL_PINFUNCTION("can1", can1_groups, ARRAY_SIZE(can1_groups)),
PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
PINCTRL_PINFUNCTION("spi1", spi1_groups, ARRAY_SIZE(spi1_groups)),
PINCTRL_PINFUNCTION("refclk0", refclk0_groups, ARRAY_SIZE(refclk0_groups)),
/* Bank B functions */
PINCTRL_PINFUNCTION("timer3", timer3_groups, ARRAY_SIZE(timer3_groups)),
PINCTRL_PINFUNCTION("timer4", timer4_groups, ARRAY_SIZE(timer4_groups)),
PINCTRL_PINFUNCTION("timer6", timer6_groups, ARRAY_SIZE(timer6_groups)),
PINCTRL_PINFUNCTION("uart2", uart2_groups, ARRAY_SIZE(uart2_groups)),
PINCTRL_PINFUNCTION("can2", can2_groups, ARRAY_SIZE(can2_groups)),
PINCTRL_PINFUNCTION("spi2", spi2_groups, ARRAY_SIZE(spi2_groups)),
PINCTRL_PINFUNCTION("spi3", spi3_groups, ARRAY_SIZE(spi3_groups)),
PINCTRL_PINFUNCTION("mclk0", mclk0_groups, ARRAY_SIZE(mclk0_groups)),
};
static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
enum eq5p_bank bank, enum eq5p_regs reg,
u32 mask, u32 val)
{
void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];
writel((readl(ptr) & ~mask) | (val & mask), ptr);
}
static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,
enum eq5p_bank bank, enum eq5p_regs reg, int offset)
{
u32 val = readl(pctrl->base + eq5p_regs[bank][reg]);
if (WARN_ON(offset > 31))
return false;
return (val & BIT(offset)) != 0;
}
static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin)
{
if (pin < EQ5P_PIN_OFFSET_BANK_B)
return EQ5P_BANK_A;
else
return EQ5P_BANK_B;
}
static unsigned int eq5p_pin_to_offset(unsigned int pin)
{
if (pin < EQ5P_PIN_OFFSET_BANK_B)
return pin;
else
return pin - EQ5P_PIN_OFFSET_BANK_B;
}
static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(eq5p_pins);
}
static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return pctldev->desc->pins[selector].name;
}
static int eq5p_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = &pctldev->desc->pins[selector].number;
*num_pins = 1;
return 0;
}
static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
enum pin_config_param param = pinconf_to_config_param(*config);
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int offset = eq5p_pin_to_offset(pin);
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
u32 val_ds, arg;
bool pd, pu;
pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);
pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
arg = !(pd || pu);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = pd;
break;
case PIN_CONFIG_BIAS_PULL_UP:
arg = pu;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
offset *= 2; /* two bits per pin */
if (offset >= 32) {
val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);
offset -= 32;
} else {
val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);
}
arg = (val_ds >> offset) & EQ5P_DS_MASK;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int pin)
{
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const char *pin_name = pctrl->desc.pins[pin].name;
unsigned int offset = eq5p_pin_to_offset(pin);
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
const char *func_name, *bias;
unsigned long ds_config;
u32 drive_strength;
bool pd, pu;
int i, j;
/*
* First, let's get the function name. All pins have only two functions:
* GPIO (IOCR == 0) and something else (IOCR == 1).
*/
if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {
func_name = NULL;
for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) {
if (i == GPIO_FUNC_SELECTOR)
continue;
for (j = 0; j < eq5p_functions[i].ngroups; j++) {
/* Groups and pins are the same thing for us. */
const char *x = eq5p_functions[i].groups[j];
if (strcmp(x, pin_name) == 0) {
func_name = eq5p_functions[i].name;
break;
}
}
if (func_name)
break;
}
/*
* We have not found the function attached to this pin, this
* should never occur as all pins have exactly two functions.
*/
if (!func_name)
func_name = "unknown";
} else {
func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name;
}
/* Second, we retrieve the bias. */
pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);
pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);
if (pd && pu)
bias = "both";
else if (pd && !pu)
bias = "pulldown";
else if (!pd && pu)
bias = "pullup";
else
bias = "none";
/* Third, we get the drive strength. */
ds_config = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 0);
eq5p_pinconf_get(pctldev, pin, &ds_config);
drive_strength = pinconf_to_config_argument(ds_config);
seq_printf(s, "function=%s bias=%s drive_strength=%d",
func_name, bias, drive_strength);
}
static const struct pinctrl_ops eq5p_pinctrl_ops = {
.get_groups_count = eq5p_pinctrl_get_groups_count,
.get_group_name = eq5p_pinctrl_get_group_name,
.get_group_pins = eq5p_pinctrl_get_group_pins,
.pin_dbg_show = eq5p_pinctrl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(eq5p_functions);
}
static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return eq5p_functions[selector].name;
}
static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int *num_groups)
{
*groups = eq5p_functions[selector].groups;
*num_groups = eq5p_functions[selector].ngroups;
return 0;
}
static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int func_selector, unsigned int pin)
{
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const char *func_name = eq5p_functions[func_selector].name;
const char *group_name = pctldev->desc->pins[pin].name;
bool is_gpio = func_selector == GPIO_FUNC_SELECTOR;
unsigned int offset = eq5p_pin_to_offset(pin);
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
u32 mask, val;
dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name);
mask = BIT(offset);
val = is_gpio ? 0 : mask;
eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val);
return 0;
}
static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
/* Pin numbers and group selectors are the same thing in our case. */
return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin);
}
static const struct pinmux_ops eq5p_pinmux_ops = {
.get_functions_count = eq5p_pinmux_get_functions_count,
.get_function_name = eq5p_pinmux_get_function_name,
.get_function_groups = eq5p_pinmux_get_function_groups,
.set_mux = eq5p_pinmux_set_mux,
.gpio_request_enable = eq5p_pinmux_gpio_request_enable,
.strict = true,
};
static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev,
unsigned int pin, u32 arg)
{
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int offset = eq5p_pin_to_offset(pin);
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
unsigned int reg;
u32 mask, val;
if (arg & ~EQ5P_DS_MASK) {
dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg);
return -EINVAL;
}
offset *= 2; /* two bits per pin */
if (offset >= 32) {
reg = EQ5P_DS_HIGH;
offset -= 32;
} else {
reg = EQ5P_DS_LOW;
}
mask = EQ5P_DS_MASK << offset;
val = arg << offset;
eq5p_update_bits(pctrl, bank, reg, mask, val);
return 0;
}
static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const char *pin_name = pctldev->desc->pins[pin].name;
unsigned int offset = eq5p_pin_to_offset(pin);
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
struct device *dev = pctldev->dev;
u32 val = BIT(offset);
unsigned int i;
for (i = 0; i < num_configs; i++) {
enum pin_config_param param = pinconf_to_config_param(configs[i]);
u32 arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
dev_dbg(dev, "pin=%s bias_disable\n", pin_name);
eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);
eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
dev_dbg(dev, "pin=%s bias_pull_down arg=%u\n",
pin_name, arg);
if (arg == 0) /* cannot connect to GND */
return -ENOTSUPP;
eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val);
eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
dev_dbg(dev, "pin=%s bias_pull_up arg=%u\n",
pin_name, arg);
if (arg == 0) /* cannot connect to VDD */
return -ENOTSUPP;
eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);
eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
dev_dbg(dev, "pin=%s drive_strength arg=%u\n",
pin_name, arg);
eq5p_pinconf_set_drive_strength(pctldev, pin, arg);
break;
default:
dev_err(dev, "Unsupported pinconf %u\n", param);
return -ENOTSUPP;
}
}
return 0;
}
static const struct pinconf_ops eq5p_pinconf_ops = {
.is_generic = true,
.pin_config_get = eq5p_pinconf_get,
.pin_config_set = eq5p_pinconf_set,
/* Pins and groups are equivalent in this driver. */
.pin_config_group_get = eq5p_pinconf_get,
.pin_config_group_set = eq5p_pinconf_set,
};
static int eq5p_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct device *dev = &adev->dev;
struct pinctrl_dev *pctldev;
struct eq5p_pinctrl *pctrl;
int ret;
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->base = (void __iomem *)dev_get_platdata(dev);
pctrl->desc.name = dev_name(dev);
pctrl->desc.pins = eq5p_pins;
pctrl->desc.npins = ARRAY_SIZE(eq5p_pins);
pctrl->desc.pctlops = &eq5p_pinctrl_ops;
pctrl->desc.pmxops = &eq5p_pinmux_ops;
pctrl->desc.confops = &eq5p_pinconf_ops;
pctrl->desc.owner = THIS_MODULE;
ret = devm_pinctrl_register_and_init(dev, &pctrl->desc, pctrl, &pctldev);
if (ret)
return dev_err_probe(dev, ret, "failed registering pinctrl device\n");
ret = pinctrl_enable(pctldev);
if (ret)
return dev_err_probe(dev, ret, "failed enabling pinctrl device\n");
return 0;
}
static const struct auxiliary_device_id eq5p_id_table[] = {
{ .name = "clk_eyeq.pinctrl" },
{}
};
MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table);
static struct auxiliary_driver eq5p_driver = {
.probe = eq5p_probe,
.id_table = eq5p_id_table,
};
module_auxiliary_driver(eq5p_driver);

35
drivers/pinctrl/pinctrl-k210.c
View File

@ -925,7 +925,6 @@ static int k210_fpioa_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct k210_fpioa_data *pdata;
int ret;
dev_info(dev, "K210 FPIOA pin controller\n");
@ -940,46 +939,28 @@ static int k210_fpioa_probe(struct platform_device *pdev)
if (IS_ERR(pdata->fpioa))
return PTR_ERR(pdata->fpioa);
pdata->clk = devm_clk_get(dev, "ref");
pdata->clk = devm_clk_get_enabled(dev, "ref");
if (IS_ERR(pdata->clk))
return PTR_ERR(pdata->clk);
ret = clk_prepare_enable(pdata->clk);
if (ret)
return ret;
pdata->pclk = devm_clk_get_optional(dev, "pclk");
if (!IS_ERR(pdata->pclk)) {
ret = clk_prepare_enable(pdata->pclk);
if (ret)
goto disable_clk;
}
pdata->pclk = devm_clk_get_optional_enabled(dev, "pclk");
if (IS_ERR(pdata->pclk))
return PTR_ERR(pdata->pclk);
pdata->sysctl_map =
syscon_regmap_lookup_by_phandle_args(np,
"canaan,k210-sysctl-power",
1, &pdata->power_offset);
if (IS_ERR(pdata->sysctl_map)) {
ret = PTR_ERR(pdata->sysctl_map);
goto disable_pclk;
}
if (IS_ERR(pdata->sysctl_map))
return PTR_ERR(pdata->sysctl_map);
k210_fpioa_init_ties(pdata);
pdata->pctl = pinctrl_register(&k210_pinctrl_desc, dev, (void *)pdata);
if (IS_ERR(pdata->pctl)) {
ret = PTR_ERR(pdata->pctl);
goto disable_pclk;
}
if (IS_ERR(pdata->pctl))
return PTR_ERR(pdata->pctl);
return 0;
disable_pclk:
clk_disable_unprepare(pdata->pclk);
disable_clk:
clk_disable_unprepare(pdata->clk);
return ret;
}
static const struct of_device_id k210_fpioa_dt_ids[] = {

207
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -84,6 +84,27 @@
}, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
iom1, iom2, iom3, \
offset0, offset1, \
offset2, offset3, pull0, \
pull1, pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
{ \
.bank_num = id, \
@ -1120,6 +1141,11 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (ctrl->type == RK3576) {
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
}
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
@ -1234,6 +1260,11 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (ctrl->type == RK3576) {
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
}
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
@ -2038,6 +2069,142 @@ static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RK3576_DRV_BITS_PER_PIN 4
#define RK3576_DRV_PINS_PER_REG 4
#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
#define RK3576_DRV_GPIO1_OFFSET 0x6020
#define RK3576_DRV_GPIO2_OFFSET 0x6040
#define RK3576_DRV_GPIO3_OFFSET 0x6060
#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
if (bank->bank_num == 0 && pin_num < 12)
*reg = RK3576_DRV_GPIO0_AL_OFFSET;
else if (bank->bank_num == 0)
*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
else if (bank->bank_num == 1)
*reg = RK3576_DRV_GPIO1_OFFSET;
else if (bank->bank_num == 2)
*reg = RK3576_DRV_GPIO2_OFFSET;
else if (bank->bank_num == 3)
*reg = RK3576_DRV_GPIO3_OFFSET;
else if (bank->bank_num == 4 && pin_num < 16)
*reg = RK3576_DRV_GPIO4_AL_OFFSET;
else if (bank->bank_num == 4 && pin_num < 24)
*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
else if (bank->bank_num == 4)
*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
else
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3576_DRV_PINS_PER_REG;
*bit *= RK3576_DRV_BITS_PER_PIN;
return 0;
}
#define RK3576_PULL_BITS_PER_PIN 2
#define RK3576_PULL_PINS_PER_REG 8
#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
#define RK3576_PULL_GPIO1_OFFSET 0x6110
#define RK3576_PULL_GPIO2_OFFSET 0x6120
#define RK3576_PULL_GPIO3_OFFSET 0x6130
#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
if (bank->bank_num == 0 && pin_num < 12)
*reg = RK3576_PULL_GPIO0_AL_OFFSET;
else if (bank->bank_num == 0)
*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
else if (bank->bank_num == 1)
*reg = RK3576_PULL_GPIO1_OFFSET;
else if (bank->bank_num == 2)
*reg = RK3576_PULL_GPIO2_OFFSET;
else if (bank->bank_num == 3)
*reg = RK3576_PULL_GPIO3_OFFSET;
else if (bank->bank_num == 4 && pin_num < 16)
*reg = RK3576_PULL_GPIO4_AL_OFFSET;
else if (bank->bank_num == 4 && pin_num < 24)
*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
else if (bank->bank_num == 4)
*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
else
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3576_PULL_PINS_PER_REG;
*bit *= RK3576_PULL_BITS_PER_PIN;
return 0;
}
#define RK3576_SMT_BITS_PER_PIN 1
#define RK3576_SMT_PINS_PER_REG 8
#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
#define RK3576_SMT_GPIO1_OFFSET 0x6210
#define RK3576_SMT_GPIO2_OFFSET 0x6220
#define RK3576_SMT_GPIO3_OFFSET 0x6230
#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
if (bank->bank_num == 0 && pin_num < 12)
*reg = RK3576_SMT_GPIO0_AL_OFFSET;
else if (bank->bank_num == 0)
*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
else if (bank->bank_num == 1)
*reg = RK3576_SMT_GPIO1_OFFSET;
else if (bank->bank_num == 2)
*reg = RK3576_SMT_GPIO2_OFFSET;
else if (bank->bank_num == 3)
*reg = RK3576_SMT_GPIO3_OFFSET;
else if (bank->bank_num == 4 && pin_num < 16)
*reg = RK3576_SMT_GPIO4_AL_OFFSET;
else if (bank->bank_num == 4 && pin_num < 24)
*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
else if (bank->bank_num == 4)
*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
else
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
*bit = pin_num % RK3576_SMT_PINS_PER_REG;
*bit *= RK3576_SMT_BITS_PER_PIN;
return 0;
}
#define RK3588_PMU1_IOC_REG (0x0000)
#define RK3588_PMU2_IOC_REG (0x4000)
#define RK3588_BUS_IOC_REG (0x8000)
@ -2332,6 +2499,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
goto config;
} else if (ctrl->type == RK3576) {
rmask_bits = RK3576_DRV_BITS_PER_PIN;
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
goto config;
}
if (ctrl->type == RV1126) {
@ -2469,6 +2640,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3368:
case RK3399:
case RK3568:
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
data >>= bit;
@ -2528,6 +2700,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3368:
case RK3399:
case RK3568:
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
ret = -EINVAL;
@ -2793,6 +2966,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3368:
case RK3399:
case RK3568:
case RK3576:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
@ -3949,6 +4123,37 @@ static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
};
#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
OFFSET0, OFFSET1, \
OFFSET2, OFFSET3, \
PULL_TYPE_IO_1V8_ONLY, \
PULL_TYPE_IO_1V8_ONLY, \
PULL_TYPE_IO_1V8_ONLY, \
PULL_TYPE_IO_1V8_ONLY)
static struct rockchip_pin_bank rk3576_pin_banks[] = {
RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
};
static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
.pin_banks = rk3576_pin_banks,
.nr_banks = ARRAY_SIZE(rk3576_pin_banks),
.label = "RK3576-GPIO",
.type = RK3576,
.pull_calc_reg = rk3576_calc_pull_reg_and_bit,
.drv_calc_reg = rk3576_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3588_pin_banks[] = {
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
@ -4005,6 +4210,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3399_pin_ctrl },
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
{ .compatible = "rockchip,rk3576-pinctrl",
.data = &rk3576_pin_ctrl },
{ .compatible = "rockchip,rk3588-pinctrl",
.data = &rk3588_pin_ctrl },
{},

1
drivers/pinctrl/pinctrl-rockchip.h
View File

@ -197,6 +197,7 @@ enum rockchip_pinctrl_type {
RK3368,
RK3399,
RK3568,
RK3576,
RK3588,
};

3
drivers/pinctrl/pinctrl-single.c
View File

@ -1913,7 +1913,8 @@ static int pcs_probe(struct platform_device *pdev)
dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
if (pinctrl_enable(pcs->pctl))
ret = pinctrl_enable(pcs->pctl);
if (ret)
goto free;
return 0;

5
drivers/pinctrl/pinctrl-stmfx.c
View File

@ -11,6 +11,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/string_choices.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
@ -369,14 +370,14 @@ static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
return;
if (dir == GPIO_LINE_DIRECTION_OUT) {
seq_printf(s, "output %s ", val ? "high" : "low");
seq_printf(s, "output %s ", str_high_low(val));
if (type)
seq_printf(s, "open drain %s internal pull-up ",
pupd ? "with" : "without");
else
seq_puts(s, "push pull no pull ");
} else {
seq_printf(s, "input %s ", val ? "high" : "low");
seq_printf(s, "input %s ", str_high_low(val));
if (type)
seq_printf(s, "with internal pull-%s ",
pupd ? "up" : "down");

4
drivers/pinctrl/pinctrl-utils.c
View File

@ -70,8 +70,8 @@ int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
dup_configs = kmemdup_array(configs, num_configs,
sizeof(*dup_configs), GFP_KERNEL);
if (!dup_configs)
return -ENOMEM;

1
drivers/pinctrl/pinctrl-zynq.c
View File

@ -1202,6 +1202,7 @@ static const struct of_device_id zynq_pinctrl_of_match[] = {
{ .compatible = "xlnx,pinctrl-zynq" },
{ }
};
MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match);
static struct platform_driver zynq_pinctrl_driver = {
.driver = {

7
drivers/pinctrl/pinmux.c
View File

@ -442,8 +442,7 @@ int pinmux_enable_setting(const struct pinctrl_setting *setting)
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_err_probe(pctldev->dev, ret,
"could not request pin %d (%s) from group %s "
" on device %s\n",
"could not request pin %d (%s) from group %s on device %s\n",
pins[i], pname, gname,
pinctrl_dev_get_name(pctldev));
goto err_pin_request;
@ -526,9 +525,7 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting)
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"not freeing pin %d (%s) as part of "
"deactivating group %s - it is already "
"used for some other setting",
"not freeing pin %d (%s) as part of deactivating group %s - it is already used for some other setting",
pins[i], desc->name, gname);
}
}

2
drivers/pinctrl/realtek/pinctrl-rtd.c
View File

@ -533,7 +533,7 @@ static const struct pinconf_ops rtd_pinconf_ops = {
.pin_config_group_set = rtd_pin_config_group_set,
};
static struct regmap_config rtd_pinctrl_regmap_config = {
static const struct regmap_config rtd_pinctrl_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,

117
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -16,6 +16,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
@ -51,17 +52,15 @@
#define PIN_CFG_IO_VMC_QSPI BIT(7)
#define PIN_CFG_IO_VMC_ETH0 BIT(8)
#define PIN_CFG_IO_VMC_ETH1 BIT(9)
#define PIN_CFG_FILONOFF BIT(10)
#define PIN_CFG_FILNUM BIT(11)
#define PIN_CFG_FILCLKSEL BIT(12)
#define PIN_CFG_IOLH_C BIT(13)
#define PIN_CFG_SOFT_PS BIT(14)
#define PIN_CFG_OEN BIT(15)
#define PIN_CFG_NOGPIO_INT BIT(16)
#define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */
#define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */
#define PIN_CFG_ELC BIT(19)
#define PIN_CFG_IOLH_RZV2H BIT(20)
#define PIN_CFG_NF BIT(10) /* Digital noise filter */
#define PIN_CFG_IOLH_C BIT(11)
#define PIN_CFG_SOFT_PS BIT(12)
#define PIN_CFG_OEN BIT(13)
#define PIN_CFG_NOGPIO_INT BIT(14)
#define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
#define PIN_CFG_ELC BIT(17)
#define PIN_CFG_IOLH_RZV2H BIT(18)
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
@ -69,9 +68,7 @@
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
(PIN_CFG_IOLH_##group | \
PIN_CFG_PUPD | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
PIN_CFG_FILCLKSEL)
PIN_CFG_NF)
#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
PIN_CFG_SR)
@ -84,10 +81,7 @@
PIN_CFG_SR | \
PIN_CFG_SMT)
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
PIN_CFG_FILCLKSEL)
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
@ -394,13 +388,13 @@ static const u64 r9a09g057_variable_pin_cfg[] = {
#ifdef CONFIG_RISCV
static const u64 r9a07g043f_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_NF |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_NF |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_NF |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
@ -431,7 +425,7 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_NF |
PIN_CFG_NOGPIO_INT),
};
#endif
@ -528,8 +522,7 @@ static int rzg2l_map_add_config(struct pinctrl_map *map,
{
unsigned long *cfgs;
cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
GFP_KERNEL);
cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
if (!cfgs)
return -ENOMEM;
@ -1261,7 +1254,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
if (!(cfg & PIN_CFG_OEN))
return -EINVAL;
if (!pctrl->data->oen_read)
return -EOPNOTSUPP;
arg = pctrl->data->oen_read(pctrl, _pin);
if (!arg)
@ -1390,9 +1385,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(_configs[i]);
arg = pinconf_to_config_argument(_configs[i]);
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_IEN))
return -EINVAL;
@ -1401,8 +1396,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
if (!(cfg & PIN_CFG_OEN))
return -EINVAL;
if (!pctrl->data->oen_write)
return -EOPNOTSUPP;
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
if (ret)
@ -1410,12 +1406,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_POWER_SOURCE:
settings.power_source = pinconf_to_config_argument(_configs[i]);
settings.power_source = arg;
break;
case PIN_CONFIG_SLEW_RATE:
arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_SR) || arg > 1)
return -EINVAL;
@ -1436,8 +1430,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
return -EINVAL;
@ -1457,12 +1449,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
!hwcfg->drive_strength_ua)
return -EINVAL;
settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]);
settings.drive_strength_ua = arg;
break;
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
return -EINVAL;
@ -1480,7 +1470,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
if (!(cfg & PIN_CFG_IOLH_RZV2H))
return -EINVAL;
arg = pinconf_to_config_argument(_configs[i]);
if (arg > 3)
return -EINVAL;
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
@ -1883,8 +1872,7 @@ static const u64 r9a07g043_gpio_configs[] = {
#ifdef CONFIG_RISCV
/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
@ -1892,8 +1880,7 @@ static const u64 r9a07g043_gpio_configs[] = {
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
PIN_CFG_NOGPIO_INT), /* P25 */
0x0, /* P26 */
0x0, /* P27 */
@ -1971,8 +1958,7 @@ static const struct {
struct rzg2l_dedicated_configs rzg2l_pins[7];
} rzg2l_dedicated_pins = {
.common = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
@ -2053,8 +2039,7 @@ static const struct {
};
static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
PIN_CFG_FILCLKSEL)) },
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
PIN_CFG_SOFT_PS)) },
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
@ -2093,8 +2078,7 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
};
static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
PIN_CFG_FILCLKSEL)) },
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
PIN_CFG_IEN)) },
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
@ -2596,16 +2580,13 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
return -EPROBE_DEFER;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
if (ret) {
dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n");
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
of_args.args[2] != pctrl->data->n_port_pins) {
dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
return -EINVAL;
}
of_args.args[2] != pctrl->data->n_port_pins)
return dev_err_probe(pctrl->dev, -EINVAL,
"gpio-ranges does not match selected SOC\n");
chip->names = pctrl->data->port_pins;
chip->request = rzg2l_gpio_request;
@ -2623,7 +2604,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
girq = &chip->irq;
gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
girq->fwnode = of_node_to_fwnode(np);
girq->fwnode = dev_fwnode(pctrl->dev);
girq->parent_domain = parent_domain;
girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
@ -2637,10 +2618,8 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
pctrl->gpio_range.name = chip->label;
pctrl->gpio_range.gc = chip;
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO controller\n");
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n");
dev_dbg(pctrl->dev, "Registered gpio controller\n");
@ -2726,22 +2705,16 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
&pctrl->pctl);
if (ret) {
dev_err(pctrl->dev, "pinctrl registration failed\n");
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n");
ret = pinctrl_enable(pctrl->pctl);
if (ret) {
dev_err(pctrl->dev, "pinctrl enable failed\n");
return ret;
}
if (ret)
dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
ret = rzg2l_gpio_register(pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
return ret;
}
if (ret)
return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n");
return 0;
}

3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
View File

@ -196,8 +196,7 @@ static int rzv2m_map_add_config(struct pinctrl_map *map,
{
unsigned long *cfgs;
cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
GFP_KERNEL);
cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
if (!cfgs)
return -ENOMEM;

3
drivers/pinctrl/renesas/pinctrl.c
View File

@ -83,8 +83,7 @@ static int sh_pfc_map_add_config(struct pinctrl_map *map,
{
unsigned long *cfgs;
cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
GFP_KERNEL);
cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
if (cfgs == NULL)
return -ENOMEM;

14
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
View File

@ -40,6 +40,19 @@ static const struct samsung_pin_bank_type bank_type_alive = {
#define S5P_OTHERS_RET_MMC (1 << 29)
#define S5P_OTHERS_RET_UART (1 << 28)
#define S5P_PIN_PULL_DISABLE 0
#define S5P_PIN_PULL_DOWN 1
#define S5P_PIN_PULL_UP 2
static void s5pv210_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
{
unsigned int *pud_val = drvdata->pud_val;
pud_val[PUD_PULL_DISABLE] = S5P_PIN_PULL_DISABLE;
pud_val[PUD_PULL_DOWN] = S5P_PIN_PULL_DOWN;
pud_val[PUD_PULL_UP] = S5P_PIN_PULL_UP;
}
static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
{
void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
@ -133,6 +146,7 @@ static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
.nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.pud_value_init = s5pv210_pud_value_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &s5pv210_retention_data,

16
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@ -662,7 +662,7 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
__init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
{
struct device *dev = d->dev;
struct device_node *wkup_np = NULL;
struct device_node *wkup_np __free(device_node) = NULL;
struct device_node *np;
struct samsung_pin_bank *bank;
struct exynos_weint_data *weint_data;
@ -692,17 +692,14 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
GFP_KERNEL);
if (!bank->irq_chip) {
of_node_put(wkup_np);
if (!bank->irq_chip)
return -ENOMEM;
}
bank->irq_chip->chip.name = bank->name;
bank->irq_domain = irq_domain_create_linear(bank->fwnode,
bank->nr_pins, &exynos_eint_irqd_ops, bank);
if (!bank->irq_domain) {
dev_err(dev, "wkup irq domain add failed\n");
of_node_put(wkup_np);
return -ENXIO;
}
@ -715,10 +712,8 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
weint_data = devm_kcalloc(dev,
bank->nr_pins, sizeof(*weint_data),
GFP_KERNEL);
if (!weint_data) {
of_node_put(wkup_np);
if (!weint_data)
return -ENOMEM;
}
for (idx = 0; idx < bank->nr_pins; ++idx) {
irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
@ -735,13 +730,10 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
}
}
if (!muxed_banks) {
of_node_put(wkup_np);
if (!muxed_banks)
return 0;
}
irq = irq_of_parse_and_map(wkup_np, 0);
of_node_put(wkup_np);
if (!irq) {
dev_err(dev, "irq number for muxed EINTs not found\n");
return 0;

14
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
View File

@ -63,6 +63,10 @@
#define EINT_CON_MASK 0xF
#define EINT_CON_LEN 4
#define S3C_PIN_PULL_DISABLE 0
#define S3C_PIN_PULL_DOWN 1
#define S3C_PIN_PULL_UP 2
static const struct samsung_pin_bank_type bank_type_4bit_off = {
.fld_width = { 4, 1, 2, 0, 2, 2, },
.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
@ -255,6 +259,15 @@ static int s3c64xx_irq_get_trigger(unsigned int type)
return trigger;
}
static void s3c64xx_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
{
unsigned int *pud_val = drvdata->pud_val;
pud_val[PUD_PULL_DISABLE] = S3C_PIN_PULL_DISABLE;
pud_val[PUD_PULL_DOWN] = S3C_PIN_PULL_DOWN;
pud_val[PUD_PULL_UP] = S3C_PIN_PULL_UP;
}
static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
{
/* Edge- and level-triggered interrupts need different handlers */
@ -797,6 +810,7 @@ static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
.nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
.eint_gpio_init = s3c64xx_eint_gpio_init,
.eint_wkup_init = s3c64xx_eint_eint0_init,
.pud_value_init = s3c64xx_pud_value_init,
},
};

108
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -122,8 +122,8 @@ static int add_map_configs(struct device *dev, struct pinctrl_map **map,
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs),
GFP_KERNEL);
if (!dup_configs)
return -ENOMEM;
@ -251,7 +251,6 @@ static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
{
struct samsung_pinctrl_drv_data *drvdata;
unsigned reserved_maps;
struct device_node *np;
int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
@ -266,12 +265,11 @@ static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
&reserved_maps,
num_maps);
for_each_child_of_node(np_config, np) {
for_each_child_of_node_scoped(np_config, np) {
ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
samsung_dt_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}
@ -823,16 +821,16 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions(
struct device_node *func_np;
if (!of_get_child_count(cfg_np)) {
if (!of_find_property(cfg_np,
"samsung,pin-function", NULL))
if (!of_property_present(cfg_np,
"samsung,pin-function"))
continue;
++func_cnt;
continue;
}
for_each_child_of_node(cfg_np, func_np) {
if (!of_find_property(func_np,
"samsung,pin-function", NULL))
if (!of_property_present(func_np,
"samsung,pin-function"))
continue;
++func_cnt;
}
@ -849,16 +847,12 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions(
* and create pin groups and pin function lists.
*/
func_cnt = 0;
for_each_child_of_node(dev_np, cfg_np) {
struct device_node *func_np;
for_each_child_of_node_scoped(dev_np, cfg_np) {
if (!of_get_child_count(cfg_np)) {
ret = samsung_pinctrl_create_function(dev, drvdata,
cfg_np, func);
if (ret < 0) {
of_node_put(cfg_np);
if (ret < 0)
return ERR_PTR(ret);
}
if (ret > 0) {
++func;
++func_cnt;
@ -866,14 +860,11 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions(
continue;
}
for_each_child_of_node(cfg_np, func_np) {
for_each_child_of_node_scoped(cfg_np, func_np) {
ret = samsung_pinctrl_create_function(dev, drvdata,
func_np, func);
if (ret < 0) {
of_node_put(func_np);
of_node_put(cfg_np);
if (ret < 0)
return ERR_PTR(ret);
}
if (ret > 0) {
++func;
++func_cnt;
@ -997,6 +988,77 @@ static int samsung_pinctrl_unregister(struct platform_device *pdev,
return 0;
}
static void samsung_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
{
unsigned int *pud_val = drvdata->pud_val;
pud_val[PUD_PULL_DISABLE] = EXYNOS_PIN_PUD_PULL_DISABLE;
pud_val[PUD_PULL_DOWN] = EXYNOS_PIN_PID_PULL_DOWN;
pud_val[PUD_PULL_UP] = EXYNOS_PIN_PID_PULL_UP;
}
/*
* Enable or Disable the pull-down and pull-up for the gpio pins in the
* PUD register.
*/
static void samsung_gpio_set_pud(struct gpio_chip *gc, unsigned int offset,
unsigned int value)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
void __iomem *reg;
unsigned int data, mask;
reg = bank->pctl_base + bank->pctl_offset;
data = readl(reg + type->reg_offset[PINCFG_TYPE_PUD]);
mask = (1 << type->fld_width[PINCFG_TYPE_PUD]) - 1;
data &= ~(mask << (offset * type->fld_width[PINCFG_TYPE_PUD]));
data |= value << (offset * type->fld_width[PINCFG_TYPE_PUD]);
writel(data, reg + type->reg_offset[PINCFG_TYPE_PUD]);
}
/*
* Identify the type of PUD config based on the gpiolib request to enable
* or disable the PUD config.
*/
static int samsung_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned int value;
int ret = 0;
unsigned long flags;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_BIAS_DISABLE:
value = drvdata->pud_val[PUD_PULL_DISABLE];
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
value = drvdata->pud_val[PUD_PULL_DOWN];
break;
case PIN_CONFIG_BIAS_PULL_UP:
value = drvdata->pud_val[PUD_PULL_UP];
break;
default:
return -ENOTSUPP;
}
ret = clk_enable(drvdata->pclk);
if (ret) {
dev_err(drvdata->dev, "failed to enable clock\n");
return ret;
}
raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_pud(gc, offset, value);
raw_spin_unlock_irqrestore(&bank->slock, flags);
clk_disable(drvdata->pclk);
return ret;
}
static const struct gpio_chip samsung_gpiolib_chip = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
@ -1006,6 +1068,7 @@ static const struct gpio_chip samsung_gpiolib_chip = {
.direction_output = samsung_gpio_direction_output,
.to_irq = samsung_gpio_to_irq,
.add_pin_ranges = samsung_add_pin_ranges,
.set_config = samsung_gpio_set_config,
.owner = THIS_MODULE,
};
@ -1237,6 +1300,11 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
if (ctrl->eint_wkup_init)
ctrl->eint_wkup_init(drvdata);
if (ctrl->pud_value_init)
ctrl->pud_value_init(drvdata);
else
samsung_pud_value_init(drvdata);
ret = samsung_gpiolib_register(pdev, drvdata);
if (ret)
goto err_unregister;

21
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -61,6 +61,25 @@ enum pincfg_type {
#define PIN_CON_FUNC_INPUT 0x0
#define PIN_CON_FUNC_OUTPUT 0x1
/* Values for the pin PUD register */
#define EXYNOS_PIN_PUD_PULL_DISABLE 0x0
#define EXYNOS_PIN_PID_PULL_DOWN 0x1
#define EXYNOS_PIN_PID_PULL_UP 0x3
/*
* enum pud_index - Possible index values to access the pud_val array.
* @PUD_PULL_DISABLE: Index for the value of pud disable
* @PUD_PULL_DOWN: Index for the value of pull down enable
* @PUD_PULL_UP: Index for the value of pull up enable
* @PUD_MAX: Maximum value of the index
*/
enum pud_index {
PUD_PULL_DISABLE,
PUD_PULL_DOWN,
PUD_PULL_UP,
PUD_MAX,
};
/**
* enum eint_type - possible external interrupt types.
* @EINT_TYPE_NONE: bank does not support external interrupts
@ -261,6 +280,7 @@ struct samsung_pin_ctrl {
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata);
void (*suspend)(struct samsung_pinctrl_drv_data *);
void (*resume)(struct samsung_pinctrl_drv_data *);
};
@ -307,6 +327,7 @@ struct samsung_pinctrl_drv_data {
struct samsung_pin_bank *pin_banks;
unsigned int nr_banks;
unsigned int nr_pins;
unsigned int pud_val[PUD_MAX];
struct samsung_retention_ctrl *retention_ctrl;

54
drivers/pinctrl/sophgo/Kconfig Normal file
View File

@ -0,0 +1,54 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Sophgo SoC PINCTRL drivers
#
config PINCTRL_SOPHGO_CV18XX
bool
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
config PINCTRL_SOPHGO_CV1800B
tristate "Sophgo CV1800B SoC Pinctrl driver"
depends on ARCH_SOPHGO || COMPILE_TEST
depends on OF
select PINCTRL_SOPHGO_CV18XX
help
Say Y to select the pinctrl driver for CV1800B SoC.
This pin controller allows selecting the mux function for
each pin. This driver can also be built as a module called
pinctrl-cv1800b.
config PINCTRL_SOPHGO_CV1812H
tristate "Sophgo CV1812H SoC Pinctrl driver"
depends on ARCH_SOPHGO || COMPILE_TEST
depends on OF
select PINCTRL_SOPHGO_CV18XX
help
Say Y to select the pinctrl driver for CV1812H SoC.
This pin controller allows selecting the mux function for
each pin. This driver can also be built as a module called
pinctrl-cv1812h.
config PINCTRL_SOPHGO_SG2000
tristate "Sophgo SG2000 SoC Pinctrl driver"
depends on ARCH_SOPHGO || COMPILE_TEST
depends on OF
select PINCTRL_SOPHGO_CV18XX
help
Say Y to select the pinctrl driver for SG2000 SoC.
This pin controller allows selecting the mux function for
each pin. This driver can also be built as a module called
pinctrl-sg2000.
config PINCTRL_SOPHGO_SG2002
tristate "Sophgo SG2000 SoC Pinctrl driver"
depends on ARCH_SOPHGO || COMPILE_TEST
depends on OF
select PINCTRL_SOPHGO_CV18XX
help
Say Y to select the pinctrl driver for SG2002 SoC.
This pin controller allows selecting the mux function for
each pin. This driver can also be built as a module called
pinctrl-sg2002.

7
drivers/pinctrl/sophgo/Makefile Normal file
View File

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_SOPHGO_CV18XX) += pinctrl-cv18xx.o
obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o
obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o
obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o
obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o

462
drivers/pinctrl/sophgo/pinctrl-cv1800b.c Normal file
View File

@ -0,0 +1,462 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Sophgo CV1800B SoC pinctrl driver.
*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
#include "pinctrl-cv18xx.h"
enum CV1800B_POWER_DOMAIN {
VDD18A_AUD = 0,
VDD18A_USB_PLL_ETH_CSI = 1,
VDD33A_ETH_USB_SD1 = 2,
VDDIO_RTC = 3,
VDDIO_SD0_SPI = 4
};
static const char *const cv1800b_power_domain_desc[] = {
[VDD18A_AUD] = "VDD18A_AUD",
[VDD18A_USB_PLL_ETH_CSI] = "VDD18A_USB_PLL_ETH_CSI",
[VDD33A_ETH_USB_SD1] = "VDD33A_ETH_USB_SD1",
[VDDIO_RTC] = "VDDIO_RTC",
[VDDIO_SD0_SPI] = "VDDIO_SD0_SPI",
};
static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 79000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 60000;
if (pstate == PIN_POWER_STATE_3V3)
return 60000;
return -EINVAL;
}
return -ENOTSUPP;
}
static int cv1800b_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 87000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 61000;
if (pstate == PIN_POWER_STATE_3V3)
return 62000;
return -EINVAL;
}
return -ENOTSUPP;
}
static const u32 cv1800b_1v8_oc_map[] = {
12800,
25300,
37400,
49000
};
static const u32 cv1800b_18od33_1v8_oc_map[] = {
7800,
11700,
15500,
19200,
23000,
26600,
30200,
33700
};
static const u32 cv1800b_18od33_3v3_oc_map[] = {
5500,
8200,
10800,
13400,
16100,
18700,
21200,
23700
};
static const u32 cv1800b_eth_oc_map[] = {
15700,
17800
};
static int cv1800b_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = cv1800b_1v8_oc_map;
return ARRAY_SIZE(cv1800b_1v8_oc_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = cv1800b_18od33_1v8_oc_map;
return ARRAY_SIZE(cv1800b_18od33_1v8_oc_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = cv1800b_18od33_3v3_oc_map;
return ARRAY_SIZE(cv1800b_18od33_3v3_oc_map);
}
}
if (type == IO_TYPE_ETH) {
*map = cv1800b_eth_oc_map;
return ARRAY_SIZE(cv1800b_eth_oc_map);
}
return -ENOTSUPP;
}
static const u32 cv1800b_1v8_schmitt_map[] = {
0,
970000,
1040000
};
static const u32 cv1800b_18od33_1v8_schmitt_map[] = {
0,
1070000
};
static const u32 cv1800b_18od33_3v3_schmitt_map[] = {
0,
1100000
};
static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = cv1800b_1v8_schmitt_map;
return ARRAY_SIZE(cv1800b_1v8_schmitt_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = cv1800b_18od33_1v8_schmitt_map;
return ARRAY_SIZE(cv1800b_18od33_1v8_schmitt_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = cv1800b_18od33_3v3_schmitt_map;
return ARRAY_SIZE(cv1800b_18od33_3v3_schmitt_map);
}
}
return -ENOTSUPP;
}
static const struct cv1800_vddio_cfg_ops cv1800b_vddio_cfg_ops = {
.get_pull_up = cv1800b_get_pull_up,
.get_pull_down = cv1800b_get_pull_down,
.get_oc_map = cv1800b_get_oc_map,
.get_schmitt_map = cv1800b_get_schmitt_map,
};
static const struct pinctrl_pin_desc cv1800b_pins[] = {
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
PINCTRL_PIN(PIN_SPINOR_HOLD_X, "SPINOR_HOLD_X"),
PINCTRL_PIN(PIN_SPINOR_SCK, "SPINOR_SCK"),
PINCTRL_PIN(PIN_SPINOR_MOSI, "SPINOR_MOSI"),
PINCTRL_PIN(PIN_SPINOR_WP_X, "SPINOR_WP_X"),
PINCTRL_PIN(PIN_SPINOR_MISO, "SPINOR_MISO"),
PINCTRL_PIN(PIN_SPINOR_CS_X, "SPINOR_CS_X"),
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
PINCTRL_PIN(PIN_AUX0, "AUX0"),
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
PINCTRL_PIN(PIN_SD1_GPIO0, "SD1_GPIO0"),
PINCTRL_PIN(PIN_SD1_GPIO1, "SD1_GPIO1"),
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
PINCTRL_PIN(PIN_ADC1, "ADC1"),
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
};
static const struct cv1800_pin cv1800b_pin_data[ARRAY_SIZE(cv1800b_pins)] = {
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_AUD,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x12c, 6),
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x000, 7,
CV1800_PINCONF_AREA_SYS, 0xa00),
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x004, 7,
CV1800_PINCONF_AREA_SYS, 0xa04),
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x008, 7,
CV1800_PINCONF_AREA_SYS, 0xa08),
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x00c, 7,
CV1800_PINCONF_AREA_SYS, 0xa0c),
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x010, 7,
CV1800_PINCONF_AREA_SYS, 0xa10),
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x014, 7,
CV1800_PINCONF_AREA_SYS, 0xa14),
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x018, 3,
CV1800_PINCONF_AREA_SYS, 0x900),
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x01c, 3,
CV1800_PINCONF_AREA_SYS, 0x904),
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x020, 3,
CV1800_PINCONF_AREA_SYS, 0x908),
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x024, 7,
CV1800_PINCONF_AREA_SYS, 0x90c),
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x028, 7,
CV1800_PINCONF_AREA_SYS, 0x910),
CV1800_GENERAL_PIN(PIN_SPINOR_HOLD_X, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x02c, 3,
CV1800_PINCONF_AREA_SYS, 0x914),
CV1800_GENERAL_PIN(PIN_SPINOR_SCK, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x030, 3,
CV1800_PINCONF_AREA_SYS, 0x918),
CV1800_GENERAL_PIN(PIN_SPINOR_MOSI, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x034, 3,
CV1800_PINCONF_AREA_SYS, 0x91c),
CV1800_GENERAL_PIN(PIN_SPINOR_WP_X, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x038, 3,
CV1800_PINCONF_AREA_SYS, 0x920),
CV1800_GENERAL_PIN(PIN_SPINOR_MISO, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
CV1800_PINCONF_AREA_SYS, 0x924),
CV1800_GENERAL_PIN(PIN_SPINOR_CS_X, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x040, 3,
CV1800_PINCONF_AREA_SYS, 0x928),
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x04c, 7,
CV1800_PINCONF_AREA_SYS, 0x934),
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x050, 7,
CV1800_PINCONF_AREA_SYS, 0x938),
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_SPI,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x054, 7,
CV1800_PINCONF_AREA_SYS, 0x93c),
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x05c, 0,
CV1800_PINCONF_AREA_RTC, 0x004),
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x068, 3,
CV1800_PINCONF_AREA_RTC, 0x010),
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x074, 0,
CV1800_PINCONF_AREA_RTC, 0x020),
CV1800_GENERAL_PIN(PIN_SD1_GPIO0, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x088, 7,
CV1800_PINCONF_AREA_RTC, 0x034),
CV1800_GENERAL_PIN(PIN_SD1_GPIO1, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x084, 7,
CV1800_PINCONF_AREA_RTC, 0x030),
CV1800_GENERAL_PIN(PIN_SD1_D3, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x08c, 7,
CV1800_PINCONF_AREA_RTC, 0x038),
CV1800_GENERAL_PIN(PIN_SD1_D2, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x090, 7,
CV1800_PINCONF_AREA_RTC, 0x03c),
CV1800_GENERAL_PIN(PIN_SD1_D1, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x094, 7,
CV1800_PINCONF_AREA_RTC, 0x040),
CV1800_GENERAL_PIN(PIN_SD1_D0, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x098, 7,
CV1800_PINCONF_AREA_RTC, 0x044),
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x09c, 7,
CV1800_PINCONF_AREA_RTC, 0x048),
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDD33A_ETH_USB_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0a0, 7,
CV1800_PINCONF_AREA_RTC, 0x04c),
CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a8, 6,
CV1800_PINCONF_AREA_SYS, 0x804),
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ac, 6,
CV1800_PINCONF_AREA_SYS, 0x808),
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x0c0, 7),
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x0c4, 7),
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x0c8, 7),
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x0cc, 7),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
CV1800_PINCONF_AREA_SYS, 0x0bc, 7,
CV1800_PINCONF_AREA_SYS, 0xc04),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
CV1800_PINCONF_AREA_SYS, 0x0b8, 7,
CV1800_PINCONF_AREA_SYS, 0xc08),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
CV1800_PINCONF_AREA_SYS, 0x0b0, 7,
CV1800_PINCONF_AREA_SYS, 0xc0c),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
CV1800_PINCONF_AREA_SYS, 0x0b4, 7,
CV1800_PINCONF_AREA_SYS, 0xc10),
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
CV1800_PINCONF_AREA_SYS, 0xc14),
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0e8, 7,
CV1800_PINCONF_AREA_SYS, 0xc18),
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ec, 7,
CV1800_PINCONF_AREA_SYS, 0xc1c),
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f0, 7,
CV1800_PINCONF_AREA_SYS, 0xc20),
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f4, 7,
CV1800_PINCONF_AREA_SYS, 0xc24),
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_USB_PLL_ETH_CSI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f8, 7,
CV1800_PINCONF_AREA_SYS, 0xc28),
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_AUD,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x120, 5),
};
static const struct cv1800_pinctrl_data cv1800b_pindata = {
.pins = cv1800b_pins,
.pindata = cv1800b_pin_data,
.pdnames = cv1800b_power_domain_desc,
.vddio_ops = &cv1800b_vddio_cfg_ops,
.npins = ARRAY_SIZE(cv1800b_pins),
.npd = ARRAY_SIZE(cv1800b_power_domain_desc),
};
static const struct of_device_id cv1800b_pinctrl_ids[] = {
{ .compatible = "sophgo,cv1800b-pinctrl", .data = &cv1800b_pindata },
{ }
};
MODULE_DEVICE_TABLE(of, cv1800b_pinctrl_ids);
static struct platform_driver cv1800b_pinctrl_driver = {
.probe = cv1800_pinctrl_probe,
.driver = {
.name = "cv1800b-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = cv1800b_pinctrl_ids,
},
};
module_platform_driver(cv1800b_pinctrl_driver);
MODULE_DESCRIPTION("Pinctrl driver for the CV1800B series SoC");
MODULE_LICENSE("GPL");

771
drivers/pinctrl/sophgo/pinctrl-cv1812h.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Sophgo CV1812H SoC pinctrl driver.
*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "pinctrl-cv18xx.h"
enum CV1812H_POWER_DOMAIN {
VDD18A_EPHY = 0,
VDD18A_MIPI = 1,
VDDIO18_1 = 2,
VDDIO_EMMC = 3,
VDDIO_RTC = 4,
VDDIO_SD0 = 5,
VDDIO_SD1 = 6,
VDDIO_VIVO = 7
};
static const char *const cv1812h_power_domain_desc[] = {
[VDD18A_EPHY] = "VDD18A_EPHY",
[VDD18A_MIPI] = "VDD18A_MIPI",
[VDDIO18_1] = "VDDIO18_1",
[VDDIO_EMMC] = "VDDIO_EMMC",
[VDDIO_RTC] = "VDDIO_RTC",
[VDDIO_SD0] = "VDDIO_SD0",
[VDDIO_SD1] = "VDDIO_SD1",
[VDDIO_VIVO] = "VDDIO_VIVO",
};
static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 79000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 60000;
if (pstate == PIN_POWER_STATE_3V3)
return 60000;
return -EINVAL;
}
return -ENOTSUPP;
}
static int cv1812h_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 87000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 61000;
if (pstate == PIN_POWER_STATE_3V3)
return 62000;
return -EINVAL;
}
return -ENOTSUPP;
}
static const u32 cv1812h_1v8_oc_map[] = {
12800,
25300,
37400,
49000
};
static const u32 cv1812h_18od33_1v8_oc_map[] = {
7800,
11700,
15500,
19200,
23000,
26600,
30200,
33700
};
static const u32 cv1812h_18od33_3v3_oc_map[] = {
5500,
8200,
10800,
13400,
16100,
18700,
21200,
23700
};
static const u32 cv1812h_eth_oc_map[] = {
15700,
17800
};
static int cv1812h_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = cv1812h_1v8_oc_map;
return ARRAY_SIZE(cv1812h_1v8_oc_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = cv1812h_18od33_1v8_oc_map;
return ARRAY_SIZE(cv1812h_18od33_1v8_oc_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = cv1812h_18od33_3v3_oc_map;
return ARRAY_SIZE(cv1812h_18od33_3v3_oc_map);
}
}
if (type == IO_TYPE_ETH) {
*map = cv1812h_eth_oc_map;
return ARRAY_SIZE(cv1812h_eth_oc_map);
}
return -ENOTSUPP;
}
static const u32 cv1812h_1v8_schmitt_map[] = {
0,
970000,
1040000
};
static const u32 cv1812h_18od33_1v8_schmitt_map[] = {
0,
1070000
};
static const u32 cv1812h_18od33_3v3_schmitt_map[] = {
0,
1100000
};
static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = cv1812h_1v8_schmitt_map;
return ARRAY_SIZE(cv1812h_1v8_schmitt_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = cv1812h_18od33_1v8_schmitt_map;
return ARRAY_SIZE(cv1812h_18od33_1v8_schmitt_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = cv1812h_18od33_3v3_schmitt_map;
return ARRAY_SIZE(cv1812h_18od33_3v3_schmitt_map);
}
}
return -ENOTSUPP;
}
static const struct cv1800_vddio_cfg_ops cv1812h_vddio_cfg_ops = {
.get_pull_up = cv1812h_get_pull_up,
.get_pull_down = cv1812h_get_pull_down,
.get_oc_map = cv1812h_get_oc_map,
.get_schmitt_map = cv1812h_get_schmitt_map,
};
static const struct pinctrl_pin_desc cv1812h_pins[] = {
PINCTRL_PIN(PIN_MIPI_TXM4, "MIPI_TXM4"),
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
PINCTRL_PIN(PIN_VIVO_D2, "VIVO_D2"),
PINCTRL_PIN(PIN_VIVO_D3, "VIVO_D3"),
PINCTRL_PIN(PIN_VIVO_D10, "VIVO_D10"),
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
PINCTRL_PIN(PIN_MIPI_TXP3, "MIPI_TXP3"),
PINCTRL_PIN(PIN_MIPI_TXM3, "MIPI_TXM3"),
PINCTRL_PIN(PIN_MIPI_TXP4, "MIPI_TXP4"),
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
PINCTRL_PIN(PIN_MIPIRX5N, "MIPIRX5N"),
PINCTRL_PIN(PIN_VIVO_D1, "VIVO_D1"),
PINCTRL_PIN(PIN_VIVO_D5, "VIVO_D5"),
PINCTRL_PIN(PIN_VIVO_D7, "VIVO_D7"),
PINCTRL_PIN(PIN_VIVO_D9, "VIVO_D9"),
PINCTRL_PIN(PIN_USB_ID, "USB_ID"),
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
PINCTRL_PIN(PIN_CAM_PD0, "CAM_PD0"),
PINCTRL_PIN(PIN_CAM_MCLK0, "CAM_MCLK0"),
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
PINCTRL_PIN(PIN_MIPIRX5P, "MIPIRX5P"),
PINCTRL_PIN(PIN_VIVO_CLK, "VIVO_CLK"),
PINCTRL_PIN(PIN_VIVO_D6, "VIVO_D6"),
PINCTRL_PIN(PIN_VIVO_D8, "VIVO_D8"),
PINCTRL_PIN(PIN_USB_VBUS_EN, "USB_VBUS_EN"),
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
PINCTRL_PIN(PIN_CAM_MCLK1, "CAM_MCLK1"),
PINCTRL_PIN(PIN_IIC3_SCL, "IIC3_SCL"),
PINCTRL_PIN(PIN_VIVO_D4, "VIVO_D4"),
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
PINCTRL_PIN(PIN_CAM_PD1, "CAM_PD1"),
PINCTRL_PIN(PIN_CAM_RST0, "CAM_RST0"),
PINCTRL_PIN(PIN_VIVO_D0, "VIVO_D0"),
PINCTRL_PIN(PIN_ADC1, "ADC1"),
PINCTRL_PIN(PIN_ADC2, "ADC2"),
PINCTRL_PIN(PIN_ADC3, "ADC3"),
PINCTRL_PIN(PIN_AUD_AOUTL, "AUD_AOUTL"),
PINCTRL_PIN(PIN_IIC3_SDA, "IIC3_SDA"),
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
PINCTRL_PIN(PIN_RSTN, "RSTN"),
PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
PINCTRL_PIN(PIN_AUD_AINR_MIC, "AUD_AINR_MIC"),
PINCTRL_PIN(PIN_IIC2_SCL, "IIC2_SCL"),
PINCTRL_PIN(PIN_IIC2_SDA, "IIC2_SDA"),
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
PINCTRL_PIN(PIN_UART2_RX, "UART2_RX"),
PINCTRL_PIN(PIN_UART2_CTS, "UART2_CTS"),
PINCTRL_PIN(PIN_UART2_TX, "UART2_TX"),
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
PINCTRL_PIN(PIN_CLK32K, "CLK32K"),
PINCTRL_PIN(PIN_UART2_RTS, "UART2_RTS"),
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
PINCTRL_PIN(PIN_JTAG_CPU_TRST, "JTAG_CPU_TRST"),
PINCTRL_PIN(PIN_PWR_ON, "PWR_ON"),
PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
PINCTRL_PIN(PIN_CLK25M, "CLK25M"),
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
PINCTRL_PIN(PIN_PWR_WAKEUP1, "PWR_WAKEUP1"),
PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
PINCTRL_PIN(PIN_EMMC_RSTN, "EMMC_RSTN"),
PINCTRL_PIN(PIN_AUX0, "AUX0"),
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
PINCTRL_PIN(PIN_PWR_SEQ3, "PWR_SEQ3"),
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
};
static const struct cv1800_pin cv1812h_pin_data[ARRAY_SIZE(cv1812h_pins)] = {
CV1800_GENERAL_PIN(PIN_MIPI_TXM4, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x194, 7,
CV1800_PINCONF_AREA_SYS, 0xc60),
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x18c, 7,
CV1800_PINCONF_AREA_SYS, 0xc58),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x178, 7,
CV1800_PINCONF_AREA_SYS, 0x118, 7,
CV1800_PINCONF_AREA_SYS, 0xc44),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x170, 7,
CV1800_PINCONF_AREA_SYS, 0x11c, 7,
CV1800_PINCONF_AREA_SYS, 0xc3c),
CV1800_GENERAL_PIN(PIN_VIVO_D2, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x154, 7,
CV1800_PINCONF_AREA_SYS, 0xc20),
CV1800_GENERAL_PIN(PIN_VIVO_D3, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x150, 7,
CV1800_PINCONF_AREA_SYS, 0xc1c),
CV1800_GENERAL_PIN(PIN_VIVO_D10, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x134, 7,
CV1800_PINCONF_AREA_SYS, 0xc00),
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x108, 5,
CV1800_PINCONF_AREA_SYS, 0x820),
CV1800_GENERAL_PIN(PIN_MIPI_TXP3, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a0, 7,
CV1800_PINCONF_AREA_SYS, 0xc6c),
CV1800_GENERAL_PIN(PIN_MIPI_TXM3, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x19c, 7,
CV1800_PINCONF_AREA_SYS, 0xc68),
CV1800_GENERAL_PIN(PIN_MIPI_TXP4, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x198, 7,
CV1800_PINCONF_AREA_SYS, 0xc64),
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x190, 7,
CV1800_PINCONF_AREA_SYS, 0xc5c),
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x184, 7,
CV1800_PINCONF_AREA_SYS, 0xc50),
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x17c, 7,
CV1800_PINCONF_AREA_SYS, 0xc48),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x16c, 7,
CV1800_PINCONF_AREA_SYS, 0x120, 7,
CV1800_PINCONF_AREA_SYS, 0xc38),
CV1800_GENERAL_PIN(PIN_MIPIRX5N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x164, 7,
CV1800_PINCONF_AREA_SYS, 0xc30),
CV1800_GENERAL_PIN(PIN_VIVO_D1, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x158, 7,
CV1800_PINCONF_AREA_SYS, 0xc24),
CV1800_GENERAL_PIN(PIN_VIVO_D5, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x148, 7,
CV1800_PINCONF_AREA_SYS, 0xc14),
CV1800_GENERAL_PIN(PIN_VIVO_D7, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x140, 7,
CV1800_PINCONF_AREA_SYS, 0xc0c),
CV1800_GENERAL_PIN(PIN_VIVO_D9, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x138, 7,
CV1800_PINCONF_AREA_SYS, 0xc04),
CV1800_GENERAL_PIN(PIN_USB_ID, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0fc, 3,
CV1800_PINCONF_AREA_SYS, 0x814),
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x130, 7),
CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
CV1800_PINCONF_AREA_SYS, 0xc74),
CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
CV1800_PINCONF_AREA_SYS, 0xc70),
CV1800_GENERAL_PIN(PIN_CAM_PD0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x004, 4,
CV1800_PINCONF_AREA_SYS, 0xb04),
CV1800_GENERAL_PIN(PIN_CAM_MCLK0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x000, 3,
CV1800_PINCONF_AREA_SYS, 0xb00),
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x188, 7,
CV1800_PINCONF_AREA_SYS, 0xc54),
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x180, 7,
CV1800_PINCONF_AREA_SYS, 0xc4c),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x174, 7,
CV1800_PINCONF_AREA_SYS, 0x114, 7,
CV1800_PINCONF_AREA_SYS, 0xc40),
CV1800_GENERAL_PIN(PIN_MIPIRX5P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x168, 7,
CV1800_PINCONF_AREA_SYS, 0xc34),
CV1800_GENERAL_PIN(PIN_VIVO_CLK, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x160, 7,
CV1800_PINCONF_AREA_SYS, 0xc2c),
CV1800_GENERAL_PIN(PIN_VIVO_D6, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x144, 7,
CV1800_PINCONF_AREA_SYS, 0xc10),
CV1800_GENERAL_PIN(PIN_VIVO_D8, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x13c, 7,
CV1800_PINCONF_AREA_SYS, 0xc08),
CV1800_GENERAL_PIN(PIN_USB_VBUS_EN, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x100, 3,
CV1800_PINCONF_AREA_SYS, 0x818),
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x12c, 7),
CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
CV1800_PINCONF_AREA_SYS, 0xc8c),
CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
CV1800_PINCONF_AREA_SYS, 0xc7c),
CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
CV1800_PINCONF_AREA_SYS, 0xc78),
CV1800_GENERAL_PIN(PIN_CAM_MCLK1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x00c, 4,
CV1800_PINCONF_AREA_SYS, 0xb0c),
CV1800_GENERAL_PIN(PIN_IIC3_SCL, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x014, 3,
CV1800_PINCONF_AREA_SYS, 0xb14),
CV1800_GENERAL_PIN(PIN_VIVO_D4, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x14c, 7,
CV1800_PINCONF_AREA_SYS, 0xc18),
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x128, 7),
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x124, 7),
CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
CV1800_PINCONF_AREA_SYS, 0xc84),
CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
CV1800_PINCONF_AREA_SYS, 0xc80),
CV1800_GENERAL_PIN(PIN_CAM_PD1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x010, 6,
CV1800_PINCONF_AREA_SYS, 0xb10),
CV1800_GENERAL_PIN(PIN_CAM_RST0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x008, 6,
CV1800_PINCONF_AREA_SYS, 0xb08),
CV1800_GENERAL_PIN(PIN_VIVO_D0, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x15c, 7,
CV1800_PINCONF_AREA_SYS, 0xc28),
CV1800_GENERAL_PIN(PIN_ADC1, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
CV1800_PINCONF_AREA_SYS, 0x810),
CV1800_GENERAL_PIN(PIN_ADC2, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f4, 7,
CV1800_PINCONF_AREA_SYS, 0x80c),
CV1800_GENERAL_PIN(PIN_ADC3, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f0, 7,
CV1800_PINCONF_AREA_SYS, 0x808),
CV1800_FUNC_PIN(PIN_AUD_AOUTL, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c4, 5),
CV1800_GENERAL_PIN(PIN_IIC3_SDA, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x018, 3,
CV1800_PINCONF_AREA_SYS, 0xb18),
CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
CV1800_PINCONF_AREA_RTC, 0x05c),
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
CV1800_PINCONF_AREA_RTC, 0x058),
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
CV1800_PINCONF_AREA_RTC, 0x06c),
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
CV1800_PINCONF_AREA_RTC, 0x068),
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
CV1800_GENERAL_PIN(PIN_RSTN, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0e8, 0,
CV1800_PINCONF_AREA_SYS, 0x800),
CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
CV1800_PINCONF_AREA_SYS, 0x804),
CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
CV1800_PINCONF_AREA_RTC, 0x060),
CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
CV1800_PINCONF_AREA_RTC, 0x064),
CV1800_FUNC_PIN(PIN_AUD_AINR_MIC, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c0, 6),
CV1800_GENERAL_PIN(PIN_IIC2_SCL, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0b8, 7,
CV1800_PINCONF_AREA_RTC, 0x040),
CV1800_GENERAL_PIN(PIN_IIC2_SDA, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0bc, 7,
CV1800_PINCONF_AREA_RTC, 0x044),
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x034, 3,
CV1800_PINCONF_AREA_SYS, 0x900),
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x028, 7,
CV1800_PINCONF_AREA_SYS, 0xa0c),
CV1800_GENERAL_PIN(PIN_UART2_RX, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0c8, 7,
CV1800_PINCONF_AREA_RTC, 0x050),
CV1800_GENERAL_PIN(PIN_UART2_CTS, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0cc, 7,
CV1800_PINCONF_AREA_RTC, 0x054),
CV1800_GENERAL_PIN(PIN_UART2_TX, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0c0, 7,
CV1800_PINCONF_AREA_RTC, 0x048),
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x01c, 7,
CV1800_PINCONF_AREA_SYS, 0xa00),
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x024, 7,
CV1800_PINCONF_AREA_SYS, 0xa08),
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x020, 7,
CV1800_PINCONF_AREA_SYS, 0xa04),
CV1800_GENERAL_PIN(PIN_CLK32K, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0b0, 7,
CV1800_PINCONF_AREA_RTC, 0x038),
CV1800_GENERAL_PIN(PIN_UART2_RTS, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0c4, 7,
CV1800_PINCONF_AREA_RTC, 0x04c),
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x030, 7,
CV1800_PINCONF_AREA_SYS, 0xa14),
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x02c, 7,
CV1800_PINCONF_AREA_SYS, 0xa10),
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x044, 7,
CV1800_PINCONF_AREA_SYS, 0x910),
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x040, 7,
CV1800_PINCONF_AREA_SYS, 0x90c),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TRST, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x06c, 6,
CV1800_PINCONF_AREA_SYS, 0x938),
CV1800_GENERAL_PIN(PIN_PWR_ON, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x09c, 7,
CV1800_PINCONF_AREA_RTC, 0x024),
CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
CV1800_PINCONF_AREA_RTC, 0x034),
CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
CV1800_PINCONF_AREA_RTC, 0x02c),
CV1800_GENERAL_PIN(PIN_CLK25M, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0b4, 7,
CV1800_PINCONF_AREA_RTC, 0x03c),
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x038, 3,
CV1800_PINCONF_AREA_SYS, 0x904),
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
CV1800_PINCONF_AREA_SYS, 0x908),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x068, 7,
CV1800_PINCONF_AREA_SYS, 0x934),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x064, 7,
CV1800_PINCONF_AREA_SYS, 0x930),
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x094, 7,
CV1800_PINCONF_AREA_RTC, 0x01c),
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x090, 7,
CV1800_PINCONF_AREA_RTC, 0x018),
CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
CV1800_PINCONF_AREA_RTC, 0x030),
CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x058, 3,
CV1800_PINCONF_AREA_SYS, 0x924),
CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x054, 3,
CV1800_PINCONF_AREA_SYS, 0x920),
CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x04c, 3,
CV1800_PINCONF_AREA_SYS, 0x918),
CV1800_GENERAL_PIN(PIN_EMMC_RSTN, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x048, 4,
CV1800_PINCONF_AREA_SYS, 0x914),
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x078, 7,
CV1800_PINCONF_AREA_SYS, 0x944),
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x074, 7,
CV1800_PINCONF_AREA_SYS, 0x940),
CV1800_GENERAL_PIN(PIN_PWR_SEQ3, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x08c, 3,
CV1800_PINCONF_AREA_RTC, 0x010),
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x07c, 0,
CV1800_PINCONF_AREA_RTC, 0x000),
CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x084, 3,
CV1800_PINCONF_AREA_RTC, 0x008),
CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x098, 7,
CV1800_PINCONF_AREA_RTC, 0x020),
CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x060, 3,
CV1800_PINCONF_AREA_SYS, 0x92c),
CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x05c, 3,
CV1800_PINCONF_AREA_SYS, 0x928),
CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x050, 3,
CV1800_PINCONF_AREA_SYS, 0x91c),
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x070, 7,
CV1800_PINCONF_AREA_SYS, 0x93c),
CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
CV1800_PINCONF_AREA_RTC, 0x0e0),
CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x080, 0,
CV1800_PINCONF_AREA_RTC, 0x004),
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x088, 3,
CV1800_PINCONF_AREA_RTC, 0x00c),
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
CV1800_PINCONF_AREA_RTC, 0x028),
};
static const struct cv1800_pinctrl_data cv1812h_pindata = {
.pins = cv1812h_pins,
.pindata = cv1812h_pin_data,
.pdnames = cv1812h_power_domain_desc,
.vddio_ops = &cv1812h_vddio_cfg_ops,
.npins = ARRAY_SIZE(cv1812h_pins),
.npd = ARRAY_SIZE(cv1812h_power_domain_desc),
};
static const struct of_device_id cv1812h_pinctrl_ids[] = {
{ .compatible = "sophgo,cv1812h-pinctrl", .data = &cv1812h_pindata },
{ }
};
MODULE_DEVICE_TABLE(of, cv1812h_pinctrl_ids);
static struct platform_driver cv1812h_pinctrl_driver = {
.probe = cv1800_pinctrl_probe,
.driver = {
.name = "cv1812h-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = cv1812h_pinctrl_ids,
},
};
module_platform_driver(cv1812h_pinctrl_driver);
MODULE_DESCRIPTION("Pinctrl driver for the CV1812H series SoC");
MODULE_LICENSE("GPL");

765
drivers/pinctrl/sophgo/pinctrl-cv18xx.c Normal file
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@ -0,0 +1,765 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Sophgo CV18XX SoCs pinctrl driver.
*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
*/
#include <linux/bitfield.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/bsearch.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "../pinconf.h"
#include "../pinmux.h"
#include "pinctrl-cv18xx.h"
struct cv1800_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl_dev;
const struct cv1800_pinctrl_data *data;
struct pinctrl_desc pdesc;
u32 *power_cfg;
struct mutex mutex;
raw_spinlock_t lock;
void __iomem *regs[2];
};
struct cv1800_pin_mux_config {
struct cv1800_pin *pin;
u32 config;
};
static unsigned int cv1800_dt_get_pin(u32 value)
{
return value & GENMASK(15, 0);
}
static unsigned int cv1800_dt_get_pin_mux(u32 value)
{
return (value >> 16) & GENMASK(7, 0);
}
static unsigned int cv1800_dt_get_pin_mux2(u32 value)
{
return (value >> 24) & GENMASK(7, 0);
}
#define cv1800_pinctrl_get_component_addr(pctrl, _comp) \
((pctrl)->regs[(_comp)->area] + (_comp)->offset)
static int cv1800_cmp_pin(const void *key, const void *pivot)
{
const struct cv1800_pin *pin = pivot;
int pin_id = (long)key;
int pivid = pin->pin;
return pin_id - pivid;
}
static int cv1800_set_power_cfg(struct cv1800_pinctrl *pctrl,
u8 domain, u32 cfg)
{
if (domain >= pctrl->data->npd)
return -ENOTSUPP;
if (pctrl->power_cfg[domain] && pctrl->power_cfg[domain] != cfg)
return -EINVAL;
pctrl->power_cfg[domain] = cfg;
return 0;
}
static int cv1800_get_power_cfg(struct cv1800_pinctrl *pctrl,
u8 domain)
{
return pctrl->power_cfg[domain];
}
static struct cv1800_pin *cv1800_get_pin(struct cv1800_pinctrl *pctrl,
unsigned long pin)
{
return bsearch((void *)pin, pctrl->data->pindata, pctrl->data->npins,
sizeof(struct cv1800_pin), cv1800_cmp_pin);
}
#define PIN_BGA_ID_OFFSET 8
#define PIN_BGA_ID_MASK 0xff
static const char *const io_type_desc[] = {
"1V8",
"18OD33",
"AUDIO",
"ETH"
};
static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl,
u8 domain)
{
return pctrl->data->pdnames[domain];
}
static void cv1800_pctrl_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *seq, unsigned int pin_id)
{
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 value;
void __iomem *reg;
if (pin->pin >> PIN_BGA_ID_OFFSET)
seq_printf(seq, "pos: %c%u ",
'A' + (pin->pin >> PIN_BGA_ID_OFFSET) - 1,
pin->pin & PIN_BGA_ID_MASK);
else
seq_printf(seq, "pos: %u ", pin->pin);
seq_printf(seq, "power-domain: %s ",
cv1800_get_power_cfg_desc(pctrl, pin->power_domain));
seq_printf(seq, "type: %s ", io_type_desc[type]);
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux);
value = readl(reg);
seq_printf(seq, "mux: 0x%08x ", value);
if (pin->flags & CV1800_PIN_HAVE_MUX2) {
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2);
value = readl(reg);
seq_printf(seq, "mux2: 0x%08x ", value);
}
if (type == IO_TYPE_1V8_ONLY || type == IO_TYPE_1V8_OR_3V3) {
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf);
value = readl(reg);
seq_printf(seq, "conf: 0x%08x ", value);
}
}
static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *config)
{
unsigned int mux = cv1800_dt_get_pin_mux(config->config);
unsigned int mux2 = cv1800_dt_get_pin_mux2(config->config);
if (mux > config->pin->mux.max)
return -EINVAL;
if (config->pin->flags & CV1800_PIN_HAVE_MUX2) {
if (mux != config->pin->mux2.pfunc)
return -EINVAL;
if (mux2 > config->pin->mux2.max)
return -EINVAL;
} else {
if (mux2 != PIN_MUX_INVALD)
return -ENOTSUPP;
}
return 0;
}
static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux,
unsigned long npins)
{
enum cv1800_pin_io_type type;
u8 power_domain;
int i;
if (npins == 1)
return 0;
type = cv1800_pin_io_type(mux[0].pin);
power_domain = mux[0].pin->power_domain;
for (i = 0; i < npins; i++) {
if (type != cv1800_pin_io_type(mux[i].pin) ||
power_domain != mux[i].pin->power_domain)
return -ENOTSUPP;
}
return 0;
}
static int cv1800_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **maps,
unsigned int *num_maps)
{
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = pctrl->dev;
struct device_node *child;
struct pinctrl_map *map;
const char **grpnames;
const char *grpname;
int ngroups = 0;
int nmaps = 0;
int ret;
for_each_available_child_of_node(np, child)
ngroups += 1;
grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL);
if (!grpnames)
return -ENOMEM;
map = devm_kcalloc(dev, ngroups * 2, sizeof(*map), GFP_KERNEL);
if (!map)
return -ENOMEM;
ngroups = 0;
mutex_lock(&pctrl->mutex);
for_each_available_child_of_node(np, child) {
int npins = of_property_count_u32_elems(child, "pinmux");
unsigned int *pins;
struct cv1800_pin_mux_config *pinmuxs;
u32 config, power;
int i;
if (npins < 1) {
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n",
np, child);
ret = -EINVAL;
goto dt_failed;
}
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn",
np, child);
if (!grpname) {
ret = -ENOMEM;
goto dt_failed;
}
grpnames[ngroups++] = grpname;
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
if (!pins) {
ret = -ENOMEM;
goto dt_failed;
}
pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL);
if (!pinmuxs) {
ret = -ENOMEM;
goto dt_failed;
}
for (i = 0; i < npins; i++) {
ret = of_property_read_u32_index(child, "pinmux",
i, &config);
if (ret)
goto dt_failed;
pins[i] = cv1800_dt_get_pin(config);
pinmuxs[i].config = config;
pinmuxs[i].pin = cv1800_get_pin(pctrl, pins[i]);
if (!pinmuxs[i].pin) {
dev_err(dev, "failed to get pin %d\n", pins[i]);
ret = -ENODEV;
goto dt_failed;
}
ret = cv1800_verify_pinmux_config(&pinmuxs[i]);
if (ret) {
dev_err(dev, "group %s pin %d is invalid\n",
grpname, i);
goto dt_failed;
}
}
ret = cv1800_verify_pin_group(pinmuxs, npins);
if (ret) {
dev_err(dev, "group %s is invalid\n", grpname);
goto dt_failed;
}
ret = of_property_read_u32(child, "power-source", &power);
if (ret)
goto dt_failed;
if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) {
dev_err(dev, "group %s have unsupported power: %u\n",
grpname, power);
ret = -ENOTSUPP;
goto dt_failed;
}
ret = cv1800_set_power_cfg(pctrl, pinmuxs[0].pin->power_domain,
power);
if (ret)
goto dt_failed;
map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
map[nmaps].data.mux.function = np->name;
map[nmaps].data.mux.group = grpname;
nmaps += 1;
ret = pinconf_generic_parse_dt_config(child, pctldev,
&map[nmaps].data.configs.configs,
&map[nmaps].data.configs.num_configs);
if (ret) {
dev_err(dev, "failed to parse pin config of group %s: %d\n",
grpname, ret);
goto dt_failed;
}
ret = pinctrl_generic_add_group(pctldev, grpname,
pins, npins, pinmuxs);
if (ret < 0) {
dev_err(dev, "failed to add group %s: %d\n", grpname, ret);
goto dt_failed;
}
/* don't create a map if there are no pinconf settings */
if (map[nmaps].data.configs.num_configs == 0)
continue;
map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
map[nmaps].data.configs.group_or_pin = grpname;
nmaps += 1;
}
ret = pinmux_generic_add_function(pctldev, np->name,
grpnames, ngroups, NULL);
if (ret < 0) {
dev_err(dev, "error adding function %s: %d\n", np->name, ret);
goto function_failed;
}
*maps = map;
*num_maps = nmaps;
mutex_unlock(&pctrl->mutex);
return 0;
dt_failed:
of_node_put(child);
function_failed:
pinctrl_utils_free_map(pctldev, map, nmaps);
mutex_unlock(&pctrl->mutex);
return ret;
}
static const struct pinctrl_ops cv1800_pctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.pin_dbg_show = cv1800_pctrl_dbg_show,
.dt_node_to_map = cv1800_pctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int cv1800_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned int fsel, unsigned int gsel)
{
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct group_desc *group;
const struct cv1800_pin_mux_config *configs;
unsigned int i;
group = pinctrl_generic_get_group(pctldev, gsel);
if (!group)
return -EINVAL;
configs = group->data;
for (i = 0; i < group->grp.npins; i++) {
const struct cv1800_pin *pin = configs[i].pin;
u32 value = configs[i].config;
void __iomem *reg_mux;
void __iomem *reg_mux2;
unsigned long flags;
u32 mux;
u32 mux2;
reg_mux = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux);
reg_mux2 = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2);
mux = cv1800_dt_get_pin_mux(value);
mux2 = cv1800_dt_get_pin_mux2(value);
raw_spin_lock_irqsave(&pctrl->lock, flags);
writel_relaxed(mux, reg_mux);
if (mux2 != PIN_MUX_INVALD)
writel_relaxed(mux2, reg_mux2);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
return 0;
}
static const struct pinmux_ops cv1800_pmx_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = cv1800_pmx_set_mux,
.strict = true,
};
#define PIN_IO_PULLUP BIT(2)
#define PIN_IO_PULLDOWN BIT(3)
#define PIN_IO_DRIVE GENMASK(7, 5)
#define PIN_IO_SCHMITT GENMASK(9, 8)
#define PIN_IO_BUS_HOLD BIT(10)
#define PIN_IO_OUT_FAST_SLEW BIT(11)
static u32 cv1800_pull_down_typical_resistor(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin)
{
return pctrl->data->vddio_ops->get_pull_down(pin, pctrl->power_cfg);
}
static u32 cv1800_pull_up_typical_resistor(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin)
{
return pctrl->data->vddio_ops->get_pull_up(pin, pctrl->power_cfg);
}
static int cv1800_pinctrl_oc2reg(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin, u32 target)
{
const u32 *map;
int i, len;
len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map);
if (len < 0)
return len;
for (i = 0; i < len; i++) {
if (map[i] >= target)
return i;
}
return -EINVAL;
}
static int cv1800_pinctrl_reg2oc(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin, u32 reg)
{
const u32 *map;
int len;
len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map);
if (len < 0)
return len;
if (reg >= len)
return -EINVAL;
return map[reg];
}
static int cv1800_pinctrl_schmitt2reg(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin, u32 target)
{
const u32 *map;
int i, len;
len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg,
&map);
if (len < 0)
return len;
for (i = 0; i < len; i++) {
if (map[i] == target)
return i;
}
return -EINVAL;
}
static int cv1800_pinctrl_reg2schmitt(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin, u32 reg)
{
const u32 *map;
int len;
len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg,
&map);
if (len < 0)
return len;
if (reg >= len)
return -EINVAL;
return map[reg];
}
static int cv1800_pconf_get(struct pinctrl_dev *pctldev,
unsigned int pin_id, unsigned long *config)
{
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
int param = pinconf_to_config_param(*config);
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
enum cv1800_pin_io_type type;
u32 value;
u32 arg;
bool enabled;
int ret;
if (!pin)
return -EINVAL;
type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO)
return -ENOTSUPP;
value = readl(cv1800_pinctrl_get_component_addr(pctrl, &pin->conf));
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
enabled = FIELD_GET(PIN_IO_PULLDOWN, value);
arg = cv1800_pull_down_typical_resistor(pctrl, pin);
break;
case PIN_CONFIG_BIAS_PULL_UP:
enabled = FIELD_GET(PIN_IO_PULLUP, value);
arg = cv1800_pull_up_typical_resistor(pctrl, pin);
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
enabled = true;
arg = FIELD_GET(PIN_IO_DRIVE, value);
ret = cv1800_pinctrl_reg2oc(pctrl, pin, arg);
if (ret < 0)
return ret;
arg = ret;
break;
case PIN_CONFIG_INPUT_SCHMITT_UV:
arg = FIELD_GET(PIN_IO_SCHMITT, value);
ret = cv1800_pinctrl_reg2schmitt(pctrl, pin, arg);
if (ret < 0)
return ret;
arg = ret;
enabled = arg != 0;
break;
case PIN_CONFIG_POWER_SOURCE:
enabled = true;
arg = cv1800_get_power_cfg(pctrl, pin->power_domain);
break;
case PIN_CONFIG_SLEW_RATE:
enabled = true;
arg = FIELD_GET(PIN_IO_OUT_FAST_SLEW, value);
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
arg = FIELD_GET(PIN_IO_BUS_HOLD, value);
enabled = arg != 0;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return enabled ? 0 : -EINVAL;
}
static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl,
struct cv1800_pin *pin,
unsigned long *configs,
unsigned int num_configs,
u32 *value)
{
int i;
u32 v = 0;
enum cv1800_pin_io_type type;
int ret;
if (!pin)
return -EINVAL;
type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO)
return -ENOTSUPP;
for (i = 0; i < num_configs; i++) {
int param = pinconf_to_config_param(configs[i]);
u32 arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
v &= ~PIN_IO_PULLDOWN;
v |= FIELD_PREP(PIN_IO_PULLDOWN, arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
v &= ~PIN_IO_PULLUP;
v |= FIELD_PREP(PIN_IO_PULLUP, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
ret = cv1800_pinctrl_oc2reg(pctrl, pin, arg);
if (ret < 0)
return ret;
v &= ~PIN_IO_DRIVE;
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
break;
case PIN_CONFIG_INPUT_SCHMITT_UV:
ret = cv1800_pinctrl_schmitt2reg(pctrl, pin, arg);
if (ret < 0)
return ret;
v &= ~PIN_IO_SCHMITT;
v |= FIELD_PREP(PIN_IO_SCHMITT, ret);
break;
case PIN_CONFIG_POWER_SOURCE:
/* Ignore power source as it is always fixed */
break;
case PIN_CONFIG_SLEW_RATE:
v &= ~PIN_IO_OUT_FAST_SLEW;
v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg);
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
v &= ~PIN_IO_BUS_HOLD;
v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg);
break;
default:
return -ENOTSUPP;
}
}
*value = v;
return 0;
}
static int cv1800_pin_set_config(struct cv1800_pinctrl *pctrl,
unsigned int pin_id,
u32 value)
{
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
unsigned long flags;
void __iomem *addr;
if (!pin)
return -EINVAL;
addr = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf);
raw_spin_lock_irqsave(&pctrl->lock, flags);
writel(value, addr);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static int cv1800_pconf_set(struct pinctrl_dev *pctldev,
unsigned int pin_id, unsigned long *configs,
unsigned int num_configs)
{
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
u32 value;
if (!pin)
return -ENODEV;
if (cv1800_pinconf_compute_config(pctrl, pin,
configs, num_configs, &value))
return -ENOTSUPP;
return cv1800_pin_set_config(pctrl, pin_id, value);
}
static int cv1800_pconf_group_set(struct pinctrl_dev *pctldev,
unsigned int gsel,
unsigned long *configs,
unsigned int num_configs)
{
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct group_desc *group;
const struct cv1800_pin_mux_config *pinmuxs;
u32 value;
int i;
group = pinctrl_generic_get_group(pctldev, gsel);
if (!group)
return -EINVAL;
pinmuxs = group->data;
if (cv1800_pinconf_compute_config(pctrl, pinmuxs[0].pin,
configs, num_configs, &value))
return -ENOTSUPP;
for (i = 0; i < group->grp.npins; i++)
cv1800_pin_set_config(pctrl, group->grp.pins[i], value);
return 0;
}
static const struct pinconf_ops cv1800_pconf_ops = {
.pin_config_get = cv1800_pconf_get,
.pin_config_set = cv1800_pconf_set,
.pin_config_group_set = cv1800_pconf_group_set,
.is_generic = true,
};
int cv1800_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cv1800_pinctrl *pctrl;
const struct cv1800_pinctrl_data *pctrl_data;
int ret;
pctrl_data = device_get_match_data(dev);
if (!pctrl_data)
return -ENODEV;
if (pctrl_data->npins == 0 || pctrl_data->npd == 0)
return dev_err_probe(dev, -EINVAL, "invalid pin data\n");
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->power_cfg = devm_kcalloc(dev, pctrl_data->npd,
sizeof(u32), GFP_KERNEL);
if (!pctrl->power_cfg)
return -ENOMEM;
pctrl->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys");
if (IS_ERR(pctrl->regs[0]))
return PTR_ERR(pctrl->regs[0]);
pctrl->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc");
if (IS_ERR(pctrl->regs[1]))
return PTR_ERR(pctrl->regs[1]);
pctrl->pdesc.name = dev_name(dev);
pctrl->pdesc.pins = pctrl_data->pins;
pctrl->pdesc.npins = pctrl_data->npins;
pctrl->pdesc.pctlops = &cv1800_pctrl_ops;
pctrl->pdesc.pmxops = &cv1800_pmx_ops;
pctrl->pdesc.confops = &cv1800_pconf_ops;
pctrl->pdesc.owner = THIS_MODULE;
pctrl->data = pctrl_data;
pctrl->dev = dev;
raw_spin_lock_init(&pctrl->lock);
mutex_init(&pctrl->mutex);
platform_set_drvdata(pdev, pctrl);
ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc,
pctrl, &pctrl->pctl_dev);
if (ret)
return dev_err_probe(dev, ret,
"fail to register pinctrl driver\n");
return pinctrl_enable(pctrl->pctl_dev);
}
EXPORT_SYMBOL_GPL(cv1800_pinctrl_probe);

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drivers/pinctrl/sophgo/pinctrl-cv18xx.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*/
#ifndef _PINCTRL_SOPHGO_CV18XX_H
#define _PINCTRL_SOPHGO_CV18XX_H
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
enum cv1800_pin_io_type {
IO_TYPE_1V8_ONLY = 0,
IO_TYPE_1V8_OR_3V3 = 1,
IO_TYPE_AUDIO = 2,
IO_TYPE_ETH = 3
};
#define CV1800_PINCONF_AREA_SYS 0
#define CV1800_PINCONF_AREA_RTC 1
struct cv1800_pinmux {
u16 offset;
u8 area;
u8 max;
};
struct cv1800_pinmux2 {
u16 offset;
u8 area;
u8 max;
u8 pfunc;
};
struct cv1800_pinconf {
u16 offset;
u8 area;
};
#define CV1800_PIN_HAVE_MUX2 BIT(0)
#define CV1800_PIN_IO_TYPE GENMASK(2, 1)
#define CV1800_PIN_FLAG_IO_TYPE(type) \
FIELD_PREP_CONST(CV1800_PIN_IO_TYPE, type)
struct cv1800_pin {
u16 pin;
u16 flags;
u8 power_domain;
struct cv1800_pinmux mux;
struct cv1800_pinmux2 mux2;
struct cv1800_pinconf conf;
};
#define PIN_POWER_STATE_1V8 1800
#define PIN_POWER_STATE_3V3 3300
/**
* struct cv1800_vddio_cfg_ops - pin vddio operations
*
* @get_pull_up: get resistor for pull up;
* @get_pull_down: get resistor for pull down.
* @get_oc_map: get mapping for typical low level output current value to
* register value map.
* @get_schmitt_map: get mapping for register value to typical schmitt
* threshold.
*/
struct cv1800_vddio_cfg_ops {
int (*get_pull_up)(struct cv1800_pin *pin, const u32 *psmap);
int (*get_pull_down)(struct cv1800_pin *pin, const u32 *psmap);
int (*get_oc_map)(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map);
int (*get_schmitt_map)(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map);
};
struct cv1800_pinctrl_data {
const struct pinctrl_pin_desc *pins;
const struct cv1800_pin *pindata;
const char * const *pdnames;
const struct cv1800_vddio_cfg_ops *vddio_ops;
u16 npins;
u16 npd;
};
static inline enum cv1800_pin_io_type cv1800_pin_io_type(struct cv1800_pin *pin)
{
return FIELD_GET(CV1800_PIN_IO_TYPE, pin->flags);
};
int cv1800_pinctrl_probe(struct platform_device *pdev);
#define CV1800_FUNC_PIN(_id, _power_domain, _type, \
_mux_area, _mux_offset, _mux_func_max) \
{ \
.pin = (_id), \
.power_domain = (_power_domain), \
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
.mux = { \
.area = (_mux_area), \
.offset = (_mux_offset), \
.max = (_mux_func_max), \
}, \
}
#define CV1800_GENERAL_PIN(_id, _power_domain, _type, \
_mux_area, _mux_offset, _mux_func_max, \
_conf_area, _conf_offset) \
{ \
.pin = (_id), \
.power_domain = (_power_domain), \
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
.mux = { \
.area = (_mux_area), \
.offset = (_mux_offset), \
.max = (_mux_func_max), \
}, \
.conf = { \
.area = (_conf_area), \
.offset = (_conf_offset), \
}, \
}
#define CV1800_GENERATE_PIN_MUX2(_id, _power_domain, _type, \
_mux_area, _mux_offset, _mux_func_max, \
_mux2_area, _mux2_offset, \
_mux2_func_max, \
_conf_area, _conf_offset) \
{ \
.pin = (_id), \
.power_domain = (_power_domain), \
.flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \
CV1800_PIN_HAVE_MUX2, \
.mux = { \
.area = (_mux_area), \
.offset = (_mux_offset), \
.max = (_mux_func_max), \
}, \
.mux2 = { \
.area = (_mux2_area), \
.offset = (_mux2_offset), \
.max = (_mux2_func_max), \
}, \
.conf = { \
.area = (_conf_area), \
.offset = (_conf_offset), \
}, \
}
#endif

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// SPDX-License-Identifier: GPL-2.0
/*
* Sophgo SG2000 SoC pinctrl driver.
*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
#include "pinctrl-cv18xx.h"
enum SG2000_POWER_DOMAIN {
VDD18A_EPHY = 0,
VDD18A_MIPI = 1,
VDDIO18_1 = 2,
VDDIO_EMMC = 3,
VDDIO_RTC = 4,
VDDIO_SD0 = 5,
VDDIO_SD1 = 6,
VDDIO_VIVO = 7
};
static const char *const sg2000_power_domain_desc[] = {
[VDD18A_EPHY] = "VDD18A_EPHY",
[VDD18A_MIPI] = "VDD18A_MIPI",
[VDDIO18_1] = "VDDIO18_1",
[VDDIO_EMMC] = "VDDIO_EMMC",
[VDDIO_RTC] = "VDDIO_RTC",
[VDDIO_SD0] = "VDDIO_SD0",
[VDDIO_SD1] = "VDDIO_SD1",
[VDDIO_VIVO] = "VDDIO_VIVO",
};
static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 79000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 60000;
if (pstate == PIN_POWER_STATE_3V3)
return 60000;
return -EINVAL;
}
return -ENOTSUPP;
}
static int sg2000_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 87000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 61000;
if (pstate == PIN_POWER_STATE_3V3)
return 62000;
return -EINVAL;
}
return -ENOTSUPP;
}
static const u32 sg2000_1v8_oc_map[] = {
12800,
25300,
37400,
49000
};
static const u32 sg2000_18od33_1v8_oc_map[] = {
7800,
11700,
15500,
19200,
23000,
26600,
30200,
33700
};
static const u32 sg2000_18od33_3v3_oc_map[] = {
5500,
8200,
10800,
13400,
16100,
18700,
21200,
23700
};
static const u32 sg2000_eth_oc_map[] = {
15700,
17800
};
static int sg2000_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = sg2000_1v8_oc_map;
return ARRAY_SIZE(sg2000_1v8_oc_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = sg2000_18od33_1v8_oc_map;
return ARRAY_SIZE(sg2000_18od33_1v8_oc_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = sg2000_18od33_3v3_oc_map;
return ARRAY_SIZE(sg2000_18od33_3v3_oc_map);
}
}
if (type == IO_TYPE_ETH) {
*map = sg2000_eth_oc_map;
return ARRAY_SIZE(sg2000_eth_oc_map);
}
return -ENOTSUPP;
}
static const u32 sg2000_1v8_schmitt_map[] = {
0,
970000,
1040000
};
static const u32 sg2000_18od33_1v8_schmitt_map[] = {
0,
1070000
};
static const u32 sg2000_18od33_3v3_schmitt_map[] = {
0,
1100000
};
static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = sg2000_1v8_schmitt_map;
return ARRAY_SIZE(sg2000_1v8_schmitt_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = sg2000_18od33_1v8_schmitt_map;
return ARRAY_SIZE(sg2000_18od33_1v8_schmitt_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = sg2000_18od33_3v3_schmitt_map;
return ARRAY_SIZE(sg2000_18od33_3v3_schmitt_map);
}
}
return -ENOTSUPP;
}
static const struct cv1800_vddio_cfg_ops sg2000_vddio_cfg_ops = {
.get_pull_up = sg2000_get_pull_up,
.get_pull_down = sg2000_get_pull_down,
.get_oc_map = sg2000_get_oc_map,
.get_schmitt_map = sg2000_get_schmitt_map,
};
static const struct pinctrl_pin_desc sg2000_pins[] = {
PINCTRL_PIN(PIN_MIPI_TXM4, "MIPI_TXM4"),
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
PINCTRL_PIN(PIN_VIVO_D2, "VIVO_D2"),
PINCTRL_PIN(PIN_VIVO_D3, "VIVO_D3"),
PINCTRL_PIN(PIN_VIVO_D10, "VIVO_D10"),
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
PINCTRL_PIN(PIN_MIPI_TXP3, "MIPI_TXP3"),
PINCTRL_PIN(PIN_MIPI_TXM3, "MIPI_TXM3"),
PINCTRL_PIN(PIN_MIPI_TXP4, "MIPI_TXP4"),
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
PINCTRL_PIN(PIN_MIPIRX5N, "MIPIRX5N"),
PINCTRL_PIN(PIN_VIVO_D1, "VIVO_D1"),
PINCTRL_PIN(PIN_VIVO_D5, "VIVO_D5"),
PINCTRL_PIN(PIN_VIVO_D7, "VIVO_D7"),
PINCTRL_PIN(PIN_VIVO_D9, "VIVO_D9"),
PINCTRL_PIN(PIN_USB_ID, "USB_ID"),
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
PINCTRL_PIN(PIN_CAM_PD0, "CAM_PD0"),
PINCTRL_PIN(PIN_CAM_MCLK0, "CAM_MCLK0"),
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
PINCTRL_PIN(PIN_MIPIRX5P, "MIPIRX5P"),
PINCTRL_PIN(PIN_VIVO_CLK, "VIVO_CLK"),
PINCTRL_PIN(PIN_VIVO_D6, "VIVO_D6"),
PINCTRL_PIN(PIN_VIVO_D8, "VIVO_D8"),
PINCTRL_PIN(PIN_USB_VBUS_EN, "USB_VBUS_EN"),
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
PINCTRL_PIN(PIN_CAM_MCLK1, "CAM_MCLK1"),
PINCTRL_PIN(PIN_IIC3_SCL, "IIC3_SCL"),
PINCTRL_PIN(PIN_VIVO_D4, "VIVO_D4"),
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
PINCTRL_PIN(PIN_CAM_PD1, "CAM_PD1"),
PINCTRL_PIN(PIN_CAM_RST0, "CAM_RST0"),
PINCTRL_PIN(PIN_VIVO_D0, "VIVO_D0"),
PINCTRL_PIN(PIN_ADC1, "ADC1"),
PINCTRL_PIN(PIN_ADC2, "ADC2"),
PINCTRL_PIN(PIN_ADC3, "ADC3"),
PINCTRL_PIN(PIN_AUD_AOUTL, "AUD_AOUTL"),
PINCTRL_PIN(PIN_IIC3_SDA, "IIC3_SDA"),
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
PINCTRL_PIN(PIN_RSTN, "RSTN"),
PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
PINCTRL_PIN(PIN_AUD_AINR_MIC, "AUD_AINR_MIC"),
PINCTRL_PIN(PIN_IIC2_SCL, "IIC2_SCL"),
PINCTRL_PIN(PIN_IIC2_SDA, "IIC2_SDA"),
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
PINCTRL_PIN(PIN_UART2_RX, "UART2_RX"),
PINCTRL_PIN(PIN_UART2_CTS, "UART2_CTS"),
PINCTRL_PIN(PIN_UART2_TX, "UART2_TX"),
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
PINCTRL_PIN(PIN_CLK32K, "CLK32K"),
PINCTRL_PIN(PIN_UART2_RTS, "UART2_RTS"),
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
PINCTRL_PIN(PIN_JTAG_CPU_TRST, "JTAG_CPU_TRST"),
PINCTRL_PIN(PIN_PWR_ON, "PWR_ON"),
PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
PINCTRL_PIN(PIN_CLK25M, "CLK25M"),
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
PINCTRL_PIN(PIN_PWR_WAKEUP1, "PWR_WAKEUP1"),
PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
PINCTRL_PIN(PIN_EMMC_RSTN, "EMMC_RSTN"),
PINCTRL_PIN(PIN_AUX0, "AUX0"),
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
PINCTRL_PIN(PIN_PWR_SEQ3, "PWR_SEQ3"),
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
};
static const struct cv1800_pin sg2000_pin_data[ARRAY_SIZE(sg2000_pins)] = {
CV1800_GENERAL_PIN(PIN_MIPI_TXM4, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x194, 7,
CV1800_PINCONF_AREA_SYS, 0xc60),
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x18c, 7,
CV1800_PINCONF_AREA_SYS, 0xc58),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x178, 7,
CV1800_PINCONF_AREA_SYS, 0x118, 7,
CV1800_PINCONF_AREA_SYS, 0xc44),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x170, 7,
CV1800_PINCONF_AREA_SYS, 0x11c, 7,
CV1800_PINCONF_AREA_SYS, 0xc3c),
CV1800_GENERAL_PIN(PIN_VIVO_D2, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x154, 7,
CV1800_PINCONF_AREA_SYS, 0xc20),
CV1800_GENERAL_PIN(PIN_VIVO_D3, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x150, 7,
CV1800_PINCONF_AREA_SYS, 0xc1c),
CV1800_GENERAL_PIN(PIN_VIVO_D10, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x134, 7,
CV1800_PINCONF_AREA_SYS, 0xc00),
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x108, 5,
CV1800_PINCONF_AREA_SYS, 0x820),
CV1800_GENERAL_PIN(PIN_MIPI_TXP3, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a0, 7,
CV1800_PINCONF_AREA_SYS, 0xc6c),
CV1800_GENERAL_PIN(PIN_MIPI_TXM3, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x19c, 7,
CV1800_PINCONF_AREA_SYS, 0xc68),
CV1800_GENERAL_PIN(PIN_MIPI_TXP4, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x198, 7,
CV1800_PINCONF_AREA_SYS, 0xc64),
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x190, 7,
CV1800_PINCONF_AREA_SYS, 0xc5c),
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x184, 7,
CV1800_PINCONF_AREA_SYS, 0xc50),
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x17c, 7,
CV1800_PINCONF_AREA_SYS, 0xc48),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x16c, 7,
CV1800_PINCONF_AREA_SYS, 0x120, 7,
CV1800_PINCONF_AREA_SYS, 0xc38),
CV1800_GENERAL_PIN(PIN_MIPIRX5N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x164, 7,
CV1800_PINCONF_AREA_SYS, 0xc30),
CV1800_GENERAL_PIN(PIN_VIVO_D1, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x158, 7,
CV1800_PINCONF_AREA_SYS, 0xc24),
CV1800_GENERAL_PIN(PIN_VIVO_D5, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x148, 7,
CV1800_PINCONF_AREA_SYS, 0xc14),
CV1800_GENERAL_PIN(PIN_VIVO_D7, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x140, 7,
CV1800_PINCONF_AREA_SYS, 0xc0c),
CV1800_GENERAL_PIN(PIN_VIVO_D9, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x138, 7,
CV1800_PINCONF_AREA_SYS, 0xc04),
CV1800_GENERAL_PIN(PIN_USB_ID, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0fc, 3,
CV1800_PINCONF_AREA_SYS, 0x814),
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x130, 7),
CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
CV1800_PINCONF_AREA_SYS, 0xc74),
CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
CV1800_PINCONF_AREA_SYS, 0xc70),
CV1800_GENERAL_PIN(PIN_CAM_PD0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x004, 4,
CV1800_PINCONF_AREA_SYS, 0xb04),
CV1800_GENERAL_PIN(PIN_CAM_MCLK0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x000, 3,
CV1800_PINCONF_AREA_SYS, 0xb00),
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x188, 7,
CV1800_PINCONF_AREA_SYS, 0xc54),
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x180, 7,
CV1800_PINCONF_AREA_SYS, 0xc4c),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x174, 7,
CV1800_PINCONF_AREA_SYS, 0x114, 7,
CV1800_PINCONF_AREA_SYS, 0xc40),
CV1800_GENERAL_PIN(PIN_MIPIRX5P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x168, 7,
CV1800_PINCONF_AREA_SYS, 0xc34),
CV1800_GENERAL_PIN(PIN_VIVO_CLK, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x160, 7,
CV1800_PINCONF_AREA_SYS, 0xc2c),
CV1800_GENERAL_PIN(PIN_VIVO_D6, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x144, 7,
CV1800_PINCONF_AREA_SYS, 0xc10),
CV1800_GENERAL_PIN(PIN_VIVO_D8, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x13c, 7,
CV1800_PINCONF_AREA_SYS, 0xc08),
CV1800_GENERAL_PIN(PIN_USB_VBUS_EN, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x100, 3,
CV1800_PINCONF_AREA_SYS, 0x818),
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x12c, 7),
CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
CV1800_PINCONF_AREA_SYS, 0xc8c),
CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
CV1800_PINCONF_AREA_SYS, 0xc7c),
CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
CV1800_PINCONF_AREA_SYS, 0xc78),
CV1800_GENERAL_PIN(PIN_CAM_MCLK1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x00c, 4,
CV1800_PINCONF_AREA_SYS, 0xb0c),
CV1800_GENERAL_PIN(PIN_IIC3_SCL, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x014, 3,
CV1800_PINCONF_AREA_SYS, 0xb14),
CV1800_GENERAL_PIN(PIN_VIVO_D4, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x14c, 7,
CV1800_PINCONF_AREA_SYS, 0xc18),
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x128, 7),
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_EPHY,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x124, 7),
CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
CV1800_PINCONF_AREA_SYS, 0xc84),
CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
CV1800_PINCONF_AREA_SYS, 0xc80),
CV1800_GENERAL_PIN(PIN_CAM_PD1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x010, 6,
CV1800_PINCONF_AREA_SYS, 0xb10),
CV1800_GENERAL_PIN(PIN_CAM_RST0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x008, 6,
CV1800_PINCONF_AREA_SYS, 0xb08),
CV1800_GENERAL_PIN(PIN_VIVO_D0, VDDIO_VIVO,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x15c, 7,
CV1800_PINCONF_AREA_SYS, 0xc28),
CV1800_GENERAL_PIN(PIN_ADC1, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
CV1800_PINCONF_AREA_SYS, 0x810),
CV1800_GENERAL_PIN(PIN_ADC2, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f4, 7,
CV1800_PINCONF_AREA_SYS, 0x80c),
CV1800_GENERAL_PIN(PIN_ADC3, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f0, 7,
CV1800_PINCONF_AREA_SYS, 0x808),
CV1800_FUNC_PIN(PIN_AUD_AOUTL, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c4, 5),
CV1800_GENERAL_PIN(PIN_IIC3_SDA, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x018, 3,
CV1800_PINCONF_AREA_SYS, 0xb18),
CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
CV1800_PINCONF_AREA_RTC, 0x05c),
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
CV1800_PINCONF_AREA_RTC, 0x058),
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
CV1800_PINCONF_AREA_RTC, 0x06c),
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
CV1800_PINCONF_AREA_RTC, 0x068),
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
CV1800_GENERAL_PIN(PIN_RSTN, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0e8, 0,
CV1800_PINCONF_AREA_SYS, 0x800),
CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDDIO18_1,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
CV1800_PINCONF_AREA_SYS, 0x804),
CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
CV1800_PINCONF_AREA_RTC, 0x060),
CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
CV1800_PINCONF_AREA_RTC, 0x064),
CV1800_FUNC_PIN(PIN_AUD_AINR_MIC, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c0, 6),
CV1800_GENERAL_PIN(PIN_IIC2_SCL, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0b8, 7,
CV1800_PINCONF_AREA_RTC, 0x040),
CV1800_GENERAL_PIN(PIN_IIC2_SDA, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0bc, 7,
CV1800_PINCONF_AREA_RTC, 0x044),
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x034, 3,
CV1800_PINCONF_AREA_SYS, 0x900),
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x028, 7,
CV1800_PINCONF_AREA_SYS, 0xa0c),
CV1800_GENERAL_PIN(PIN_UART2_RX, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0c8, 7,
CV1800_PINCONF_AREA_RTC, 0x050),
CV1800_GENERAL_PIN(PIN_UART2_CTS, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0cc, 7,
CV1800_PINCONF_AREA_RTC, 0x054),
CV1800_GENERAL_PIN(PIN_UART2_TX, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0c0, 7,
CV1800_PINCONF_AREA_RTC, 0x048),
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x01c, 7,
CV1800_PINCONF_AREA_SYS, 0xa00),
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x024, 7,
CV1800_PINCONF_AREA_SYS, 0xa08),
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x020, 7,
CV1800_PINCONF_AREA_SYS, 0xa04),
CV1800_GENERAL_PIN(PIN_CLK32K, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0b0, 7,
CV1800_PINCONF_AREA_RTC, 0x038),
CV1800_GENERAL_PIN(PIN_UART2_RTS, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0c4, 7,
CV1800_PINCONF_AREA_RTC, 0x04c),
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x030, 7,
CV1800_PINCONF_AREA_SYS, 0xa14),
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x02c, 7,
CV1800_PINCONF_AREA_SYS, 0xa10),
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x044, 7,
CV1800_PINCONF_AREA_SYS, 0x910),
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x040, 7,
CV1800_PINCONF_AREA_SYS, 0x90c),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TRST, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x06c, 6,
CV1800_PINCONF_AREA_SYS, 0x938),
CV1800_GENERAL_PIN(PIN_PWR_ON, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x09c, 7,
CV1800_PINCONF_AREA_RTC, 0x024),
CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
CV1800_PINCONF_AREA_RTC, 0x034),
CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
CV1800_PINCONF_AREA_RTC, 0x02c),
CV1800_GENERAL_PIN(PIN_CLK25M, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0b4, 7,
CV1800_PINCONF_AREA_RTC, 0x03c),
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x038, 3,
CV1800_PINCONF_AREA_SYS, 0x904),
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
CV1800_PINCONF_AREA_SYS, 0x908),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x068, 7,
CV1800_PINCONF_AREA_SYS, 0x934),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x064, 7,
CV1800_PINCONF_AREA_SYS, 0x930),
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x094, 7,
CV1800_PINCONF_AREA_RTC, 0x01c),
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x090, 7,
CV1800_PINCONF_AREA_RTC, 0x018),
CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
CV1800_PINCONF_AREA_RTC, 0x030),
CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x058, 3,
CV1800_PINCONF_AREA_SYS, 0x924),
CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x054, 3,
CV1800_PINCONF_AREA_SYS, 0x920),
CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x04c, 3,
CV1800_PINCONF_AREA_SYS, 0x918),
CV1800_GENERAL_PIN(PIN_EMMC_RSTN, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x048, 4,
CV1800_PINCONF_AREA_SYS, 0x914),
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x078, 7,
CV1800_PINCONF_AREA_SYS, 0x944),
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x074, 7,
CV1800_PINCONF_AREA_SYS, 0x940),
CV1800_GENERAL_PIN(PIN_PWR_SEQ3, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x08c, 3,
CV1800_PINCONF_AREA_RTC, 0x010),
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x07c, 0,
CV1800_PINCONF_AREA_RTC, 0x000),
CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x084, 3,
CV1800_PINCONF_AREA_RTC, 0x008),
CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x098, 7,
CV1800_PINCONF_AREA_RTC, 0x020),
CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x060, 3,
CV1800_PINCONF_AREA_SYS, 0x92c),
CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x05c, 3,
CV1800_PINCONF_AREA_SYS, 0x928),
CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x050, 3,
CV1800_PINCONF_AREA_SYS, 0x91c),
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x070, 7,
CV1800_PINCONF_AREA_SYS, 0x93c),
CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
CV1800_PINCONF_AREA_RTC, 0x0e0),
CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x080, 0,
CV1800_PINCONF_AREA_RTC, 0x004),
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x088, 3,
CV1800_PINCONF_AREA_RTC, 0x00c),
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
CV1800_PINCONF_AREA_RTC, 0x028),
};
static const struct cv1800_pinctrl_data sg2000_pindata = {
.pins = sg2000_pins,
.pindata = sg2000_pin_data,
.pdnames = sg2000_power_domain_desc,
.vddio_ops = &sg2000_vddio_cfg_ops,
.npins = ARRAY_SIZE(sg2000_pins),
.npd = ARRAY_SIZE(sg2000_power_domain_desc),
};
static const struct of_device_id sg2000_pinctrl_ids[] = {
{ .compatible = "sophgo,sg2000-pinctrl", .data = &sg2000_pindata },
{ }
};
MODULE_DEVICE_TABLE(of, sg2000_pinctrl_ids);
static struct platform_driver sg2000_pinctrl_driver = {
.probe = cv1800_pinctrl_probe,
.driver = {
.name = "sg2000-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = sg2000_pinctrl_ids,
},
};
module_platform_driver(sg2000_pinctrl_driver);
MODULE_DESCRIPTION("Pinctrl driver for the SG2000 series SoC");
MODULE_LICENSE("GPL");

542
drivers/pinctrl/sophgo/pinctrl-sg2002.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Sophgo SG2002 SoC pinctrl driver.
*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
#include "pinctrl-cv18xx.h"
enum SG2002_POWER_DOMAIN {
VDD18A_MIPI = 0,
VDD18A_USB_PLL_ETH = 1,
VDDIO_RTC = 2,
VDDIO_SD0_EMMC = 3,
VDDIO_SD1 = 4
};
static const char *const sg2002_power_domain_desc[] = {
[VDD18A_MIPI] = "VDD18A_MIPI",
[VDD18A_USB_PLL_ETH] = "VDD18A_USB_PLL_ETH",
[VDDIO_RTC] = "VDDIO_RTC",
[VDDIO_SD0_EMMC] = "VDDIO_SD0_EMMC",
[VDDIO_SD1] = "VDDIO_SD1",
};
static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 79000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 60000;
if (pstate == PIN_POWER_STATE_3V3)
return 60000;
return -EINVAL;
}
return -ENOTSUPP;
}
static int sg2002_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
{
u32 pstate = psmap[pin->power_domain];
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
if (type == IO_TYPE_1V8_ONLY)
return 87000;
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8)
return 61000;
if (pstate == PIN_POWER_STATE_3V3)
return 62000;
return -EINVAL;
}
return -ENOTSUPP;
}
static const u32 sg2002_1v8_oc_map[] = {
12800,
25300,
37400,
49000
};
static const u32 sg2002_18od33_1v8_oc_map[] = {
7800,
11700,
15500,
19200,
23000,
26600,
30200,
33700
};
static const u32 sg2002_18od33_3v3_oc_map[] = {
5500,
8200,
10800,
13400,
16100,
18700,
21200,
23700
};
static const u32 sg2002_eth_oc_map[] = {
15700,
17800
};
static int sg2002_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = sg2002_1v8_oc_map;
return ARRAY_SIZE(sg2002_1v8_oc_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = sg2002_18od33_1v8_oc_map;
return ARRAY_SIZE(sg2002_18od33_1v8_oc_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = sg2002_18od33_3v3_oc_map;
return ARRAY_SIZE(sg2002_18od33_3v3_oc_map);
}
}
if (type == IO_TYPE_ETH) {
*map = sg2002_eth_oc_map;
return ARRAY_SIZE(sg2002_eth_oc_map);
}
return -ENOTSUPP;
}
static const u32 sg2002_1v8_schmitt_map[] = {
0,
970000,
1040000
};
static const u32 sg2002_18od33_1v8_schmitt_map[] = {
0,
1070000
};
static const u32 sg2002_18od33_3v3_schmitt_map[] = {
0,
1100000
};
static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
const u32 **map)
{
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
u32 pstate = psmap[pin->power_domain];
if (type == IO_TYPE_1V8_ONLY) {
*map = sg2002_1v8_schmitt_map;
return ARRAY_SIZE(sg2002_1v8_schmitt_map);
}
if (type == IO_TYPE_1V8_OR_3V3) {
if (pstate == PIN_POWER_STATE_1V8) {
*map = sg2002_18od33_1v8_schmitt_map;
return ARRAY_SIZE(sg2002_18od33_1v8_schmitt_map);
} else if (pstate == PIN_POWER_STATE_3V3) {
*map = sg2002_18od33_3v3_schmitt_map;
return ARRAY_SIZE(sg2002_18od33_3v3_schmitt_map);
}
}
return -ENOTSUPP;
}
static const struct cv1800_vddio_cfg_ops sg2002_vddio_cfg_ops = {
.get_pull_up = sg2002_get_pull_up,
.get_pull_down = sg2002_get_pull_down,
.get_oc_map = sg2002_get_oc_map,
.get_schmitt_map = sg2002_get_schmitt_map,
};
static const struct pinctrl_pin_desc sg2002_pins[] = {
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
PINCTRL_PIN(PIN_AUX0, "AUX0"),
PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
PINCTRL_PIN(PIN_ADC1, "ADC1"),
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
};
static const struct cv1800_pin sg2002_pin_data[ARRAY_SIZE(sg2002_pins)] = {
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
IO_TYPE_AUDIO,
CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x01c, 7,
CV1800_PINCONF_AREA_SYS, 0xa00),
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x020, 7,
CV1800_PINCONF_AREA_SYS, 0xa04),
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x024, 7,
CV1800_PINCONF_AREA_SYS, 0xa08),
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x028, 7,
CV1800_PINCONF_AREA_SYS, 0xa0c),
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x02c, 7,
CV1800_PINCONF_AREA_SYS, 0xa10),
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x030, 7,
CV1800_PINCONF_AREA_SYS, 0xa14),
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x034, 3,
CV1800_PINCONF_AREA_SYS, 0x900),
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x038, 3,
CV1800_PINCONF_AREA_SYS, 0x904),
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
CV1800_PINCONF_AREA_SYS, 0x908),
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x040, 7,
CV1800_PINCONF_AREA_SYS, 0x90c),
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x044, 7,
CV1800_PINCONF_AREA_SYS, 0x910),
CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x04c, 3,
CV1800_PINCONF_AREA_SYS, 0x918),
CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x050, 3,
CV1800_PINCONF_AREA_SYS, 0x91c),
CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x054, 3,
CV1800_PINCONF_AREA_SYS, 0x920),
CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x058, 3,
CV1800_PINCONF_AREA_SYS, 0x924),
CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x05c, 3,
CV1800_PINCONF_AREA_SYS, 0x928),
CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x060, 3,
CV1800_PINCONF_AREA_SYS, 0x92c),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x064, 7,
CV1800_PINCONF_AREA_SYS, 0x930),
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x068, 7,
CV1800_PINCONF_AREA_SYS, 0x934),
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x070, 7,
CV1800_PINCONF_AREA_SYS, 0x93c),
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x074, 7,
CV1800_PINCONF_AREA_SYS, 0x940),
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_EMMC,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x078, 7,
CV1800_PINCONF_AREA_SYS, 0x944),
CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
CV1800_PINCONF_AREA_RTC, 0x0e0),
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x07c, 0,
CV1800_PINCONF_AREA_RTC, 0x000),
CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x080, 0,
CV1800_PINCONF_AREA_RTC, 0x004),
CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x084, 3,
CV1800_PINCONF_AREA_RTC, 0x008),
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x088, 3,
CV1800_PINCONF_AREA_RTC, 0x00c),
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x090, 7,
CV1800_PINCONF_AREA_RTC, 0x018),
CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x098, 7,
CV1800_PINCONF_AREA_RTC, 0x020),
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
CV1800_PINCONF_AREA_RTC, 0x028),
CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
CV1800_PINCONF_AREA_RTC, 0x02c),
CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
CV1800_PINCONF_AREA_RTC, 0x030),
CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
CV1800_PINCONF_AREA_RTC, 0x034),
CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
CV1800_PINCONF_AREA_RTC, 0x058),
CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
CV1800_PINCONF_AREA_RTC, 0x05c),
CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
CV1800_PINCONF_AREA_RTC, 0x060),
CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
CV1800_PINCONF_AREA_RTC, 0x064),
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
CV1800_PINCONF_AREA_RTC, 0x068),
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
IO_TYPE_1V8_OR_3V3,
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
CV1800_PINCONF_AREA_RTC, 0x06c),
CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDD18A_USB_PLL_ETH,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
CV1800_PINCONF_AREA_SYS, 0x804),
CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
CV1800_PINCONF_AREA_SYS, 0x810),
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x108, 5,
CV1800_PINCONF_AREA_SYS, 0x820),
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x124, 7),
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x128, 7),
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x12c, 7),
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH,
IO_TYPE_ETH,
CV1800_PINCONF_AREA_SYS, 0x130, 7),
CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDD18A_USB_PLL_ETH,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
CV1800_PINCONF_AREA_SYS, 0xc8c),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x16c, 7,
CV1800_PINCONF_AREA_SYS, 0x120, 7,
CV1800_PINCONF_AREA_SYS, 0xc38),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x170, 7,
CV1800_PINCONF_AREA_SYS, 0x11c, 7,
CV1800_PINCONF_AREA_SYS, 0xc3c),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x174, 7,
CV1800_PINCONF_AREA_SYS, 0x114, 7,
CV1800_PINCONF_AREA_SYS, 0xc40),
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x178, 7,
CV1800_PINCONF_AREA_SYS, 0x118, 7,
CV1800_PINCONF_AREA_SYS, 0xc44),
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x17c, 7,
CV1800_PINCONF_AREA_SYS, 0xc48),
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x180, 7,
CV1800_PINCONF_AREA_SYS, 0xc4c),
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x184, 7,
CV1800_PINCONF_AREA_SYS, 0xc50),
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x188, 7,
CV1800_PINCONF_AREA_SYS, 0xc54),
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x18c, 7,
CV1800_PINCONF_AREA_SYS, 0xc58),
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x190, 7,
CV1800_PINCONF_AREA_SYS, 0xc5c),
CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
CV1800_PINCONF_AREA_SYS, 0xc70),
CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
CV1800_PINCONF_AREA_SYS, 0xc74),
CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
CV1800_PINCONF_AREA_SYS, 0xc78),
CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
CV1800_PINCONF_AREA_SYS, 0xc7c),
CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
CV1800_PINCONF_AREA_SYS, 0xc80),
CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
IO_TYPE_1V8_ONLY,
CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
CV1800_PINCONF_AREA_SYS, 0xc84),
};
static const struct cv1800_pinctrl_data sg2002_pindata = {
.pins = sg2002_pins,
.pindata = sg2002_pin_data,
.pdnames = sg2002_power_domain_desc,
.vddio_ops = &sg2002_vddio_cfg_ops,
.npins = ARRAY_SIZE(sg2002_pins),
.npd = ARRAY_SIZE(sg2002_power_domain_desc),
};
static const struct of_device_id sg2002_pinctrl_ids[] = {
{ .compatible = "sophgo,sg2002-pinctrl", .data = &sg2002_pindata },
{ }
};
MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids);
static struct platform_driver sg2002_pinctrl_driver = {
.probe = cv1800_pinctrl_probe,
.driver = {
.name = "sg2002-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = sg2002_pinctrl_ids,
},
};
module_platform_driver(sg2002_pinctrl_driver);
MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
MODULE_LICENSE("GPL");

14
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -1603,30 +1603,26 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
}
ret = of_clk_get_parent_count(node);
clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
clk = devm_clk_get_enabled(&pdev->dev, ret == 1 ? NULL : "apb");
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto gpiochip_error;
}
ret = clk_prepare_enable(clk);
if (ret)
goto gpiochip_error;
pctl->irq = devm_kcalloc(&pdev->dev,
pctl->desc->irq_banks,
sizeof(*pctl->irq),
GFP_KERNEL);
if (!pctl->irq) {
ret = -ENOMEM;
goto clk_error;
goto gpiochip_error;
}
for (i = 0; i < pctl->desc->irq_banks; i++) {
pctl->irq[i] = platform_get_irq(pdev, i);
if (pctl->irq[i] < 0) {
ret = pctl->irq[i];
goto clk_error;
goto gpiochip_error;
}
}
@ -1637,7 +1633,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
if (!pctl->domain) {
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
ret = -ENOMEM;
goto clk_error;
goto gpiochip_error;
}
for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
@ -1669,8 +1665,6 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
return 0;
clk_error:
clk_disable_unprepare(clk);
gpiochip_error:
gpiochip_remove(pctl->chip);
return ret;

58
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
View File

@ -82,7 +82,7 @@ struct ti_iodelay_reg_data {
u32 reg_start_offset;
u32 reg_nr_per_pin;
struct regmap_config *regmap_config;
const struct regmap_config *regmap_config;
};
/**
@ -273,6 +273,22 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod,
return r;
}
/**
* ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
* @data: IODelay device
*
* Deinitialize the IODelay device (basically just lock the region back up.
*/
static void ti_iodelay_pinconf_deinit_dev(void *data)
{
struct ti_iodelay_device *iod = data;
const struct ti_iodelay_reg_data *reg = iod->reg_data;
/* lock the iodelay region back again */
regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
reg->global_lock_mask, reg->global_lock_val);
}
/**
* ti_iodelay_pinconf_init_dev() - Initialize IODelay device
* @iod: iodelay device
@ -295,6 +311,11 @@ static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod)
if (r)
return r;
r = devm_add_action_or_reset(iod->dev, ti_iodelay_pinconf_deinit_dev,
iod);
if (r)
return r;
/* Read up Recalibration sequence done by bootloader */
r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val);
if (r)
@ -353,21 +374,6 @@ static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod)
return 0;
}
/**
* ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
* @iod: IODelay device
*
* Deinitialize the IODelay device (basically just lock the region back up.
*/
static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod)
{
const struct ti_iodelay_reg_data *reg = iod->reg_data;
/* lock the iodelay region back again */
regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
reg->global_lock_mask, reg->global_lock_val);
}
/**
* ti_iodelay_get_pingroup() - Find the group mapped by a group selector
* @iod: iodelay device
@ -770,14 +776,14 @@ static int ti_iodelay_alloc_pins(struct device *dev,
return 0;
}
static struct regmap_config dra7_iodelay_regmap_config = {
static const struct regmap_config dra7_iodelay_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xd1c,
};
static struct ti_iodelay_reg_data dra7_iodelay_data = {
static const struct ti_iodelay_reg_data dra7_iodelay_data = {
.signature_mask = 0x0003f000,
.signature_value = 0x29,
.lock_mask = 0x00000400,
@ -877,27 +883,11 @@ static int ti_iodelay_probe(struct platform_device *pdev)
return ret;
}
platform_set_drvdata(pdev, iod);
return pinctrl_enable(iod->pctl);
}
/**
* ti_iodelay_remove() - standard remove
* @pdev: platform device
*/
static void ti_iodelay_remove(struct platform_device *pdev)
{
struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
ti_iodelay_pinconf_deinit_dev(iod);
/* Expect other allocations to be freed by devm */
}
static struct platform_driver ti_iodelay_driver = {
.probe = ti_iodelay_probe,
.remove_new = ti_iodelay_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = ti_iodelay_of_match,

63
include/dt-bindings/pinctrl/pinctrl-cv1800b.h Normal file
View File

@ -0,0 +1,63 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#ifndef _DT_BINDINGS_PINCTRL_CV1800B_H
#define _DT_BINDINGS_PINCTRL_CV1800B_H
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
#define PIN_AUD_AOUTR 1
#define PIN_SD0_CLK 3
#define PIN_SD0_CMD 4
#define PIN_SD0_D0 5
#define PIN_SD0_D1 7
#define PIN_SD0_D2 8
#define PIN_SD0_D3 9
#define PIN_SD0_CD 11
#define PIN_SD0_PWR_EN 12
#define PIN_SPK_EN 14
#define PIN_UART0_TX 15
#define PIN_UART0_RX 16
#define PIN_SPINOR_HOLD_X 17
#define PIN_SPINOR_SCK 18
#define PIN_SPINOR_MOSI 19
#define PIN_SPINOR_WP_X 20
#define PIN_SPINOR_MISO 21
#define PIN_SPINOR_CS_X 22
#define PIN_IIC0_SCL 23
#define PIN_IIC0_SDA 24
#define PIN_AUX0 25
#define PIN_PWR_VBAT_DET 30
#define PIN_PWR_SEQ2 31
#define PIN_XTAL_XIN 33
#define PIN_SD1_GPIO0 35
#define PIN_SD1_GPIO1 36
#define PIN_SD1_D3 38
#define PIN_SD1_D2 39
#define PIN_SD1_D1 40
#define PIN_SD1_D0 41
#define PIN_SD1_CMD 42
#define PIN_SD1_CLK 43
#define PIN_ADC1 44
#define PIN_USB_VBUS_DET 45
#define PIN_ETH_TXP 47
#define PIN_ETH_TXM 48
#define PIN_ETH_RXP 49
#define PIN_ETH_RXM 50
#define PIN_MIPIRX4N 56
#define PIN_MIPIRX4P 57
#define PIN_MIPIRX3N 58
#define PIN_MIPIRX3P 59
#define PIN_MIPIRX2N 60
#define PIN_MIPIRX2P 61
#define PIN_MIPIRX1N 62
#define PIN_MIPIRX1P 63
#define PIN_MIPIRX0N 64
#define PIN_MIPIRX0P 65
#define PIN_AUD_AINL_MIC 67
#endif /* _DT_BINDINGS_PINCTRL_CV1800B_H */

127
include/dt-bindings/pinctrl/pinctrl-cv1812h.h Normal file
View File

@ -0,0 +1,127 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#ifndef _DT_BINDINGS_PINCTRL_CV1812H_H
#define _DT_BINDINGS_PINCTRL_CV1812H_H
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
#define PINPOS(row, col) \
((((row) - 'A' + 1) << 8) + ((col) - 1))
#define PIN_MIPI_TXM4 PINPOS('A', 2)
#define PIN_MIPIRX0N PINPOS('A', 4)
#define PIN_MIPIRX3P PINPOS('A', 6)
#define PIN_MIPIRX4P PINPOS('A', 7)
#define PIN_VIVO_D2 PINPOS('A', 9)
#define PIN_VIVO_D3 PINPOS('A', 10)
#define PIN_VIVO_D10 PINPOS('A', 12)
#define PIN_USB_VBUS_DET PINPOS('A', 13)
#define PIN_MIPI_TXP3 PINPOS('B', 1)
#define PIN_MIPI_TXM3 PINPOS('B', 2)
#define PIN_MIPI_TXP4 PINPOS('B', 3)
#define PIN_MIPIRX0P PINPOS('B', 4)
#define PIN_MIPIRX1N PINPOS('B', 5)
#define PIN_MIPIRX2N PINPOS('B', 6)
#define PIN_MIPIRX4N PINPOS('B', 7)
#define PIN_MIPIRX5N PINPOS('B', 8)
#define PIN_VIVO_D1 PINPOS('B', 9)
#define PIN_VIVO_D5 PINPOS('B', 10)
#define PIN_VIVO_D7 PINPOS('B', 11)
#define PIN_VIVO_D9 PINPOS('B', 12)
#define PIN_USB_ID PINPOS('B', 13)
#define PIN_ETH_RXM PINPOS('B', 15)
#define PIN_MIPI_TXP2 PINPOS('C', 1)
#define PIN_MIPI_TXM2 PINPOS('C', 2)
#define PIN_CAM_PD0 PINPOS('C', 3)
#define PIN_CAM_MCLK0 PINPOS('C', 4)
#define PIN_MIPIRX1P PINPOS('C', 5)
#define PIN_MIPIRX2P PINPOS('C', 6)
#define PIN_MIPIRX3N PINPOS('C', 7)
#define PIN_MIPIRX5P PINPOS('C', 8)
#define PIN_VIVO_CLK PINPOS('C', 9)
#define PIN_VIVO_D6 PINPOS('C', 10)
#define PIN_VIVO_D8 PINPOS('C', 11)
#define PIN_USB_VBUS_EN PINPOS('C', 12)
#define PIN_ETH_RXP PINPOS('C', 14)
#define PIN_GPIO_RTX PINPOS('C', 15)
#define PIN_MIPI_TXP1 PINPOS('D', 1)
#define PIN_MIPI_TXM1 PINPOS('D', 2)
#define PIN_CAM_MCLK1 PINPOS('D', 3)
#define PIN_IIC3_SCL PINPOS('D', 4)
#define PIN_VIVO_D4 PINPOS('D', 10)
#define PIN_ETH_TXM PINPOS('D', 14)
#define PIN_ETH_TXP PINPOS('D', 15)
#define PIN_MIPI_TXP0 PINPOS('E', 1)
#define PIN_MIPI_TXM0 PINPOS('E', 2)
#define PIN_CAM_PD1 PINPOS('E', 4)
#define PIN_CAM_RST0 PINPOS('E', 5)
#define PIN_VIVO_D0 PINPOS('E', 10)
#define PIN_ADC1 PINPOS('E', 13)
#define PIN_ADC2 PINPOS('E', 14)
#define PIN_ADC3 PINPOS('E', 15)
#define PIN_AUD_AOUTL PINPOS('F', 2)
#define PIN_IIC3_SDA PINPOS('F', 4)
#define PIN_SD1_D2 PINPOS('F', 14)
#define PIN_AUD_AOUTR PINPOS('G', 2)
#define PIN_SD1_D3 PINPOS('G', 13)
#define PIN_SD1_CLK PINPOS('G', 14)
#define PIN_SD1_CMD PINPOS('G', 15)
#define PIN_AUD_AINL_MIC PINPOS('H', 1)
#define PIN_RSTN PINPOS('H', 12)
#define PIN_PWM0_BUCK PINPOS('H', 13)
#define PIN_SD1_D1 PINPOS('H', 14)
#define PIN_SD1_D0 PINPOS('H', 15)
#define PIN_AUD_AINR_MIC PINPOS('J', 1)
#define PIN_IIC2_SCL PINPOS('J', 13)
#define PIN_IIC2_SDA PINPOS('J', 14)
#define PIN_SD0_CD PINPOS('K', 2)
#define PIN_SD0_D1 PINPOS('K', 3)
#define PIN_UART2_RX PINPOS('K', 13)
#define PIN_UART2_CTS PINPOS('K', 14)
#define PIN_UART2_TX PINPOS('K', 15)
#define PIN_SD0_CLK PINPOS('L', 1)
#define PIN_SD0_D0 PINPOS('L', 2)
#define PIN_SD0_CMD PINPOS('L', 3)
#define PIN_CLK32K PINPOS('L', 14)
#define PIN_UART2_RTS PINPOS('L', 15)
#define PIN_SD0_D3 PINPOS('M', 1)
#define PIN_SD0_D2 PINPOS('M', 2)
#define PIN_UART0_RX PINPOS('M', 4)
#define PIN_UART0_TX PINPOS('M', 5)
#define PIN_JTAG_CPU_TRST PINPOS('M', 6)
#define PIN_PWR_ON PINPOS('M', 11)
#define PIN_PWR_GPIO2 PINPOS('M', 12)
#define PIN_PWR_GPIO0 PINPOS('M', 13)
#define PIN_CLK25M PINPOS('M', 14)
#define PIN_SD0_PWR_EN PINPOS('N', 1)
#define PIN_SPK_EN PINPOS('N', 3)
#define PIN_JTAG_CPU_TCK PINPOS('N', 4)
#define PIN_JTAG_CPU_TMS PINPOS('N', 6)
#define PIN_PWR_WAKEUP1 PINPOS('N', 11)
#define PIN_PWR_WAKEUP0 PINPOS('N', 12)
#define PIN_PWR_GPIO1 PINPOS('N', 13)
#define PIN_EMMC_DAT3 PINPOS('P', 1)
#define PIN_EMMC_DAT0 PINPOS('P', 2)
#define PIN_EMMC_DAT2 PINPOS('P', 3)
#define PIN_EMMC_RSTN PINPOS('P', 4)
#define PIN_AUX0 PINPOS('P', 5)
#define PIN_IIC0_SDA PINPOS('P', 6)
#define PIN_PWR_SEQ3 PINPOS('P', 10)
#define PIN_PWR_VBAT_DET PINPOS('P', 11)
#define PIN_PWR_SEQ1 PINPOS('P', 12)
#define PIN_PWR_BUTTON1 PINPOS('P', 13)
#define PIN_EMMC_DAT1 PINPOS('R', 2)
#define PIN_EMMC_CMD PINPOS('R', 3)
#define PIN_EMMC_CLK PINPOS('R', 4)
#define PIN_IIC0_SCL PINPOS('R', 6)
#define PIN_GPIO_ZQ PINPOS('R', 10)
#define PIN_PWR_RSTN PINPOS('R', 11)
#define PIN_PWR_SEQ2 PINPOS('R', 12)
#define PIN_XTAL_XIN PINPOS('R', 13)
#endif /* _DT_BINDINGS_PINCTRL_CV1812H_H */

19
include/dt-bindings/pinctrl/pinctrl-cv18xx.h Normal file
View File

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2023 Sophgo Ltd.
*
* Author: Inochi Amaoto <inochiama@outlook.com>
*/
#ifndef _DT_BINDINGS_PINCTRL_CV18XX_H
#define _DT_BINDINGS_PINCTRL_CV18XX_H
#define PIN_MUX_INVALD 0xff
#define PINMUX2(pin, mux, mux2) \
(((pin) & 0xffff) | (((mux) & 0xff) << 16) | (((mux2) & 0xff) << 24))
#define PINMUX(pin, mux) \
PINMUX2(pin, mux, PIN_MUX_INVALD)
#endif /* _DT_BINDINGS_PINCTRL_CV18XX_H */

127
include/dt-bindings/pinctrl/pinctrl-sg2000.h Normal file
View File

@ -0,0 +1,127 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#ifndef _DT_BINDINGS_PINCTRL_SG2000_H
#define _DT_BINDINGS_PINCTRL_SG2000_H
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
#define PINPOS(row, col) \
((((row) - 'A' + 1) << 8) + ((col) - 1))
#define PIN_MIPI_TXM4 PINPOS('A', 2)
#define PIN_MIPIRX0N PINPOS('A', 4)
#define PIN_MIPIRX3P PINPOS('A', 6)
#define PIN_MIPIRX4P PINPOS('A', 7)
#define PIN_VIVO_D2 PINPOS('A', 9)
#define PIN_VIVO_D3 PINPOS('A', 10)
#define PIN_VIVO_D10 PINPOS('A', 12)
#define PIN_USB_VBUS_DET PINPOS('A', 13)
#define PIN_MIPI_TXP3 PINPOS('B', 1)
#define PIN_MIPI_TXM3 PINPOS('B', 2)
#define PIN_MIPI_TXP4 PINPOS('B', 3)
#define PIN_MIPIRX0P PINPOS('B', 4)
#define PIN_MIPIRX1N PINPOS('B', 5)
#define PIN_MIPIRX2N PINPOS('B', 6)
#define PIN_MIPIRX4N PINPOS('B', 7)
#define PIN_MIPIRX5N PINPOS('B', 8)
#define PIN_VIVO_D1 PINPOS('B', 9)
#define PIN_VIVO_D5 PINPOS('B', 10)
#define PIN_VIVO_D7 PINPOS('B', 11)
#define PIN_VIVO_D9 PINPOS('B', 12)
#define PIN_USB_ID PINPOS('B', 13)
#define PIN_ETH_RXM PINPOS('B', 15)
#define PIN_MIPI_TXP2 PINPOS('C', 1)
#define PIN_MIPI_TXM2 PINPOS('C', 2)
#define PIN_CAM_PD0 PINPOS('C', 3)
#define PIN_CAM_MCLK0 PINPOS('C', 4)
#define PIN_MIPIRX1P PINPOS('C', 5)
#define PIN_MIPIRX2P PINPOS('C', 6)
#define PIN_MIPIRX3N PINPOS('C', 7)
#define PIN_MIPIRX5P PINPOS('C', 8)
#define PIN_VIVO_CLK PINPOS('C', 9)
#define PIN_VIVO_D6 PINPOS('C', 10)
#define PIN_VIVO_D8 PINPOS('C', 11)
#define PIN_USB_VBUS_EN PINPOS('C', 12)
#define PIN_ETH_RXP PINPOS('C', 14)
#define PIN_GPIO_RTX PINPOS('C', 15)
#define PIN_MIPI_TXP1 PINPOS('D', 1)
#define PIN_MIPI_TXM1 PINPOS('D', 2)
#define PIN_CAM_MCLK1 PINPOS('D', 3)
#define PIN_IIC3_SCL PINPOS('D', 4)
#define PIN_VIVO_D4 PINPOS('D', 10)
#define PIN_ETH_TXM PINPOS('D', 14)
#define PIN_ETH_TXP PINPOS('D', 15)
#define PIN_MIPI_TXP0 PINPOS('E', 1)
#define PIN_MIPI_TXM0 PINPOS('E', 2)
#define PIN_CAM_PD1 PINPOS('E', 4)
#define PIN_CAM_RST0 PINPOS('E', 5)
#define PIN_VIVO_D0 PINPOS('E', 10)
#define PIN_ADC1 PINPOS('E', 13)
#define PIN_ADC2 PINPOS('E', 14)
#define PIN_ADC3 PINPOS('E', 15)
#define PIN_AUD_AOUTL PINPOS('F', 2)
#define PIN_IIC3_SDA PINPOS('F', 4)
#define PIN_SD1_D2 PINPOS('F', 14)
#define PIN_AUD_AOUTR PINPOS('G', 2)
#define PIN_SD1_D3 PINPOS('G', 13)
#define PIN_SD1_CLK PINPOS('G', 14)
#define PIN_SD1_CMD PINPOS('G', 15)
#define PIN_AUD_AINL_MIC PINPOS('H', 1)
#define PIN_RSTN PINPOS('H', 12)
#define PIN_PWM0_BUCK PINPOS('H', 13)
#define PIN_SD1_D1 PINPOS('H', 14)
#define PIN_SD1_D0 PINPOS('H', 15)
#define PIN_AUD_AINR_MIC PINPOS('J', 1)
#define PIN_IIC2_SCL PINPOS('J', 13)
#define PIN_IIC2_SDA PINPOS('J', 14)
#define PIN_SD0_CD PINPOS('K', 2)
#define PIN_SD0_D1 PINPOS('K', 3)
#define PIN_UART2_RX PINPOS('K', 13)
#define PIN_UART2_CTS PINPOS('K', 14)
#define PIN_UART2_TX PINPOS('K', 15)
#define PIN_SD0_CLK PINPOS('L', 1)
#define PIN_SD0_D0 PINPOS('L', 2)
#define PIN_SD0_CMD PINPOS('L', 3)
#define PIN_CLK32K PINPOS('L', 14)
#define PIN_UART2_RTS PINPOS('L', 15)
#define PIN_SD0_D3 PINPOS('M', 1)
#define PIN_SD0_D2 PINPOS('M', 2)
#define PIN_UART0_RX PINPOS('M', 4)
#define PIN_UART0_TX PINPOS('M', 5)
#define PIN_JTAG_CPU_TRST PINPOS('M', 6)
#define PIN_PWR_ON PINPOS('M', 11)
#define PIN_PWR_GPIO2 PINPOS('M', 12)
#define PIN_PWR_GPIO0 PINPOS('M', 13)
#define PIN_CLK25M PINPOS('M', 14)
#define PIN_SD0_PWR_EN PINPOS('N', 1)
#define PIN_SPK_EN PINPOS('N', 3)
#define PIN_JTAG_CPU_TCK PINPOS('N', 4)
#define PIN_JTAG_CPU_TMS PINPOS('N', 6)
#define PIN_PWR_WAKEUP1 PINPOS('N', 11)
#define PIN_PWR_WAKEUP0 PINPOS('N', 12)
#define PIN_PWR_GPIO1 PINPOS('N', 13)
#define PIN_EMMC_DAT3 PINPOS('P', 1)
#define PIN_EMMC_DAT0 PINPOS('P', 2)
#define PIN_EMMC_DAT2 PINPOS('P', 3)
#define PIN_EMMC_RSTN PINPOS('P', 4)
#define PIN_AUX0 PINPOS('P', 5)
#define PIN_IIC0_SDA PINPOS('P', 6)
#define PIN_PWR_SEQ3 PINPOS('P', 10)
#define PIN_PWR_VBAT_DET PINPOS('P', 11)
#define PIN_PWR_SEQ1 PINPOS('P', 12)
#define PIN_PWR_BUTTON1 PINPOS('P', 13)
#define PIN_EMMC_DAT1 PINPOS('R', 2)
#define PIN_EMMC_CMD PINPOS('R', 3)
#define PIN_EMMC_CLK PINPOS('R', 4)
#define PIN_IIC0_SCL PINPOS('R', 6)
#define PIN_GPIO_ZQ PINPOS('R', 10)
#define PIN_PWR_RSTN PINPOS('R', 11)
#define PIN_PWR_SEQ2 PINPOS('R', 12)
#define PIN_XTAL_XIN PINPOS('R', 13)
#endif /* _DT_BINDINGS_PINCTRL_SG2000_H */

79
include/dt-bindings/pinctrl/pinctrl-sg2002.h Normal file
View File

@ -0,0 +1,79 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*
* This file is generated from vendor pinout definition.
*/
#ifndef _DT_BINDINGS_PINCTRL_SG2002_H
#define _DT_BINDINGS_PINCTRL_SG2002_H
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
#define PIN_AUD_AINL_MIC 2
#define PIN_AUD_AOUTR 4
#define PIN_SD0_CLK 6
#define PIN_SD0_CMD 7
#define PIN_SD0_D0 8
#define PIN_SD0_D1 10
#define PIN_SD0_D2 11
#define PIN_SD0_D3 12
#define PIN_SD0_CD 14
#define PIN_SD0_PWR_EN 15
#define PIN_SPK_EN 17
#define PIN_UART0_TX 18
#define PIN_UART0_RX 19
#define PIN_EMMC_DAT2 20
#define PIN_EMMC_CLK 21
#define PIN_EMMC_DAT0 22
#define PIN_EMMC_DAT3 23
#define PIN_EMMC_CMD 24
#define PIN_EMMC_DAT1 25
#define PIN_JTAG_CPU_TMS 26
#define PIN_JTAG_CPU_TCK 27
#define PIN_IIC0_SCL 28
#define PIN_IIC0_SDA 29
#define PIN_AUX0 30
#define PIN_GPIO_ZQ 35
#define PIN_PWR_VBAT_DET 38
#define PIN_PWR_RSTN 39
#define PIN_PWR_SEQ1 40
#define PIN_PWR_SEQ2 41
#define PIN_PWR_WAKEUP0 43
#define PIN_PWR_BUTTON1 44
#define PIN_XTAL_XIN 45
#define PIN_PWR_GPIO0 47
#define PIN_PWR_GPIO1 48
#define PIN_PWR_GPIO2 49
#define PIN_SD1_D3 51
#define PIN_SD1_D2 52
#define PIN_SD1_D1 53
#define PIN_SD1_D0 54
#define PIN_SD1_CMD 55
#define PIN_SD1_CLK 56
#define PIN_PWM0_BUCK 58
#define PIN_ADC1 59
#define PIN_USB_VBUS_DET 60
#define PIN_ETH_TXP 62
#define PIN_ETH_TXM 63
#define PIN_ETH_RXP 64
#define PIN_ETH_RXM 65
#define PIN_GPIO_RTX 67
#define PIN_MIPIRX4N 72
#define PIN_MIPIRX4P 73
#define PIN_MIPIRX3N 74
#define PIN_MIPIRX3P 75
#define PIN_MIPIRX2N 76
#define PIN_MIPIRX2P 77
#define PIN_MIPIRX1N 78
#define PIN_MIPIRX1P 79
#define PIN_MIPIRX0N 80
#define PIN_MIPIRX0P 81
#define PIN_MIPI_TXM2 83
#define PIN_MIPI_TXP2 84
#define PIN_MIPI_TXM1 85
#define PIN_MIPI_TXP1 86
#define PIN_MIPI_TXM0 87
#define PIN_MIPI_TXP0 88
#endif /* _DT_BINDINGS_PINCTRL_SG2002_H */

3
include/linux/pinctrl/pinconf-generic.h
View File

@ -81,6 +81,8 @@ struct pinctrl_map;
* @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
* If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
* schmitt-trigger mode is disabled.
* @PIN_CONFIG_INPUT_SCHMITT_UV: this will configure an input pin to run in
* schmitt-trigger mode. The argument is in uV.
* @PIN_CONFIG_MODE_LOW_POWER: this will configure the pin for low power
* operation, if several modes of operation are supported these can be
* passed in the argument on a custom form, else just use argument 1
@ -132,6 +134,7 @@ enum pin_config_param {
PIN_CONFIG_INPUT_ENABLE,
PIN_CONFIG_INPUT_SCHMITT,
PIN_CONFIG_INPUT_SCHMITT_ENABLE,
PIN_CONFIG_INPUT_SCHMITT_UV,
PIN_CONFIG_MODE_LOW_POWER,
PIN_CONFIG_MODE_PWM,
PIN_CONFIG_OUTPUT,