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dt-bindings: PCI: Convert v3,v360epc-pci to DT schema
Convert the v3,v360epc-pci binding to DT schema format. Add "clocks" which was not documented and is required. Drop "syscon" which was documented, but is not used. Drop the "v3,v360epc-pci" compatible by itself as this device is only used on the Arm Integrator/AP and not likely going to be used anywhere else at this point. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patch.msgid.link/20250505220139.2202164-1-robh@kernel.org
This commit is contained in:
Rob Herring (Arm)
Manivannan Sadhasivam
parent
a733e71127
commit
9a5f8c7a81
100
Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml
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100
Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml
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@ -0,0 +1,100 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: V3 Semiconductor V360 EPC PCI bridge
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description:
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This bridge is found in the ARM Integrator/AP (Application Platform)
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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items:
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- const: arm,integrator-ap-pci
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- const: v3,v360epc-pci
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reg:
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items:
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- description: V3 host bridge controller
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- description: Configuration space
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clocks:
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maxItems: 1
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dma-ranges:
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maxItems: 2
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description:
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The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB,
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4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The
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memory should be marked as pre-fetchable.
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interrupts:
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description: Bus Error IRQ
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maxItems: 1
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ranges:
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description:
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The non-prefetchable and prefetchable memory windows must each be exactly
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256MB (0x10000000) in size. The prefetchable memory window must be
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immediately adjacent to the non-prefetchable memory window.
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required:
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- compatible
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- reg
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- clocks
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- dma-ranges
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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unevaluatedProperties: false
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examples:
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- |
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pci@62000000 {
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compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
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device_type = "pci";
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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clocks = <&pciclk>;
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ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>, /* 16 MiB @ LB 60000000 */
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<0x02000000 0 0x40000000 0x40000000 0 0x10000000>, /* 256 MiB @ LB 40000000 1:1 */
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<0x42000000 0 0x50000000 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
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dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */
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<0x02000000 0 0x80000000 0x80000000 0 0x40000000>; /* CM alias: 1GB @ LB 80000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map =
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/* IDSEL 9 */
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<0x4800 0 0 1 &pic 13>, /* INT A on slot 9 is irq 13 */
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<0x4800 0 0 2 &pic 14>, /* INT B on slot 9 is irq 14 */
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<0x4800 0 0 3 &pic 15>, /* INT C on slot 9 is irq 15 */
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<0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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<0x5000 0 0 1 &pic 14>, /* INT A on slot 10 is irq 14 */
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<0x5000 0 0 2 &pic 15>, /* INT B on slot 10 is irq 15 */
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<0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */
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<0x5000 0 0 4 &pic 13>, /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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<0x5800 0 0 1 &pic 15>, /* INT A on slot 11 is irq 15 */
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<0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */
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<0x5800 0 0 3 &pic 13>, /* INT C on slot 11 is irq 13 */
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<0x5800 0 0 4 &pic 14>, /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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<0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */
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<0x6000 0 0 2 &pic 13>, /* INT B on slot 12 is irq 13 */
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<0x6000 0 0 3 &pic 14>, /* INT C on slot 12 is irq 14 */
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<0x6000 0 0 4 &pic 15>; /* INT D on slot 12 is irq 15 */
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};
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...
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@ -1,76 +0,0 @@
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V3 Semiconductor V360 EPC PCI bridge
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This bridge is found in the ARM Integrator/AP (Application Platform)
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Required properties:
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- compatible: should be one of:
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"v3,v360epc-pci"
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"arm,integrator-ap-pci", "v3,v360epc-pci"
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- reg: should contain two register areas:
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first the base address of the V3 host bridge controller, 64KB
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second the configuration area register space, 16MB
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- interrupts: should contain a reference to the V3 error interrupt
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as routed on the system.
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- bus-range: see pci.txt
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- ranges: this follows the standard PCI bindings in the IEEE Std
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1275-1994 (see pci.txt) with the following restriction:
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- The non-prefetchable and prefetchable memory windows must
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each be exactly 256MB (0x10000000) in size.
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- The prefetchable memory window must be immediately adjacent
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to the non-prefetcable memory window
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- dma-ranges: three ranges for the inbound memory region. The ranges must
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be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
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64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
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as pre-fetchable. Two ranges are supported by the hardware.
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Integrator-specific required properties:
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- syscon: should contain a link to the syscon device node, since
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on the Integrator, some registers in the syscon are required to
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operate the V3 host bridge.
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Example:
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pci: pciv3@62000000 {
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compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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clocks = <&pciclk>;
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bus-range = <0x00 0xff>;
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ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
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0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
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0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
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0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
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0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
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0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
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dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
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0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
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0x02000000 0 0x80000000 /* Core module alias memory */
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0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <
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/* IDSEL 9 */
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0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
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0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
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0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
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0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
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0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
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0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
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0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
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0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
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0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
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0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
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0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
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>;
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};
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@ -18568,7 +18568,7 @@ PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
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M: Linus Walleij <linus.walleij@linaro.org>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
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F: Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml
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F: drivers/pci/controller/pci-v3-semi.c
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PCI DRIVER FOR XILINX VERSAL CPM
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