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clk: meson: s4: fix fixed_pll_dco clock

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The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.

Fixes: 57b55c76aa ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Xianwei Zhao 2024-06-03 18:04:33 +08:00 committed by Jerome Brunet
parent 1613e604df
commit c1380adf2e
1 changed files with 5 additions and 0 deletions
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5
drivers/clk/meson/s4-pll.c
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@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = {
.shift = 0,
.width = 8,
},
.frac = {
.reg_off = ANACTRL_FIXPLL_CTRL1,
.shift = 0,
.width = 17,
},
.n = {
.reg_off = ANACTRL_FIXPLL_CTRL0,
.shift = 10,