mirror of
git://git.yoctoproject.org/linux-yocto.git
synced 2025-10-22 23:13:01 +02:00
drm fixes for 6.16-rc7
dp: - aux dpcd address fix xe: - SR-IOV fixes for GT reset and TLB invalidation - Fix memory copy direction during migration - Fix alignment check on migration - Fix MOCS and page fault init order to correctly account for topology amdgpu: - Fix a DC memory leak - DCN 4.0.1 degamma LUT fix - Fix reset counter handling for soft recovery - GC 8 fix radeon: - Drop console locks when suspending/resuming nouveau: - ioctl validation fix panfrost: - scheduler bug fix mediatek: - Add wait_event_timeout when disabling plane - only announce AFBC if really supported - mtk_dpi: Reorder output formats on MT8195/88 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmh6IjUACgkQDHTzWXnE hr5Mow/+J+FdXUi/5N8S6WUfk7tXY1+OQ0qOIx6px2QHc0yFR20ab6Izwjy1fjzf AmlgYexniWPqXO/4JimeDHP0Cn3OnsuH652lt0HSVE2WR/uo+dYvGwvGx/xk+0tE WjODlx2U4GHLmgPo7BRTB9vR+FMhKOVK5drVv1i1Vfnt6bhnNJF8kwGJHLa79koO JYhK8ngxP+JZAINPXp42HC3z/cArbvwUe5FcUrlIOA6xEw9sVSP452cI783bGGTV 8CQoa5Z0rMOFKvbnAJDmDBMaIIUa8NddCDM0CyZ7EIVa2AMvcOoEL//BoHpn4X2E r8JRpsCRx7z734Hv/vK61zVrOlo3nqisWKWKIEXreDtjDCriSPC6BpyMabJJ07Ly giYtXSTJG2Lu69BEJsudITfU7YYwEGZ32W1k2rUmAZT47NwnFpsnInTcxd1mpa0H FDegXQHtfIhYZo59Woa62xBc/f7bxzlMdjYCHZ8T7G9up4Ofrt+UGjZJU6h5VpVN S9RT73Yw0HOJYX06IbK7HVCAXlOY+6eJ0mJYYpuz0pzanHDSFL22A99qjE7oVsUP /Yndij07yBDBNV8WY9gKJDbCQEBrPMmVF7l/6vSJqclstrxJV0mAx/H06kNtsDU1 i0GrzTfkwK8fzsKZx3T6x7n32hREe22Srej8jlN8ezXBwWQP/ow= =VtzE -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2025-07-18-1' of https://gitlab.freedesktop.org/drm/kernel Pull drm fixes from Dave Airlie: "Seems like a quiet enough week, xe/amdgpu being the usual suspects, then mediatek with a few fixes, and otherwise just misc other bits. dp: - aux dpcd address fix xe: - SR-IOV fixes for GT reset and TLB invalidation - Fix memory copy direction during migration - Fix alignment check on migration - Fix MOCS and page fault init order to correctly account for topology amdgpu: - Fix a DC memory leak - DCN 4.0.1 degamma LUT fix - Fix reset counter handling for soft recovery - GC 8 fix radeon: - Drop console locks when suspending/resuming nouveau: - ioctl validation fix panfrost: - scheduler bug fix mediatek: - Add wait_event_timeout when disabling plane - only announce AFBC if really supported - mtk_dpi: Reorder output formats on MT8195/88" * tag 'drm-fixes-2025-07-18-1' of https://gitlab.freedesktop.org/drm/kernel: drm/mediatek: mtk_dpi: Reorder output formats on MT8195/88 drm/mediatek: only announce AFBC if really supported drm/mediatek: Add wait_event_timeout when disabling plane drm/xe/pf: Resend PF provisioning after GT reset drm/xe/pf: Prepare to stop SR-IOV support prior GT reset drm/xe/migrate: Fix alignment check drm/xe: Move page fault init after topology init drm/xe/mocs: Initialize MOCS index early drm/xe/migrate: fix copy direction in access_memory drm/xe: Dont skip TLB invalidations on VF drm/amdgpu/gfx8: reset compute ring wptr on the GPU on resume drm/amdgpu: Increase reset counter only on success drm/radeon: Do not hold console lock during resume drm/radeon: Do not hold console lock while suspending clients drm/amd/display: Disable CRTC degamma LUT for DCN401 drm/amd/display: Free memory allocation drm/dp: Change AUX DPCD probe address from LANE0_1_STATUS to TRAINING_PATTERN_SET drm/panfrost: Fix scheduler workqueue bug drm/nouveau: check ioctl command codes better
This commit is contained in:
Linus Torvalds
commit
c460535a6d
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@ -427,6 +427,7 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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{
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unsigned long flags;
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ktime_t deadline;
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bool ret;
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if (unlikely(ring->adev->debug_disable_soft_recovery))
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return false;
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@ -441,12 +442,16 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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dma_fence_set_error(fence, -ENODATA);
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spin_unlock_irqrestore(fence->lock, flags);
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atomic_inc(&ring->adev->gpu_reset_counter);
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while (!dma_fence_is_signaled(fence) &&
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ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
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ring->funcs->soft_recovery(ring, vmid);
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return dma_fence_is_signaled(fence);
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ret = dma_fence_is_signaled(fence);
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/* increment the counter only if soft reset worked */
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if (ret)
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atomic_inc(&ring->adev->gpu_reset_counter);
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return ret;
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}
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/*
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@ -4640,6 +4640,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
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/* reset ring buffer */
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ring->wptr = 0;
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atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
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amdgpu_ring_clear_ring(ring);
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}
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return 0;
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@ -728,7 +728,16 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
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* support programmable degamma anywhere.
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*/
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is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
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drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
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/* Dont't enable DRM CRTC degamma property for DCN401 since the
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* pre-blending degamma LUT doesn't apply to cursor, and therefore
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* can't work similar to a post-blending degamma LUT as in other hw
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* versions.
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* TODO: revisit it once KMS plane color API is merged.
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*/
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drm_crtc_enable_color_mgmt(&acrtc->base,
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(is_dcn &&
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dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01) ?
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MAX_COLOR_LUT_ENTRIES : 0,
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true, MAX_COLOR_LUT_ENTRIES);
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drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
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@ -1565,7 +1565,7 @@ struct clk_mgr_internal *dcn401_clk_mgr_construct(
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clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
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if (!clk_mgr->base.bw_params) {
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BREAK_TO_DEBUGGER();
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kfree(clk_mgr);
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kfree(clk_mgr401);
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return NULL;
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}
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@ -1576,6 +1576,7 @@ struct clk_mgr_internal *dcn401_clk_mgr_construct(
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if (!clk_mgr->wm_range_table) {
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BREAK_TO_DEBUGGER();
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kfree(clk_mgr->base.bw_params);
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kfree(clk_mgr401);
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return NULL;
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}
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@ -725,7 +725,7 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
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* monitor doesn't power down exactly after the throw away read.
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*/
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if (!aux->is_remote) {
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ret = drm_dp_dpcd_probe(aux, DP_LANE0_1_STATUS);
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ret = drm_dp_dpcd_probe(aux, DP_TRAINING_PATTERN_SET);
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if (ret < 0)
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return ret;
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}
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@ -719,6 +719,39 @@ int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
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return 0;
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}
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void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane)
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{
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
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struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state);
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int i;
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/* no need to wait for disabling the plane by CPU */
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if (!mtk_crtc->cmdq_client.chan)
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return;
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if (!mtk_crtc->enabled)
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return;
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/* set pending plane state to disabled */
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for (i = 0; i < mtk_crtc->layer_nr; i++) {
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struct drm_plane *mtk_plane = &mtk_crtc->planes[i];
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struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(mtk_plane->state);
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if (mtk_plane->index == plane->index) {
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memcpy(mtk_plane_state, plane_state, sizeof(*plane_state));
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break;
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}
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}
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mtk_crtc_update_config(mtk_crtc, false);
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/* wait for planes to be disabled by CMDQ */
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wait_event_timeout(mtk_crtc->cb_blocking_queue,
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mtk_crtc->cmdq_vblank_cnt == 0,
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msecs_to_jiffies(500));
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#endif
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}
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void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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@ -930,7 +963,8 @@ static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
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mtk_ddp_comp_supported_rotations(comp),
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mtk_ddp_comp_get_blend_modes(comp),
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mtk_ddp_comp_get_formats(comp),
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mtk_ddp_comp_get_num_formats(comp), i);
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mtk_ddp_comp_get_num_formats(comp),
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mtk_ddp_comp_is_afbc_supported(comp), i);
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if (ret)
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return ret;
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@ -21,6 +21,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
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unsigned int num_conn_routes);
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int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
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struct mtk_plane_state *state);
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void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane);
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void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
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struct drm_atomic_state *plane_state);
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struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc);
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@ -366,6 +366,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
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.get_blend_modes = mtk_ovl_get_blend_modes,
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.get_formats = mtk_ovl_get_formats,
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.get_num_formats = mtk_ovl_get_num_formats,
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.is_afbc_supported = mtk_ovl_is_afbc_supported,
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};
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static const struct mtk_ddp_comp_funcs ddp_postmask = {
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@ -83,6 +83,7 @@ struct mtk_ddp_comp_funcs {
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u32 (*get_blend_modes)(struct device *dev);
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const u32 *(*get_formats)(struct device *dev);
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size_t (*get_num_formats)(struct device *dev);
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bool (*is_afbc_supported)(struct device *dev);
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void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
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void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
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void (*add)(struct device *dev, struct mtk_mutex *mutex);
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@ -294,6 +295,14 @@ size_t mtk_ddp_comp_get_num_formats(struct mtk_ddp_comp *comp)
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return 0;
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}
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static inline bool mtk_ddp_comp_is_afbc_supported(struct mtk_ddp_comp *comp)
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{
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if (comp->funcs && comp->funcs->is_afbc_supported)
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return comp->funcs->is_afbc_supported(comp->dev);
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return false;
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}
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static inline bool mtk_ddp_comp_add(struct mtk_ddp_comp *comp, struct mtk_mutex *mutex)
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{
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if (comp->funcs && comp->funcs->add) {
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@ -106,6 +106,7 @@ void mtk_ovl_disable_vblank(struct device *dev);
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u32 mtk_ovl_get_blend_modes(struct device *dev);
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const u32 *mtk_ovl_get_formats(struct device *dev);
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size_t mtk_ovl_get_num_formats(struct device *dev);
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bool mtk_ovl_is_afbc_supported(struct device *dev);
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void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex);
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void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
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@ -236,6 +236,13 @@ size_t mtk_ovl_get_num_formats(struct device *dev)
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return ovl->data->num_formats;
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}
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bool mtk_ovl_is_afbc_supported(struct device *dev)
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{
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struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
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return ovl->data->supports_afbc;
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}
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int mtk_ovl_clk_enable(struct device *dev)
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{
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struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
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@ -1095,7 +1095,6 @@ static const u32 mt8183_output_fmts[] = {
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};
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static const u32 mt8195_dpi_output_fmts[] = {
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MEDIA_BUS_FMT_BGR888_1X24,
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MEDIA_BUS_FMT_RGB888_1X24,
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MEDIA_BUS_FMT_RGB888_2X12_LE,
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MEDIA_BUS_FMT_RGB888_2X12_BE,
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@ -1103,18 +1102,19 @@ static const u32 mt8195_dpi_output_fmts[] = {
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MEDIA_BUS_FMT_YUYV8_1X16,
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MEDIA_BUS_FMT_YUYV10_1X20,
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MEDIA_BUS_FMT_YUYV12_1X24,
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MEDIA_BUS_FMT_BGR888_1X24,
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MEDIA_BUS_FMT_YUV8_1X24,
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MEDIA_BUS_FMT_YUV10_1X30,
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};
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static const u32 mt8195_dp_intf_output_fmts[] = {
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MEDIA_BUS_FMT_BGR888_1X24,
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MEDIA_BUS_FMT_RGB888_1X24,
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MEDIA_BUS_FMT_RGB888_2X12_LE,
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MEDIA_BUS_FMT_RGB888_2X12_BE,
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MEDIA_BUS_FMT_RGB101010_1X30,
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MEDIA_BUS_FMT_YUYV8_1X16,
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MEDIA_BUS_FMT_YUYV10_1X20,
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MEDIA_BUS_FMT_BGR888_1X24,
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MEDIA_BUS_FMT_YUV8_1X24,
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MEDIA_BUS_FMT_YUV10_1X30,
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};
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|
|
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@ -285,9 +285,14 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(new_state);
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struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
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plane);
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mtk_plane_state->pending.enable = false;
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wmb(); /* Make sure the above parameter is set before update */
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mtk_plane_state->pending.dirty = true;
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mtk_crtc_plane_disable(old_state->crtc, plane);
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}
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static void mtk_plane_atomic_update(struct drm_plane *plane,
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@ -321,7 +326,8 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
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int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
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unsigned long possible_crtcs, enum drm_plane_type type,
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unsigned int supported_rotations, const u32 blend_modes,
|
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const u32 *formats, size_t num_formats, unsigned int plane_idx)
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const u32 *formats, size_t num_formats,
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bool supports_afbc, unsigned int plane_idx)
|
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{
|
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int err;
|
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|
||||
|
|
@ -332,7 +338,9 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
|
|||
|
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err = drm_universal_plane_init(dev, plane, possible_crtcs,
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&mtk_plane_funcs, formats,
|
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num_formats, modifiers, type, NULL);
|
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num_formats,
|
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supports_afbc ? modifiers : NULL,
|
||||
type, NULL);
|
||||
if (err) {
|
||||
DRM_ERROR("failed to initialize plane\n");
|
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return err;
|
||||
|
|
|
|||
|
|
@ -49,5 +49,6 @@ to_mtk_plane_state(struct drm_plane_state *state)
|
|||
int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
|
||||
unsigned long possible_crtcs, enum drm_plane_type type,
|
||||
unsigned int supported_rotations, const u32 blend_modes,
|
||||
const u32 *formats, size_t num_formats, unsigned int plane_idx);
|
||||
const u32 *formats, size_t num_formats,
|
||||
bool supports_afbc, unsigned int plane_idx);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1284,6 +1284,9 @@ nouveau_ioctls[] = {
|
|||
DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW),
|
||||
};
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_NVIF _IOC(_IOC_READ | _IOC_WRITE, DRM_IOCTL_BASE, \
|
||||
DRM_COMMAND_BASE + DRM_NOUVEAU_NVIF, 0)
|
||||
|
||||
long
|
||||
nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
|
|
@ -1297,14 +1300,10 @@ nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|||
return ret;
|
||||
}
|
||||
|
||||
switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
|
||||
case DRM_NOUVEAU_NVIF:
|
||||
if ((cmd & ~IOCSIZE_MASK) == DRM_IOCTL_NOUVEAU_NVIF)
|
||||
ret = nouveau_abi16_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
|
||||
break;
|
||||
default:
|
||||
else
|
||||
ret = drm_ioctl(file, cmd, arg);
|
||||
break;
|
||||
}
|
||||
|
||||
pm_runtime_mark_last_busy(dev->dev);
|
||||
pm_runtime_put_autosuspend(dev->dev);
|
||||
|
|
|
|||
|
|
@ -841,7 +841,6 @@ int panfrost_job_init(struct panfrost_device *pfdev)
|
|||
.num_rqs = DRM_SCHED_PRIORITY_COUNT,
|
||||
.credit_limit = 2,
|
||||
.timeout = msecs_to_jiffies(JOB_TIMEOUT_MS),
|
||||
.timeout_wq = pfdev->reset.wq,
|
||||
.name = "pan_js",
|
||||
.dev = pfdev->dev,
|
||||
};
|
||||
|
|
@ -879,6 +878,7 @@ int panfrost_job_init(struct panfrost_device *pfdev)
|
|||
pfdev->reset.wq = alloc_ordered_workqueue("panfrost-reset", 0);
|
||||
if (!pfdev->reset.wq)
|
||||
return -ENOMEM;
|
||||
args.timeout_wq = pfdev->reset.wq;
|
||||
|
||||
for (j = 0; j < NUM_JOB_SLOTS; j++) {
|
||||
js->queue[j].fence_context = dma_fence_context_alloc(1);
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
* Jerome Glisse
|
||||
*/
|
||||
|
||||
#include <linux/console.h>
|
||||
#include <linux/efi.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
|
@ -1635,11 +1634,9 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend,
|
|||
pci_set_power_state(pdev, PCI_D3hot);
|
||||
}
|
||||
|
||||
if (notify_clients) {
|
||||
console_lock();
|
||||
drm_client_dev_suspend(dev, true);
|
||||
console_unlock();
|
||||
}
|
||||
if (notify_clients)
|
||||
drm_client_dev_suspend(dev, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1661,17 +1658,11 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool notify_clients)
|
|||
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
||||
return 0;
|
||||
|
||||
if (notify_clients) {
|
||||
console_lock();
|
||||
}
|
||||
if (resume) {
|
||||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
if (pci_enable_device(pdev)) {
|
||||
if (notify_clients)
|
||||
console_unlock();
|
||||
if (pci_enable_device(pdev))
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
/* resume AGP if in use */
|
||||
radeon_agp_resume(rdev);
|
||||
|
|
@ -1747,10 +1738,8 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool notify_clients)
|
|||
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
|
||||
radeon_pm_compute_clocks(rdev);
|
||||
|
||||
if (notify_clients) {
|
||||
drm_client_dev_resume(dev, true);
|
||||
console_unlock();
|
||||
}
|
||||
if (notify_clients)
|
||||
drm_client_dev_resume(dev, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -417,6 +417,8 @@ int xe_gt_init_early(struct xe_gt *gt)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
xe_mocs_init_early(gt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -630,12 +632,6 @@ int xe_gt_init(struct xe_gt *gt)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
err = xe_gt_pagefault_init(gt);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
xe_mocs_init_early(gt);
|
||||
|
||||
err = xe_gt_sysfs_init(gt);
|
||||
if (err)
|
||||
return err;
|
||||
|
|
@ -644,6 +640,10 @@ int xe_gt_init(struct xe_gt *gt)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
err = xe_gt_pagefault_init(gt);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = xe_gt_idle_init(>->gtidle);
|
||||
if (err)
|
||||
return err;
|
||||
|
|
@ -839,6 +839,9 @@ static int gt_reset(struct xe_gt *gt)
|
|||
goto err_out;
|
||||
}
|
||||
|
||||
if (IS_SRIOV_PF(gt_to_xe(gt)))
|
||||
xe_gt_sriov_pf_stop_prepare(gt);
|
||||
|
||||
xe_uc_gucrc_disable(>->uc);
|
||||
xe_uc_stop_prepare(>->uc);
|
||||
xe_gt_pagefault_reset(gt);
|
||||
|
|
|
|||
|
|
@ -172,6 +172,25 @@ void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid)
|
|||
pf_clear_vf_scratch_regs(gt, vfid);
|
||||
}
|
||||
|
||||
static void pf_cancel_restart(struct xe_gt *gt)
|
||||
{
|
||||
xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
|
||||
|
||||
if (cancel_work_sync(>->sriov.pf.workers.restart))
|
||||
xe_gt_sriov_dbg_verbose(gt, "pending restart canceled!\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* xe_gt_sriov_pf_stop_prepare() - Prepare to stop SR-IOV support.
|
||||
* @gt: the &xe_gt
|
||||
*
|
||||
* This function can only be called on the PF.
|
||||
*/
|
||||
void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt)
|
||||
{
|
||||
pf_cancel_restart(gt);
|
||||
}
|
||||
|
||||
static void pf_restart(struct xe_gt *gt)
|
||||
{
|
||||
struct xe_device *xe = gt_to_xe(gt);
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ int xe_gt_sriov_pf_init_early(struct xe_gt *gt);
|
|||
int xe_gt_sriov_pf_init(struct xe_gt *gt);
|
||||
void xe_gt_sriov_pf_init_hw(struct xe_gt *gt);
|
||||
void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid);
|
||||
void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt);
|
||||
void xe_gt_sriov_pf_restart(struct xe_gt *gt);
|
||||
#else
|
||||
static inline int xe_gt_sriov_pf_init_early(struct xe_gt *gt)
|
||||
|
|
@ -29,6 +30,10 @@ static inline void xe_gt_sriov_pf_init_hw(struct xe_gt *gt)
|
|||
{
|
||||
}
|
||||
|
||||
static inline void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void xe_gt_sriov_pf_restart(struct xe_gt *gt)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2364,6 +2364,21 @@ int xe_gt_sriov_pf_config_restore(struct xe_gt *gt, unsigned int vfid,
|
|||
return err;
|
||||
}
|
||||
|
||||
static int pf_push_self_config(struct xe_gt *gt)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = pf_push_full_vf_config(gt, PFID);
|
||||
if (err) {
|
||||
xe_gt_sriov_err(gt, "Failed to push self configuration (%pe)\n",
|
||||
ERR_PTR(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
xe_gt_sriov_dbg_verbose(gt, "self configuration completed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fini_config(void *arg)
|
||||
{
|
||||
struct xe_gt *gt = arg;
|
||||
|
|
@ -2387,9 +2402,17 @@ static void fini_config(void *arg)
|
|||
int xe_gt_sriov_pf_config_init(struct xe_gt *gt)
|
||||
{
|
||||
struct xe_device *xe = gt_to_xe(gt);
|
||||
int err;
|
||||
|
||||
xe_gt_assert(gt, IS_SRIOV_PF(xe));
|
||||
|
||||
mutex_lock(xe_gt_sriov_pf_master_mutex(gt));
|
||||
err = pf_push_self_config(gt);
|
||||
mutex_unlock(xe_gt_sriov_pf_master_mutex(gt));
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return devm_add_action_or_reset(xe->drm.dev, fini_config, gt);
|
||||
}
|
||||
|
||||
|
|
@ -2407,6 +2430,10 @@ void xe_gt_sriov_pf_config_restart(struct xe_gt *gt)
|
|||
unsigned int n, total_vfs = xe_sriov_pf_get_totalvfs(gt_to_xe(gt));
|
||||
unsigned int fail = 0, skip = 0;
|
||||
|
||||
mutex_lock(xe_gt_sriov_pf_master_mutex(gt));
|
||||
pf_push_self_config(gt);
|
||||
mutex_unlock(xe_gt_sriov_pf_master_mutex(gt));
|
||||
|
||||
for (n = 1; n <= total_vfs; n++) {
|
||||
if (xe_gt_sriov_pf_config_is_empty(gt, n))
|
||||
skip++;
|
||||
|
|
|
|||
|
|
@ -1817,8 +1817,8 @@ int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
|
|||
xe_bo_assert_held(bo);
|
||||
|
||||
/* Use bounce buffer for small access and unaligned access */
|
||||
if (len & XE_CACHELINE_MASK ||
|
||||
((uintptr_t)buf | offset) & XE_CACHELINE_MASK) {
|
||||
if (!IS_ALIGNED(len, XE_CACHELINE_BYTES) ||
|
||||
!IS_ALIGNED((unsigned long)buf + offset, XE_CACHELINE_BYTES)) {
|
||||
int buf_offset = 0;
|
||||
|
||||
/*
|
||||
|
|
@ -1848,7 +1848,7 @@ int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
|
|||
err = xe_migrate_access_memory(m, bo,
|
||||
offset & ~XE_CACHELINE_MASK,
|
||||
(void *)ptr,
|
||||
sizeof(bounce), 0);
|
||||
sizeof(bounce), write);
|
||||
if (err)
|
||||
return err;
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -110,13 +110,14 @@ static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
|
|||
return i;
|
||||
}
|
||||
|
||||
static int emit_flush_invalidate(u32 *dw, int i)
|
||||
static int emit_flush_invalidate(u32 addr, u32 val, u32 *dw, int i)
|
||||
{
|
||||
dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |
|
||||
MI_FLUSH_IMM_DW | MI_FLUSH_DW_STORE_INDEX;
|
||||
dw[i++] = LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR;
|
||||
dw[i++] = 0;
|
||||
MI_FLUSH_IMM_DW;
|
||||
|
||||
dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
|
||||
dw[i++] = 0;
|
||||
dw[i++] = val;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
|
@ -397,23 +398,20 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
|
|||
static void emit_migration_job_gen12(struct xe_sched_job *job,
|
||||
struct xe_lrc *lrc, u32 seqno)
|
||||
{
|
||||
u32 saddr = xe_lrc_start_seqno_ggtt_addr(lrc);
|
||||
u32 dw[MAX_JOB_SIZE_DW], i = 0;
|
||||
|
||||
i = emit_copy_timestamp(lrc, dw, i);
|
||||
|
||||
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
|
||||
seqno, dw, i);
|
||||
i = emit_store_imm_ggtt(saddr, seqno, dw, i);
|
||||
|
||||
dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */
|
||||
|
||||
i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i);
|
||||
|
||||
if (!IS_SRIOV_VF(gt_to_xe(job->q->gt))) {
|
||||
/* XXX: Do we need this? Leaving for now. */
|
||||
dw[i++] = preparser_disable(true);
|
||||
i = emit_flush_invalidate(dw, i);
|
||||
dw[i++] = preparser_disable(false);
|
||||
}
|
||||
dw[i++] = preparser_disable(true);
|
||||
i = emit_flush_invalidate(saddr, seqno, dw, i);
|
||||
dw[i++] = preparser_disable(false);
|
||||
|
||||
i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user