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Merge branch 'v6.12/standard/base' into v6.12/standard/bcm-2xxx-rpi

Browse Source 
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>

# Conflicts:
#	drivers/gpu/drm/vc4/tests/vc4_mock_output.c
This commit is contained in:
Bruce Ashfield 2025-06-25 17:21:35 -04:00
commit d75ce4d404
515 changed files with 5513 additions and 3063 deletions
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21
Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
View File

@ -27,22 +27,31 @@ properties:
maxItems: 1
"#pwm-cells":
const: 2
const: 3
clocks:
maxItems: 1
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: axi
- const: ext
required:
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
pwm@44b00000 {
compatible = "adi,axi-pwmgen-2.00.a";
reg = <0x44b00000 0x1000>;
clocks = <&spi_clk>;
#pwm-cells = <2>;
compatible = "adi,axi-pwmgen-2.00.a";
reg = <0x44b00000 0x1000>;
clocks = <&fpga_clk>, <&spi_clk>;
clock-names = "axi", "ext";
#pwm-cells = <3>;
};

8
Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
View File

@ -35,8 +35,8 @@ additionalProperties: false
examples:
- |
pwm: pwm@f0408000 {
compatible = "brcm,bcm7038-pwm";
reg = <0xf0408000 0x28>;
#pwm-cells = <2>;
clocks = <&upg_fixed>;
compatible = "brcm,bcm7038-pwm";
reg = <0xf0408000 0x28>;
#pwm-cells = <2>;
clocks = <&upg_fixed>;
};

8
Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml
View File

@ -43,9 +43,9 @@ examples:
#include <dt-bindings/clock/bcm281xx.h>
pwm@3e01a000 {
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
reg = <0x3e01a000 0xcc>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
#pwm-cells = <3>;
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
reg = <0x3e01a000 0xcc>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
#pwm-cells = <3>;
};
...

12
Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml
View File

@ -33,7 +33,7 @@ patternProperties:
"^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$":
type: object
$ref: fixed-regulator.yaml#
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for single fixed LDO regulator.
@ -112,7 +112,6 @@ examples:
regulator-enable-ramp-delay = <220>;
};
mt6357_vfe28_reg: ldo-vfe28 {
compatible = "regulator-fixed";
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -125,14 +124,12 @@ examples:
regulator-enable-ramp-delay = <110>;
};
mt6357_vrf18_reg: ldo-vrf18 {
compatible = "regulator-fixed";
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <110>;
};
mt6357_vrf12_reg: ldo-vrf12 {
compatible = "regulator-fixed";
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@ -157,14 +154,12 @@ examples:
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn28_reg: ldo-vcn28 {
compatible = "regulator-fixed";
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vcn18_reg: ldo-vcn18 {
compatible = "regulator-fixed";
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -183,7 +178,6 @@ examples:
regulator-enable-ramp-delay = <264>;
};
mt6357_vcamio_reg: ldo-vcamio18 {
compatible = "regulator-fixed";
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -212,28 +206,24 @@ examples:
regulator-always-on;
};
mt6357_vaux18_reg: ldo-vaux18 {
compatible = "regulator-fixed";
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vaud28_reg: ldo-vaud28 {
compatible = "regulator-fixed";
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vio28_reg: ldo-vio28 {
compatible = "regulator-fixed";
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <264>;
};
mt6357_vio18_reg: ldo-vio18 {
compatible = "regulator-fixed";
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;

4
Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml
View File

@ -50,7 +50,7 @@ required:
- compatible
allOf:
- $ref: reserved-memory.yaml
- $ref: /schemas/reserved-memory/reserved-memory.yaml
unevaluatedProperties: false
@ -61,7 +61,7 @@ examples:
#size-cells = <2>;
qman-fqd {
compatible = "shared-dma-pool";
compatible = "fsl,qman-fqd";
size = <0 0x400000>;
alignment = <0 0x400000>;
no-map;

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -852,6 +852,8 @@ patternProperties:
description: Linux-specific binding
"^linx,.*":
description: Linx Technologies
"^liontron,.*":
description: Shenzhen Liontron Technology Co., Ltd
"^liteon,.*":
description: LITE-ON Technology Corp.
"^litex,.*":

1
Documentation/gpu/xe/index.rst
View File

@ -16,6 +16,7 @@ DG2, etc is provided to prototype the driver.
xe_migrate
xe_cs
xe_pm
xe_gt_freq
xe_pcode
xe_gt_mcr
xe_wa

14
Documentation/gpu/xe/xe_gt_freq.rst Normal file
View File

@ -0,0 +1,14 @@
.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
==========================
Xe GT Frequency Management
==========================
.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_freq.c
:doc: Xe GT Frequency Management
Internal API
============
.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_freq.c
:internal:

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 12
SUBLEVEL = 33
SUBLEVEL = 34
EXTRAVERSION =
NAME = Baby Opossum Posse

2
arch/arm/boot/dts/microchip/at91sam9263ek.dts
View File

@ -152,7 +152,7 @@
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;

2
arch/arm/boot/dts/microchip/tny_a9263.dts
View File

@ -64,7 +64,7 @@
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;

4
arch/arm/boot/dts/microchip/usb_a9263.dts
View File

@ -58,7 +58,7 @@
};
spi0: spi@fffa4000 {
cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
@ -84,7 +84,7 @@
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;

82
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
View File

@ -213,12 +213,6 @@
};
};
sfpb_mutex: hwmutex {
compatible = "qcom,sfpb-mutex";
syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
#hwlock-cells = <1>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
@ -284,6 +278,40 @@
};
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&funnel_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint = <&etb_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint = <&tpiu_in>;
};
};
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@ -305,9 +333,10 @@
pinctrl-0 = <&ps_hold_default_state>;
};
sfpb_wrapper_mutex: syscon@1200000 {
compatible = "syscon";
reg = <0x01200000 0x8000>;
sfpb_mutex: hwmutex@1200600 {
compatible = "qcom,sfpb-mutex";
reg = <0x01200600 0x100>;
#hwlock-cells = <1>;
};
intc: interrupt-controller@2000000 {
@ -326,6 +355,8 @@
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <27000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
};
@ -1532,39 +1563,6 @@
};
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint = <&etb_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint = <&tpiu_in>;
};
};
};
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&funnel_out>;
};
};
};
};
funnel@1a04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x1a04000 0x1000>;

1
arch/arm/mach-aspeed/Kconfig
View File

@ -2,7 +2,6 @@
menuconfig ARCH_ASPEED
bool "Aspeed BMC architectures"
depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V6 || ARCH_MULTI_V7
select SRAM
select WATCHDOG
select ASPEED_WATCHDOG
select MFD_SYSCON

6
arch/arm64/Kconfig
View File

@ -322,9 +322,9 @@ config ARCH_MMAP_RND_BITS_MAX
default 24 if ARM64_VA_BITS=39
default 27 if ARM64_VA_BITS=42
default 30 if ARM64_VA_BITS=47
default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
default 33 if ARM64_VA_BITS=48
default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES
default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES
default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52)
default 14 if ARM64_64K_PAGES
default 16 if ARM64_16K_PAGES
default 18

1
arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts
View File

@ -124,6 +124,7 @@
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
View File

@ -233,6 +233,7 @@
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
quartz-load-femtofarads = <12500>;
};
};

1
arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts
View File

@ -124,6 +124,7 @@
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
View File

@ -242,6 +242,7 @@
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
quartz-load-femtofarads = <12500>;
};
};

1
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
View File

@ -257,6 +257,7 @@
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
quartz-load-femtofarads = <12500>;
};
};

10
arch/arm64/boot/dts/mediatek/mt6357.dtsi
View File

@ -60,7 +60,6 @@
};
mt6357_vfe28_reg: ldo-vfe28 {
compatible = "regulator-fixed";
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -75,7 +74,6 @@
};
mt6357_vrf18_reg: ldo-vrf18 {
compatible = "regulator-fixed";
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -83,7 +81,6 @@
};
mt6357_vrf12_reg: ldo-vrf12 {
compatible = "regulator-fixed";
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@ -112,7 +109,6 @@
};
mt6357_vcn28_reg: ldo-vcn28 {
compatible = "regulator-fixed";
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -120,7 +116,6 @@
};
mt6357_vcn18_reg: ldo-vcn18 {
compatible = "regulator-fixed";
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -142,7 +137,6 @@
};
mt6357_vcamio_reg: ldo-vcamio18 {
compatible = "regulator-fixed";
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -175,7 +169,6 @@
};
mt6357_vaux18_reg: ldo-vaux18 {
compatible = "regulator-fixed";
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -183,7 +176,6 @@
};
mt6357_vaud28_reg: ldo-vaud28 {
compatible = "regulator-fixed";
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -191,7 +183,6 @@
};
mt6357_vio28_reg: ldo-vio28 {
compatible = "regulator-fixed";
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -199,7 +190,6 @@
};
mt6357_vio18_reg: ldo-vio18 {
compatible = "regulator-fixed";
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;

4
arch/arm64/boot/dts/mediatek/mt6359.dtsi
View File

@ -18,6 +18,8 @@
};
regulators {
compatible = "mediatek,mt6359-regulator";
mt6359_vs1_buck_reg: buck_vs1 {
regulator-name = "vs1";
regulator-min-microvolt = <800000>;
@ -296,7 +298,7 @@
};
};
mt6359rtc: mt6359rtc {
mt6359rtc: rtc {
compatible = "mediatek,mt6358-rtc";
};
};

10
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -280,14 +280,10 @@
};
};
};
};
ports {
port {
dsi_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&dsi_out {
remote-endpoint = <&panel_in>;
};
&gic {

4
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1836,6 +1836,10 @@
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
port {
dsi_out: endpoint { };
};
};
dpi0: dpi@14015000 {

50
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -617,22 +617,6 @@
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8195_POWER_DOMAIN_VDEC1 {
reg = <MT8195_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC_LARB1>;
clock-names = "vdec1-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&topckgen CLK_TOP_CFG_VDO0>,
@ -678,15 +662,25 @@
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "vdec0-0";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VDEC2 {
reg = <MT8195_POWER_DOMAIN_VDEC2>;
clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
clock-names = "vdec2-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
power-domain@MT8195_POWER_DOMAIN_VDEC1 {
reg = <MT8195_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC_LARB1>;
clock-names = "vdec1-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VDEC2 {
reg = <MT8195_POWER_DOMAIN_VDEC2>;
clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
clock-names = "vdec2-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
power-domain@MT8195_POWER_DOMAIN_VENC {
@ -694,7 +688,17 @@
clocks = <&vencsys CLK_VENC_LARB>;
clock-names = "venc0-larb";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {

12
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -621,9 +621,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTB>;
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTB>;
reset-names = "serial";
status = "disabled";
};
@ -633,9 +631,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTD>;
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTD>;
reset-names = "serial";
status = "disabled";
};
@ -645,9 +641,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTE>;
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTE>;
reset-names = "serial";
status = "disabled";
};
@ -657,9 +651,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTF>;
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTF>;
reset-names = "serial";
status = "disabled";
};
@ -1236,9 +1228,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTC>;
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTC>;
reset-names = "serial";
status = "disabled";
};
@ -1248,9 +1238,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTG>;
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTG>;
reset-names = "serial";
status = "disabled";
};

12
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -766,9 +766,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTD>;
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTD>;
reset-names = "serial";
status = "disabled";
};
@ -778,9 +776,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTE>;
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTE>;
reset-names = "serial";
status = "disabled";
};
@ -790,9 +786,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTF>;
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTF>;
reset-names = "serial";
status = "disabled";
};
@ -817,9 +811,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTH>;
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTH>;
reset-names = "serial";
status = "disabled";
};
@ -1616,9 +1608,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTC>;
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTC>;
reset-names = "serial";
status = "disabled";
};
@ -1628,9 +1618,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTG>;
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTG>;
reset-names = "serial";
status = "disabled";
};

1
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@ -11,6 +11,7 @@
rtc0 = "/i2c@7000d000/pmic@3c";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
serial3 = &uartd;
};
chosen {

11
arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
View File

@ -111,6 +111,13 @@
regulator-always-on;
regulator-boot-on;
};
mp5496_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
@ -146,7 +153,7 @@
};
&usb_0_qmpphy {
vdda-pll-supply = <&mp5496_l2>;
vdda-pll-supply = <&mp5496_l5>;
vdda-phy-supply = <&regulator_fixed_0p925>;
status = "okay";
@ -154,7 +161,7 @@
&usb_0_qusbphy {
vdd-supply = <&regulator_fixed_0p925>;
vdda-pll-supply = <&mp5496_l2>;
vdda-pll-supply = <&mp5496_l5>;
vdda-phy-dpdm-supply = <&regulator_fixed_3p3>;
status = "okay";

16
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -1073,7 +1073,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
@ -1092,7 +1092,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
@ -1137,7 +1137,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
@ -1184,7 +1184,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
@ -1231,7 +1231,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
@ -1278,7 +1278,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;
@ -1297,7 +1297,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
@ -1342,7 +1342,7 @@
interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
&qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
&config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
&config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
interconnect-names = "qup-core",
"qup-config";
#address-cells = <1>;

3
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -1131,9 +1131,6 @@
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS1",
"VA DMIC2", "VA MIC BIAS3",
"TX SWR_ADC1", "ADC2_OUTPUT";
wcd-playback-dai-link {

2
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
View File

@ -167,6 +167,7 @@
* BAM DMA interconnects support is in place.
*/
/delete-property/ clocks;
/delete-property/ clock-names;
};
&blsp1_uart2 {
@ -179,6 +180,7 @@
* BAM DMA interconnects support is in place.
*/
/delete-property/ clocks;
/delete-property/ clock-names;
};
&blsp2_uart1 {

3
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
View File

@ -107,6 +107,7 @@
status = "okay";
vdd-supply = <&vreg_l1b_0p925>;
vdda-pll-supply = <&vreg_l10a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
};
@ -404,6 +405,8 @@
&sdhc_2 {
status = "okay";
cd-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vreg_l5b_2p95>;
vqmmc-supply = <&vreg_l2b_2p95>;
};

16
arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts
View File

@ -135,8 +135,6 @@
vdda_sp_sensor:
vdda_ufs1_core:
vdda_ufs2_core:
vdda_usb1_ss_core:
vdda_usb2_ss_core:
vreg_l1a_0p875: ldo1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
@ -157,6 +155,7 @@
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_usb1_ss_core:
vdd_wcss_cx:
vdd_wcss_mx:
vdda_wcss_pll:
@ -383,8 +382,8 @@
};
&sdhc_2 {
pinctrl-names = "default";
pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>;
pinctrl-names = "default";
cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vddpx_2>;
@ -418,16 +417,9 @@
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>;
gpio-reserved-ranges = <27 4>, /* SPI (eSE - embedded Secure Element) */
<85 4>; /* SPI (fingerprint reader) */
sdc2_clk_state: sdc2-clk-state {
pins = "sdc2_clk";

2
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -606,7 +606,7 @@
};
cpu7_opp9: opp-1747200000 {
opp-hz = /bits/ 64 <1708800000>;
opp-hz = /bits/ 64 <1747200000>;
opp-peak-kBps = <5412000 42393600>;
};

6
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1806,11 +1806,11 @@
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <0>;
qcom,num-ees = <4>;
num-channels = <16>;
qcom,controlled-remotely;
iommus = <&apps_smmu 0x594 0x0011>,
<&apps_smmu 0x596 0x0011>;
/* FIXME: Probing BAM DMA causes some abort and system hang */
status = "fail";
};
crypto: crypto@1dfa000 {
@ -1822,8 +1822,6 @@
<&apps_smmu 0x596 0x0011>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "memory";
/* FIXME: dependency BAM DMA is disabled */
status = "disabled";
};
ipa: ipa@1e40000 {

71
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -3605,8 +3605,11 @@
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "mdp0-mem";
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
power-domains = <&dispcc MDSS_GDSC>;
@ -6354,20 +6357,20 @@
trips {
gpu0_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6387,20 +6390,20 @@
trips {
gpu1_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6420,20 +6423,20 @@
trips {
gpu2_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6453,20 +6456,20 @@
trips {
gpu3_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6486,20 +6489,20 @@
trips {
gpu4_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6519,20 +6522,20 @@
trips {
gpu5_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6552,20 +6555,20 @@
trips {
gpu6_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
@ -6585,20 +6588,20 @@
trips {
gpu7_alert0: trip-point0 {
temperature = <85000>;
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
temperature = <110000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <110000>;
hysteresis = <1000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};

2
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
View File

@ -267,6 +267,7 @@
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l13b: ldo13 {
@ -288,6 +289,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l16b: ldo16 {

299
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View File

@ -20,6 +20,7 @@
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@ -4284,6 +4285,8 @@
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dma-coherent;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -6412,8 +6415,8 @@
};
aoss0-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6438,7 +6441,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6464,7 +6467,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6490,7 +6493,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6516,7 +6519,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6542,7 +6545,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6568,7 +6571,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6594,7 +6597,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6620,7 +6623,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6638,8 +6641,8 @@
};
cpuss2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6656,8 +6659,8 @@
};
cpuss2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6674,7 +6677,7 @@
};
mem-critical {
temperature = <125000>;
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
@ -6692,7 +6695,7 @@
};
video-critical {
temperature = <125000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6710,8 +6713,8 @@
};
aoss0-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6736,7 +6739,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6762,7 +6765,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6788,7 +6791,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6814,7 +6817,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6840,7 +6843,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6866,7 +6869,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6892,7 +6895,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6918,7 +6921,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -6936,8 +6939,8 @@
};
cpuss2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6954,8 +6957,8 @@
};
cpuss2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6972,8 +6975,8 @@
};
aoss0-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -6998,7 +7001,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7024,7 +7027,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7050,7 +7053,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7076,7 +7079,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7102,7 +7105,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7128,7 +7131,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7154,7 +7157,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7180,7 +7183,7 @@
};
cpu-critical {
temperature = <110000>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7198,8 +7201,8 @@
};
cpuss2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7216,8 +7219,8 @@
};
cpuss2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7234,8 +7237,8 @@
};
aoss0-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7252,8 +7255,8 @@
};
nsp0-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7270,8 +7273,8 @@
};
nsp1-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7288,8 +7291,8 @@
};
nsp2-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7306,33 +7309,34 @@
};
nsp3-critical {
temperature = <125000>;
hysteresis = <0>;
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-0-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 5>;
cooling-maps {
map0 {
trip = <&gpuss0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss0_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7340,25 +7344,26 @@
};
gpuss-1-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 6>;
cooling-maps {
map0 {
trip = <&gpuss1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss1_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7366,25 +7371,26 @@
};
gpuss-2-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 7>;
cooling-maps {
map0 {
trip = <&gpuss2_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss2_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7392,25 +7398,26 @@
};
gpuss-3-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 8>;
cooling-maps {
map0 {
trip = <&gpuss3_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss3_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7418,25 +7425,26 @@
};
gpuss-4-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 9>;
cooling-maps {
map0 {
trip = <&gpuss4_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss4_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7444,25 +7452,26 @@
};
gpuss-5-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 10>;
cooling-maps {
map0 {
trip = <&gpuss5_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss5_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7470,25 +7479,26 @@
};
gpuss-6-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 11>;
cooling-maps {
map0 {
trip = <&gpuss6_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss6_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7496,25 +7506,26 @@
};
gpuss-7-thermal {
polling-delay-passive = <10>;
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 12>;
cooling-maps {
map0 {
trip = <&gpuss7_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
trip-point0 {
temperature = <85000>;
gpuss7_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
trip-point2 {
temperature = <125000>;
gpu-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@ -7533,7 +7544,7 @@
camera0-critical {
temperature = <115000>;
hysteresis = <0>;
hysteresis = <1000>;
type = "critical";
};
};
@ -7551,7 +7562,7 @@
camera0-critical {
temperature = <115000>;
hysteresis = <0>;
hysteresis = <1000>;
type = "critical";
};
};

2
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso
View File

@ -108,7 +108,7 @@
};
tpu0_pins: tpu0 {
groups = "tpu_to0_a";
groups = "tpu_to0_b";
function = "tpu";
};
};

8
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
View File

@ -284,14 +284,6 @@
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vopb {
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
View File

@ -636,6 +636,7 @@
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&vcc_1v8>;
};
};

5
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
View File

@ -486,9 +486,12 @@
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};

15
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
View File

@ -428,16 +428,15 @@
#clock-cells = <0>;
};
pmu_sram: sram@10f000 {
compatible = "mmio-sram";
reg = <0x0 0x0010f000 0x0 0x100>;
ranges = <0 0x0 0x0010f000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scmi_shmem: sram@0 {
scmi_shmem: shmem@10f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x100>;
reg = <0x0 0x0010f000 0x0 0x100>;
no-map;
};
};

1
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View File

@ -557,6 +557,7 @@
&ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";

3
arch/arm64/configs/defconfig
View File

@ -1534,6 +1534,9 @@ CONFIG_PHY_HISTB_COMBPHY=y
CONFIG_PHY_HISI_INNO_USB2=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PHY_MTK_TPHY=y
CONFIG_PHY_MTK_HDMI=m
CONFIG_PHY_MTK_MIPI_DSI=m
CONFIG_PHY_MTK_DP=m
CONFIG_PHY_QCOM_EDP=m
CONFIG_PHY_QCOM_PCIE2=m
CONFIG_PHY_QCOM_QMP=m

12
arch/arm64/include/asm/esr.h
View File

@ -370,12 +370,14 @@
/*
* ISS values for SME traps
*/
#define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0)
#define ESR_ELx_SME_ISS_SMTC(esr) ((esr) & ESR_ELx_SME_ISS_SMTC_MASK)
#define ESR_ELx_SME_ISS_SME_DISABLED 0
#define ESR_ELx_SME_ISS_ILL 1
#define ESR_ELx_SME_ISS_SM_DISABLED 2
#define ESR_ELx_SME_ISS_ZA_DISABLED 3
#define ESR_ELx_SME_ISS_ZT_DISABLED 4
#define ESR_ELx_SME_ISS_SMTC_SME_DISABLED 0
#define ESR_ELx_SME_ISS_SMTC_ILL 1
#define ESR_ELx_SME_ISS_SMTC_SM_DISABLED 2
#define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED 3
#define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED 4
/* ISS field definitions for MOPS exceptions */
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)

3
arch/arm64/include/asm/fpsimd.h
View File

@ -6,6 +6,7 @@
#define __ASM_FP_H
#include <asm/errno.h>
#include <asm/percpu.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
@ -94,6 +95,8 @@ struct cpu_fp_state {
enum fp_type to_save;
};
DECLARE_PER_CPU(struct cpu_fp_state, fpsimd_last_state);
extern void fpsimd_bind_state_to_cpu(struct cpu_fp_state *fp_state);
extern void fpsimd_flush_task_state(struct task_struct *target);

46
arch/arm64/kernel/entry-common.c
View File

@ -393,20 +393,16 @@ static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
* As per the ABI exit SME streaming mode and clear the SVE state not
* shared with FPSIMD on syscall entry.
*/
static inline void fp_user_discard(void)
static inline void fpsimd_syscall_enter(void)
{
/*
* If SME is active then exit streaming mode. If ZA is active
* then flush the SVE registers but leave userspace access to
* both SVE and SME enabled, otherwise disable SME for the
* task and fall through to disabling SVE too. This means
* that after a syscall we never have any streaming mode
* register state to track, if this changes the KVM code will
* need updating.
*/
/* Ensure PSTATE.SM is clear, but leave PSTATE.ZA as-is. */
if (system_supports_sme())
sme_smstop_sm();
/*
* The CPU is not in streaming mode. If non-streaming SVE is not
* supported, there is no SVE state that needs to be discarded.
*/
if (!system_supports_sve())
return;
@ -416,6 +412,33 @@ static inline void fp_user_discard(void)
sve_vq_minus_one = sve_vq_from_vl(task_get_sve_vl(current)) - 1;
sve_flush_live(true, sve_vq_minus_one);
}
/*
* Any live non-FPSIMD SVE state has been zeroed. Allow
* fpsimd_save_user_state() to lazily discard SVE state until either
* the live state is unbound or fpsimd_syscall_exit() is called.
*/
__this_cpu_write(fpsimd_last_state.to_save, FP_STATE_FPSIMD);
}
static __always_inline void fpsimd_syscall_exit(void)
{
if (!system_supports_sve())
return;
/*
* The current task's user FPSIMD/SVE/SME state is now bound to this
* CPU. The fpsimd_last_state.to_save value is either:
*
* - FP_STATE_FPSIMD, if the state has not been reloaded on this CPU
* since fpsimd_syscall_enter().
*
* - FP_STATE_CURRENT, if the state has been reloaded on this CPU at
* any point.
*
* Reset this to FP_STATE_CURRENT to stop lazy discarding.
*/
__this_cpu_write(fpsimd_last_state.to_save, FP_STATE_CURRENT);
}
UNHANDLED(el1t, 64, sync)
@ -707,10 +730,11 @@ static void noinstr el0_svc(struct pt_regs *regs)
{
enter_from_user_mode(regs);
cortex_a76_erratum_1463225_svc_handler();
fp_user_discard();
fpsimd_syscall_enter();
local_daif_restore(DAIF_PROCCTX);
do_el0_svc(regs);
exit_to_user_mode(regs);
fpsimd_syscall_exit();
}
static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr)

36
arch/arm64/kernel/fpsimd.c
View File

@ -119,7 +119,7 @@
* whatever is in the FPSIMD registers is not saved to memory, but discarded.
*/
static DEFINE_PER_CPU(struct cpu_fp_state, fpsimd_last_state);
DEFINE_PER_CPU(struct cpu_fp_state, fpsimd_last_state);
__ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = {
#ifdef CONFIG_ARM64_SVE
@ -359,9 +359,6 @@ static void task_fpsimd_load(void)
WARN_ON(preemptible());
WARN_ON(test_thread_flag(TIF_KERNEL_FPSTATE));
if (system_supports_fpmr())
write_sysreg_s(current->thread.uw.fpmr, SYS_FPMR);
if (system_supports_sve() || system_supports_sme()) {
switch (current->thread.fp_type) {
case FP_STATE_FPSIMD:
@ -413,6 +410,9 @@ static void task_fpsimd_load(void)
restore_ffr = system_supports_fa64();
}
if (system_supports_fpmr())
write_sysreg_s(current->thread.uw.fpmr, SYS_FPMR);
if (restore_sve_regs) {
WARN_ON_ONCE(current->thread.fp_type != FP_STATE_SVE);
sve_load_state(sve_pffr(&current->thread),
@ -453,12 +453,15 @@ static void fpsimd_save_user_state(void)
*(last->fpmr) = read_sysreg_s(SYS_FPMR);
/*
* If a task is in a syscall the ABI allows us to only
* preserve the state shared with FPSIMD so don't bother
* saving the full SVE state in that case.
* Save SVE state if it is live.
*
* The syscall ABI discards live SVE state at syscall entry. When
* entering a syscall, fpsimd_syscall_enter() sets to_save to
* FP_STATE_FPSIMD to allow the SVE state to be lazily discarded until
* either new SVE state is loaded+bound or fpsimd_syscall_exit() is
* called prior to a return to userspace.
*/
if ((last->to_save == FP_STATE_CURRENT && test_thread_flag(TIF_SVE) &&
!in_syscall(current_pt_regs())) ||
if ((last->to_save == FP_STATE_CURRENT && test_thread_flag(TIF_SVE)) ||
last->to_save == FP_STATE_SVE) {
save_sve_regs = true;
save_ffr = true;
@ -651,7 +654,7 @@ static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst,
* task->thread.uw.fpsimd_state must be up to date before calling this
* function.
*/
static void fpsimd_to_sve(struct task_struct *task)
static inline void fpsimd_to_sve(struct task_struct *task)
{
unsigned int vq;
void *sst = task->thread.sve_state;
@ -675,7 +678,7 @@ static void fpsimd_to_sve(struct task_struct *task)
* bytes of allocated kernel memory.
* task->thread.sve_state must be up to date before calling this function.
*/
static void sve_to_fpsimd(struct task_struct *task)
static inline void sve_to_fpsimd(struct task_struct *task)
{
unsigned int vq, vl;
void const *sst = task->thread.sve_state;
@ -1436,7 +1439,7 @@ void do_sme_acc(unsigned long esr, struct pt_regs *regs)
* If this not a trap due to SME being disabled then something
* is being used in the wrong mode, report as SIGILL.
*/
if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) {
if (ESR_ELx_SME_ISS_SMTC(esr) != ESR_ELx_SME_ISS_SMTC_SME_DISABLED) {
force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
return;
}
@ -1460,6 +1463,8 @@ void do_sme_acc(unsigned long esr, struct pt_regs *regs)
sme_set_vq(vq_minus_one);
fpsimd_bind_task_to_cpu();
} else {
fpsimd_flush_task_state(current);
}
put_cpu_fpsimd_context();
@ -1573,8 +1578,8 @@ void fpsimd_thread_switch(struct task_struct *next)
fpsimd_save_user_state();
if (test_tsk_thread_flag(next, TIF_KERNEL_FPSTATE)) {
fpsimd_load_kernel_state(next);
fpsimd_flush_cpu_state();
fpsimd_load_kernel_state(next);
} else {
/*
* Fix up TIF_FOREIGN_FPSTATE to correctly describe next's
@ -1661,6 +1666,9 @@ void fpsimd_flush_thread(void)
current->thread.svcr = 0;
}
if (system_supports_fpmr())
current->thread.uw.fpmr = 0;
current->thread.fp_type = FP_STATE_FPSIMD;
put_cpu_fpsimd_context();
@ -1801,7 +1809,7 @@ void fpsimd_update_current_state(struct user_fpsimd_state const *state)
get_cpu_fpsimd_context();
current->thread.uw.fpsimd_state = *state;
if (test_thread_flag(TIF_SVE))
if (current->thread.fp_type == FP_STATE_SVE)
fpsimd_to_sve(current);
task_fpsimd_load();

21
arch/arm64/xen/hypercall.S
View File

@ -83,7 +83,26 @@ HYPERCALL3(vcpu_op);
HYPERCALL1(platform_op_raw);
HYPERCALL2(multicall);
HYPERCALL2(vm_assist);
HYPERCALL3(dm_op);
SYM_FUNC_START(HYPERVISOR_dm_op)
mov x16, #__HYPERVISOR_dm_op; \
/*
* dm_op hypercalls are issued by the userspace. The kernel needs to
* enable access to TTBR0_EL1 as the hypervisor would issue stage 1
* translations to user memory via AT instructions. Since AT
* instructions are not affected by the PAN bit (ARMv8.1), we only
* need the explicit uaccess_enable/disable if the TTBR0 PAN emulation
* is enabled (it implies that hardware UAO and PAN disabled).
*/
uaccess_ttbr0_enable x6, x7, x8
hvc XEN_IMM
/*
* Disable userspace access from kernel once the hyp call completed.
*/
uaccess_ttbr0_disable x6, x7
ret
SYM_FUNC_END(HYPERVISOR_dm_op);
SYM_FUNC_START(privcmd_call)
mov x16, x0

2
arch/m68k/mac/config.c
View File

@ -793,7 +793,7 @@ static void __init mac_identify(void)
}
macintosh_config = mac_data_table;
for (m = macintosh_config; m->ident != -1; m++) {
for (m = &mac_data_table[1]; m->ident != -1; m++) {
if (m->ident == model) {
macintosh_config = m;
break;

1
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
View File

@ -29,6 +29,7 @@
compatible = "loongson,pch-msi-1.0";
reg = <0 0x2ff00000 0 0x8>;
interrupt-controller;
#interrupt-cells = <1>;
msi-controller;
loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <64>;

2
arch/powerpc/kernel/Makefile
View File

@ -162,7 +162,7 @@ endif
obj64-$(CONFIG_PPC_TRANSACTIONAL_MEM) += tm.o
ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC_CORE)(CONFIG_PPC_BOOK3S),)
ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC_CORE)$(CONFIG_PPC_BOOK3S),)
obj-y += ppc_save_regs.o
endif

5
arch/powerpc/kexec/crash.c
View File

@ -359,7 +359,10 @@ void default_machine_crash_shutdown(struct pt_regs *regs)
if (TRAP(regs) == INTERRUPT_SYSTEM_RESET)
is_via_system_reset = 1;
crash_smp_send_stop();
if (IS_ENABLED(CONFIG_SMP))
crash_smp_send_stop();
else
crash_kexec_prepare();
crash_save_cpu(regs, crashing_cpu);

9
arch/powerpc/platforms/book3s/vas-api.c
View File

@ -521,6 +521,15 @@ static int coproc_mmap(struct file *fp, struct vm_area_struct *vma)
return -EINVAL;
}
/*
* Map complete page to the paste address. So the user
* space should pass 0ULL to the offset parameter.
*/
if (vma->vm_pgoff) {
pr_debug("Page offset unsupported to map paste address\n");
return -EINVAL;
}
/* Ensure instance has an open send window */
if (!txwin) {
pr_err("No send window open?\n");

8
arch/powerpc/platforms/powernv/memtrace.c
View File

@ -48,11 +48,15 @@ static ssize_t memtrace_read(struct file *filp, char __user *ubuf,
static int memtrace_mmap(struct file *filp, struct vm_area_struct *vma)
{
struct memtrace_entry *ent = filp->private_data;
unsigned long ent_nrpages = ent->size >> PAGE_SHIFT;
unsigned long vma_nrpages = vma_pages(vma);
if (ent->size < vma->vm_end - vma->vm_start)
/* The requested page offset should be within object's page count */
if (vma->vm_pgoff >= ent_nrpages)
return -EINVAL;
if (vma->vm_pgoff << PAGE_SHIFT >= ent->size)
/* The requested mapping range should remain within the bounds */
if (vma_nrpages > ent_nrpages - vma->vm_pgoff)
return -EINVAL;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

2
arch/powerpc/platforms/pseries/iommu.c
View File

@ -197,7 +197,7 @@ static void tce_iommu_userspace_view_free(struct iommu_table *tbl)
static void tce_free_pSeries(struct iommu_table *tbl)
{
if (!tbl->it_userspace)
if (tbl->it_userspace)
tce_iommu_userspace_view_free(tbl);
}

4
arch/riscv/kernel/traps_misaligned.c
View File

@ -429,7 +429,7 @@ int handle_misaligned_load(struct pt_regs *regs)
val.data_u64 = 0;
if (user_mode(regs)) {
if (copy_from_user(&val, (u8 __user *)addr, len))
if (copy_from_user_nofault(&val, (u8 __user *)addr, len))
return -1;
} else {
memcpy(&val, (u8 *)addr, len);
@ -530,7 +530,7 @@ int handle_misaligned_store(struct pt_regs *regs)
return -EOPNOTSUPP;
if (user_mode(regs)) {
if (copy_to_user((u8 __user *)addr, &val, len))
if (copy_to_user_nofault((u8 __user *)addr, &val, len))
return -1;
} else {
memcpy((u8 *)addr, &val, len);

4
arch/riscv/kvm/vcpu_sbi.c
View File

@ -139,9 +139,9 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
struct kvm_vcpu *tmp;
kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
spin_lock(&vcpu->arch.mp_state_lock);
spin_lock(&tmp->arch.mp_state_lock);
WRITE_ONCE(tmp->arch.mp_state.mp_state, KVM_MP_STATE_STOPPED);
spin_unlock(&vcpu->arch.mp_state_lock);
spin_unlock(&tmp->arch.mp_state_lock);
}
kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_SLEEP);

12
arch/s390/net/bpf_jit_comp.c
View File

@ -605,17 +605,15 @@ static void bpf_jit_prologue(struct bpf_jit *jit, struct bpf_prog *fp,
}
/* Setup stack and backchain */
if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) {
if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
/* lgr %w1,%r15 (backchain) */
EMIT4(0xb9040000, REG_W1, REG_15);
/* lgr %w1,%r15 (backchain) */
EMIT4(0xb9040000, REG_W1, REG_15);
/* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
/* aghi %r15,-STK_OFF */
EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
/* stg %w1,152(%r15) (backchain) */
EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
REG_15, 152);
/* stg %w1,152(%r15) (backchain) */
EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
REG_15, 152);
}
}

36
arch/x86/events/amd/uncore.c
View File

@ -38,7 +38,6 @@ struct amd_uncore_ctx {
int refcnt;
int cpu;
struct perf_event **events;
struct hlist_node node;
};
struct amd_uncore_pmu {
@ -890,6 +889,39 @@ static void amd_uncore_umc_start(struct perf_event *event, int flags)
perf_event_update_userpage(event);
}
static void amd_uncore_umc_read(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
u64 prev, new, shift;
s64 delta;
shift = COUNTER_SHIFT + 1;
prev = local64_read(&hwc->prev_count);
/*
* UMC counters do not have RDPMC assignments. Read counts directly
* from the corresponding PERF_CTR.
*/
rdmsrl(hwc->event_base, new);
/*
* Unlike the other uncore counters, UMC counters saturate and set the
* Overflow bit (bit 48) on overflow. Since they do not roll over,
* proactively reset the corresponding PERF_CTR when bit 47 is set so
* that the counter never gets a chance to saturate.
*/
if (new & BIT_ULL(63 - COUNTER_SHIFT)) {
wrmsrl(hwc->event_base, 0);
local64_set(&hwc->prev_count, 0);
} else {
local64_set(&hwc->prev_count, new);
}
delta = (new << shift) - (prev << shift);
delta >>= shift;
local64_add(delta, &event->count);
}
static
void amd_uncore_umc_ctx_scan(struct amd_uncore *uncore, unsigned int cpu)
{
@ -967,7 +999,7 @@ int amd_uncore_umc_ctx_init(struct amd_uncore *uncore, unsigned int cpu)
.del = amd_uncore_del,
.start = amd_uncore_umc_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
.read = amd_uncore_umc_read,
.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
.module = THIS_MODULE,
};

9
arch/x86/include/asm/mwait.h
View File

@ -117,13 +117,10 @@ static __always_inline void __sti_mwait(unsigned long eax, unsigned long ecx)
static __always_inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
{
if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {
if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
mb();
clflush((void *)&current_thread_info()->flags);
mb();
}
const void *addr = &current_thread_info()->flags;
__monitor((void *)&current_thread_info()->flags, 0, 0);
alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr));
__monitor(addr, 0, 0);
if (!need_resched()) {
if (ecx & 1) {

22
arch/x86/include/asm/sighandling.h
View File

@ -24,4 +24,26 @@ int ia32_setup_rt_frame(struct ksignal *ksig, struct pt_regs *regs);
int x64_setup_rt_frame(struct ksignal *ksig, struct pt_regs *regs);
int x32_setup_rt_frame(struct ksignal *ksig, struct pt_regs *regs);
/*
* To prevent immediate repeat of single step trap on return from SIGTRAP
* handler if the trap flag (TF) is set without an external debugger attached,
* clear the software event flag in the augmented SS, ensuring no single-step
* trap is pending upon ERETU completion.
*
* Note, this function should be called in sigreturn() before the original
* state is restored to make sure the TF is read from the entry frame.
*/
static __always_inline void prevent_single_step_upon_eretu(struct pt_regs *regs)
{
/*
* If the trap flag (TF) is set, i.e., the sigreturn() SYSCALL instruction
* is being single-stepped, do not clear the software event flag in the
* augmented SS, thus a debugger won't skip over the following instruction.
*/
#ifdef CONFIG_X86_FRED
if (!(regs->flags & X86_EFLAGS_TF))
regs->fred_ss.swevent = 0;
#endif
}
#endif /* _ASM_X86_SIGHANDLING_H */

17
arch/x86/kernel/cpu/common.c
View File

@ -1007,17 +1007,18 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_capability[CPUID_D_1_EAX] = eax;
}
/* AMD-defined flags: level 0x80000001 */
/*
* Check if extended CPUID leaves are implemented: Max extended
* CPUID leaf must be in the 0x80000001-0x8000ffff range.
*/
eax = cpuid_eax(0x80000000);
c->extended_cpuid_level = eax;
c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0;
if ((eax & 0xffff0000) == 0x80000000) {
if (eax >= 0x80000001) {
cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
if (c->extended_cpuid_level >= 0x80000001) {
cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
c->x86_capability[CPUID_8000_0001_ECX] = ecx;
c->x86_capability[CPUID_8000_0001_EDX] = edx;
}
c->x86_capability[CPUID_8000_0001_ECX] = ecx;
c->x86_capability[CPUID_8000_0001_EDX] = edx;
}
if (c->extended_cpuid_level >= 0x80000007) {

2
arch/x86/kernel/cpu/microcode/core.c
View File

@ -696,6 +696,8 @@ static int load_late_locked(void)
return load_late_stop_cpus(true);
case UCODE_NFOUND:
return -ENOENT;
case UCODE_OK:
return 0;
default:
return -EBADFD;
}

2
arch/x86/kernel/cpu/mtrr/generic.c
View File

@ -591,7 +591,7 @@ static void get_fixed_ranges(mtrr_type *frs)
void mtrr_save_fixed_ranges(void *info)
{
if (boot_cpu_has(X86_FEATURE_MTRR))
if (mtrr_state.have_fixed)
get_fixed_ranges(mtrr_state.fixed_ranges);
}

13
arch/x86/kernel/ioport.c
View File

@ -33,8 +33,9 @@ void io_bitmap_share(struct task_struct *tsk)
set_tsk_thread_flag(tsk, TIF_IO_BITMAP);
}
static void task_update_io_bitmap(struct task_struct *tsk)
static void task_update_io_bitmap(void)
{
struct task_struct *tsk = current;
struct thread_struct *t = &tsk->thread;
if (t->iopl_emul == 3 || t->io_bitmap) {
@ -54,7 +55,12 @@ void io_bitmap_exit(struct task_struct *tsk)
struct io_bitmap *iobm = tsk->thread.io_bitmap;
tsk->thread.io_bitmap = NULL;
task_update_io_bitmap(tsk);
/*
* Don't touch the TSS when invoked on a failed fork(). TSS
* reflects the state of @current and not the state of @tsk.
*/
if (tsk == current)
task_update_io_bitmap();
if (iobm && refcount_dec_and_test(&iobm->refcnt))
kfree(iobm);
}
@ -192,8 +198,7 @@ SYSCALL_DEFINE1(iopl, unsigned int, level)
}
t->iopl_emul = level;
task_update_io_bitmap(current);
task_update_io_bitmap();
return 0;
}

2
arch/x86/kernel/irq.c
View File

@ -414,7 +414,7 @@ static __always_inline bool handle_pending_pir(u64 *pir, struct pt_regs *regs)
bool handled = false;
for (i = 0; i < 4; i++)
pir_copy[i] = pir[i];
pir_copy[i] = READ_ONCE(pir[i]);
for (i = 0; i < 4; i++) {
if (!pir_copy[i])

15
arch/x86/kernel/process.c
View File

@ -180,6 +180,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
frame->ret_addr = (unsigned long) ret_from_fork_asm;
p->thread.sp = (unsigned long) fork_frame;
p->thread.io_bitmap = NULL;
clear_tsk_thread_flag(p, TIF_IO_BITMAP);
p->thread.iopl_warn = 0;
memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
@ -468,6 +469,11 @@ void native_tss_update_io_bitmap(void)
} else {
struct io_bitmap *iobm = t->io_bitmap;
if (WARN_ON_ONCE(!iobm)) {
clear_thread_flag(TIF_IO_BITMAP);
native_tss_invalidate_io_bitmap();
}
/*
* Only copy bitmap data when the sequence number differs. The
* update time is accounted to the incoming task.
@ -906,13 +912,10 @@ static __init bool prefer_mwait_c1_over_halt(void)
static __cpuidle void mwait_idle(void)
{
if (!current_set_polling_and_test()) {
if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
mb(); /* quirk */
clflush((void *)&current_thread_info()->flags);
mb(); /* quirk */
}
const void *addr = &current_thread_info()->flags;
__monitor((void *)&current_thread_info()->flags, 0, 0);
alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr));
__monitor(addr, 0, 0);
if (!need_resched()) {
__sti_mwait(0, 0);
raw_local_irq_disable();

4
arch/x86/kernel/signal_32.c
View File

@ -152,6 +152,8 @@ SYSCALL32_DEFINE0(sigreturn)
struct sigframe_ia32 __user *frame = (struct sigframe_ia32 __user *)(regs->sp-8);
sigset_t set;
prevent_single_step_upon_eretu(regs);
if (!access_ok(frame, sizeof(*frame)))
goto badframe;
if (__get_user(set.sig[0], &frame->sc.oldmask)
@ -175,6 +177,8 @@ SYSCALL32_DEFINE0(rt_sigreturn)
struct rt_sigframe_ia32 __user *frame;
sigset_t set;
prevent_single_step_upon_eretu(regs);
frame = (struct rt_sigframe_ia32 __user *)(regs->sp - 4);
if (!access_ok(frame, sizeof(*frame)))

4
arch/x86/kernel/signal_64.c
View File

@ -250,6 +250,8 @@ SYSCALL_DEFINE0(rt_sigreturn)
sigset_t set;
unsigned long uc_flags;
prevent_single_step_upon_eretu(regs);
frame = (struct rt_sigframe __user *)(regs->sp - sizeof(long));
if (!access_ok(frame, sizeof(*frame)))
goto badframe;
@ -366,6 +368,8 @@ COMPAT_SYSCALL_DEFINE0(x32_rt_sigreturn)
sigset_t set;
unsigned long uc_flags;
prevent_single_step_upon_eretu(regs);
frame = (struct rt_sigframe_x32 __user *)(regs->sp - 8);
if (!access_ok(frame, sizeof(*frame)))

50
arch/x86/lib/x86-opcode-map.txt
View File

@ -35,7 +35,7 @@
# - (!F3) : the last prefix is not 0xF3 (including non-last prefix case)
# - (66&F2): Both 0x66 and 0xF2 prefixes are specified.
#
# REX2 Prefix
# REX2 Prefix Superscripts
# - (!REX2): REX2 is not allowed
# - (REX2): REX2 variant e.g. JMPABS
@ -286,10 +286,10 @@ df: ESC
# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
# to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD.
e0: LOOPNE/LOOPNZ Jb (f64) (!REX2)
e1: LOOPE/LOOPZ Jb (f64) (!REX2)
e2: LOOP Jb (f64) (!REX2)
e3: JrCXZ Jb (f64) (!REX2)
e0: LOOPNE/LOOPNZ Jb (f64),(!REX2)
e1: LOOPE/LOOPZ Jb (f64),(!REX2)
e2: LOOP Jb (f64),(!REX2)
e3: JrCXZ Jb (f64),(!REX2)
e4: IN AL,Ib (!REX2)
e5: IN eAX,Ib (!REX2)
e6: OUT Ib,AL (!REX2)
@ -298,10 +298,10 @@ e7: OUT Ib,eAX (!REX2)
# in "near" jumps and calls is 16-bit. For CALL,
# push of return address is 16-bit wide, RSP is decremented by 2
# but is not truncated to 16 bits, unlike RIP.
e8: CALL Jz (f64) (!REX2)
e9: JMP-near Jz (f64) (!REX2)
ea: JMP-far Ap (i64) (!REX2)
eb: JMP-short Jb (f64) (!REX2)
e8: CALL Jz (f64),(!REX2)
e9: JMP-near Jz (f64),(!REX2)
ea: JMP-far Ap (i64),(!REX2)
eb: JMP-short Jb (f64),(!REX2)
ec: IN AL,DX (!REX2)
ed: IN eAX,DX (!REX2)
ee: OUT DX,AL (!REX2)
@ -478,22 +478,22 @@ AVXcode: 1
7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev)
# 0x0f 0x80-0x8f
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
80: JO Jz (f64) (!REX2)
81: JNO Jz (f64) (!REX2)
82: JB/JC/JNAE Jz (f64) (!REX2)
83: JAE/JNB/JNC Jz (f64) (!REX2)
84: JE/JZ Jz (f64) (!REX2)
85: JNE/JNZ Jz (f64) (!REX2)
86: JBE/JNA Jz (f64) (!REX2)
87: JA/JNBE Jz (f64) (!REX2)
88: JS Jz (f64) (!REX2)
89: JNS Jz (f64) (!REX2)
8a: JP/JPE Jz (f64) (!REX2)
8b: JNP/JPO Jz (f64) (!REX2)
8c: JL/JNGE Jz (f64) (!REX2)
8d: JNL/JGE Jz (f64) (!REX2)
8e: JLE/JNG Jz (f64) (!REX2)
8f: JNLE/JG Jz (f64) (!REX2)
80: JO Jz (f64),(!REX2)
81: JNO Jz (f64),(!REX2)
82: JB/JC/JNAE Jz (f64),(!REX2)
83: JAE/JNB/JNC Jz (f64),(!REX2)
84: JE/JZ Jz (f64),(!REX2)
85: JNE/JNZ Jz (f64),(!REX2)
86: JBE/JNA Jz (f64),(!REX2)
87: JA/JNBE Jz (f64),(!REX2)
88: JS Jz (f64),(!REX2)
89: JNS Jz (f64),(!REX2)
8a: JP/JPE Jz (f64),(!REX2)
8b: JNP/JPO Jz (f64),(!REX2)
8c: JL/JNGE Jz (f64),(!REX2)
8d: JNL/JGE Jz (f64),(!REX2)
8e: JLE/JNG Jz (f64),(!REX2)
8f: JNLE/JG Jz (f64),(!REX2)
# 0x0f 0x90-0x9f
90: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66)
91: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66)

7
block/blk-zoned.c
View File

@ -1321,7 +1321,6 @@ again:
spin_unlock_irqrestore(&zwplug->lock, flags);
bdev = bio->bi_bdev;
submit_bio_noacct_nocheck(bio);
/*
* blk-mq devices will reuse the extra reference on the request queue
@ -1329,8 +1328,12 @@ again:
* path for BIO-based devices will not do that. So drop this extra
* reference here.
*/
if (bdev_test_flag(bdev, BD_HAS_SUBMIT_BIO))
if (bdev_test_flag(bdev, BD_HAS_SUBMIT_BIO)) {
bdev->bd_disk->fops->submit_bio(bio);
blk_queue_exit(bdev->bd_disk->queue);
} else {
blk_mq_submit_bio(bio);
}
put_zwplug:
/* Drop the reference we took in disk_zone_wplug_schedule_bio_work(). */

3
block/elevator.c
View File

@ -752,7 +752,6 @@ ssize_t elv_iosched_store(struct gendisk *disk, const char *buf,
ssize_t elv_iosched_show(struct gendisk *disk, char *name)
{
struct request_queue *q = disk->queue;
struct elevator_queue *eq = q->elevator;
struct elevator_type *cur = NULL, *e;
int len = 0;
@ -763,7 +762,7 @@ ssize_t elv_iosched_show(struct gendisk *disk, char *name)
len += sprintf(name+len, "[none] ");
} else {
len += sprintf(name+len, "none ");
cur = eq->type;
cur = q->elevator->type;
}
spin_lock(&elv_list_lock);

13
crypto/api.c
View File

@ -220,10 +220,19 @@ again:
if (crypto_is_test_larval(larval))
crypto_larval_kill(larval);
alg = ERR_PTR(-ETIMEDOUT);
} else if (!alg) {
} else if (!alg || PTR_ERR(alg) == -EEXIST) {
int err = alg ? -EEXIST : -EAGAIN;
/*
* EEXIST is expected because two probes can be scheduled
* at the same time with one using alg_name and the other
* using driver_name. Do a re-lookup but do not retry in
* case we hit a quirk like gcm_base(ctr(aes),...) which
* will never match.
*/
alg = &larval->alg;
alg = crypto_alg_lookup(alg->cra_name, type, mask) ?:
ERR_PTR(-EAGAIN);
ERR_PTR(err);
} else if (IS_ERR(alg))
;
else if (crypto_is_test_larval(larval) &&

4
crypto/lrw.c
View File

@ -322,7 +322,7 @@ static int lrw_create(struct crypto_template *tmpl, struct rtattr **tb)
err = crypto_grab_skcipher(spawn, skcipher_crypto_instance(inst),
cipher_name, 0, mask);
if (err == -ENOENT) {
if (err == -ENOENT && memcmp(cipher_name, "ecb(", 4)) {
err = -ENAMETOOLONG;
if (snprintf(ecb_name, CRYPTO_MAX_ALG_NAME, "ecb(%s)",
cipher_name) >= CRYPTO_MAX_ALG_NAME)
@ -356,7 +356,7 @@ static int lrw_create(struct crypto_template *tmpl, struct rtattr **tb)
/* Alas we screwed up the naming so we have to mangle the
* cipher name.
*/
if (!strncmp(cipher_name, "ecb(", 4)) {
if (!memcmp(cipher_name, "ecb(", 4)) {
int len;
len = strscpy(ecb_name, cipher_name + 4, sizeof(ecb_name));

4
crypto/xts.c
View File

@ -363,7 +363,7 @@ static int xts_create(struct crypto_template *tmpl, struct rtattr **tb)
err = crypto_grab_skcipher(&ctx->spawn, skcipher_crypto_instance(inst),
cipher_name, 0, mask);
if (err == -ENOENT) {
if (err == -ENOENT && memcmp(cipher_name, "ecb(", 4)) {
err = -ENAMETOOLONG;
if (snprintf(name, CRYPTO_MAX_ALG_NAME, "ecb(%s)",
cipher_name) >= CRYPTO_MAX_ALG_NAME)
@ -397,7 +397,7 @@ static int xts_create(struct crypto_template *tmpl, struct rtattr **tb)
/* Alas we screwed up the naming so we have to mangle the
* cipher name.
*/
if (!strncmp(cipher_name, "ecb(", 4)) {
if (!memcmp(cipher_name, "ecb(", 4)) {
int len;
len = strscpy(name, cipher_name + 4, sizeof(name));

6
drivers/acpi/acpica/exserial.c
View File

@ -201,6 +201,12 @@ acpi_ex_read_serial_bus(union acpi_operand_object *obj_desc,
function = ACPI_READ;
break;
case ACPI_ADR_SPACE_FIXED_HARDWARE:
buffer_length = ACPI_FFH_INPUT_BUFFER_SIZE;
function = ACPI_READ;
break;
default:
return_ACPI_STATUS(AE_AML_INVALID_SPACE_ID);
}

1
drivers/acpi/apei/Kconfig
View File

@ -23,6 +23,7 @@ config ACPI_APEI_GHES
select ACPI_HED
select IRQ_WORK
select GENERIC_ALLOCATOR
select ARM_SDE_INTERFACE if ARM64
help
Generic Hardware Error Source provides a way to report
platform hardware errors (such as that from chipset). It

2
drivers/acpi/apei/ghes.c
View File

@ -1612,7 +1612,7 @@ void __init acpi_ghes_init(void)
{
int rc;
sdei_init();
acpi_sdei_init();
if (acpi_disabled)
return;

2
drivers/acpi/cppc_acpi.c
View File

@ -463,7 +463,7 @@ bool cppc_allow_fast_switch(void)
struct cpc_desc *cpc_ptr;
int cpu;
for_each_possible_cpu(cpu) {
for_each_present_cpu(cpu) {
cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&

1
drivers/acpi/osi.c
View File

@ -42,7 +42,6 @@ static struct acpi_osi_entry
osi_setup_entries[OSI_STRING_ENTRIES_MAX] __initdata = {
{"Module Device", true},
{"Processor Device", true},
{"3.0 _SCP Extensions", true},
{"Processor Aggregator Device", true},
};

2
drivers/acpi/resource.c
View File

@ -534,7 +534,7 @@ static const struct dmi_system_id irq1_level_low_skip_override[] = {
*/
static const struct dmi_system_id irq1_edge_low_force_override[] = {
{
/* MECHREV Jiaolong17KS Series GM7XG0M */
/* MECHREVO Jiaolong17KS Series GM7XG0M */
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "GM7XG0M"),
},

3
drivers/base/power/main.c
View File

@ -916,6 +916,8 @@ static void device_resume(struct device *dev, pm_message_t state, bool async)
if (!dev->power.is_suspended)
goto Complete;
dev->power.is_suspended = false;
if (dev->power.direct_complete) {
/* Match the pm_runtime_disable() in __device_suspend(). */
pm_runtime_enable(dev);
@ -971,7 +973,6 @@ static void device_resume(struct device *dev, pm_message_t state, bool async)
End:
error = dpm_run_callback(callback, dev, state, info);
dev->power.is_suspended = false;
device_unlock(dev);
dpm_watchdog_clear(&wd);

11
drivers/block/brd.c
View File

@ -224,19 +224,22 @@ out:
static void brd_do_discard(struct brd_device *brd, sector_t sector, u32 size)
{
sector_t aligned_sector = (sector + PAGE_SECTORS) & ~PAGE_SECTORS;
sector_t aligned_sector = round_up(sector, PAGE_SECTORS);
sector_t aligned_end = round_down(
sector + (size >> SECTOR_SHIFT), PAGE_SECTORS);
struct page *page;
size -= (aligned_sector - sector) * SECTOR_SIZE;
if (aligned_end <= aligned_sector)
return;
xa_lock(&brd->brd_pages);
while (size >= PAGE_SIZE && aligned_sector < rd_size * 2) {
while (aligned_sector < aligned_end && aligned_sector < rd_size * 2) {
page = __xa_erase(&brd->brd_pages, aligned_sector >> PAGE_SECTORS_SHIFT);
if (page) {
__free_page(page);
brd->brd_nr_pages--;
}
aligned_sector += PAGE_SECTORS;
size -= PAGE_SIZE;
}
xa_unlock(&brd->brd_pages);
}

8
drivers/block/loop.c
View File

@ -323,11 +323,14 @@ end_io:
static void lo_rw_aio_do_completion(struct loop_cmd *cmd)
{
struct request *rq = blk_mq_rq_from_pdu(cmd);
struct loop_device *lo = rq->q->queuedata;
if (!atomic_dec_and_test(&cmd->ref))
return;
kfree(cmd->bvec);
cmd->bvec = NULL;
if (req_op(rq) == REQ_OP_WRITE)
file_end_write(lo->lo_backing_file);
if (likely(!blk_should_fake_timeout(rq->q)))
blk_mq_complete_request(rq);
}
@ -402,9 +405,10 @@ static int lo_rw_aio(struct loop_device *lo, struct loop_cmd *cmd,
cmd->iocb.ki_flags = 0;
}
if (rw == ITER_SOURCE)
if (rw == ITER_SOURCE) {
file_start_write(lo->lo_backing_file);
ret = file->f_op->write_iter(&cmd->iocb, &iter);
else
} else
ret = file->f_op->read_iter(&cmd->iocb, &iter);
lo_rw_aio_do_completion(cmd);

10
drivers/bluetooth/btintel.c
View File

@ -2705,7 +2705,7 @@ static int btintel_uefi_get_dsbr(u32 *dsbr_var)
} __packed data;
efi_status_t status;
unsigned long data_size = 0;
unsigned long data_size = sizeof(data);
efi_guid_t guid = EFI_GUID(0xe65d8884, 0xd4af, 0x4b20, 0x8d, 0x03,
0x77, 0x2e, 0xcc, 0x3d, 0xa5, 0x31);
@ -2715,16 +2715,10 @@ static int btintel_uefi_get_dsbr(u32 *dsbr_var)
if (!efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE))
return -EOPNOTSUPP;
status = efi.get_variable(BTINTEL_EFI_DSBR, &guid, NULL, &data_size,
NULL);
if (status != EFI_BUFFER_TOO_SMALL || !data_size)
return -EIO;
status = efi.get_variable(BTINTEL_EFI_DSBR, &guid, NULL, &data_size,
&data);
if (status != EFI_SUCCESS)
if (status != EFI_SUCCESS || data_size != sizeof(data))
return -ENXIO;
*dsbr_var = data.dsbr;

31
drivers/bluetooth/btintel_pcie.c
View File

@ -231,8 +231,13 @@ static int btintel_pcie_submit_rx(struct btintel_pcie_data *data)
static int btintel_pcie_start_rx(struct btintel_pcie_data *data)
{
int i, ret;
struct rxq *rxq = &data->rxq;
for (i = 0; i < BTINTEL_PCIE_RX_MAX_QUEUE; i++) {
/* Post (BTINTEL_PCIE_RX_DESCS_COUNT - 3) buffers to overcome the
* hardware issues leading to race condition at the firmware.
*/
for (i = 0; i < rxq->count - 3; i++) {
ret = btintel_pcie_submit_rx(data);
if (ret)
return ret;
@ -1147,8 +1152,8 @@ static int btintel_pcie_alloc(struct btintel_pcie_data *data)
* + size of index * Number of queues(2) * type of index array(4)
* + size of context information
*/
total = (sizeof(struct tfd) + sizeof(struct urbd0) + sizeof(struct frbd)
+ sizeof(struct urbd1)) * BTINTEL_DESCS_COUNT;
total = (sizeof(struct tfd) + sizeof(struct urbd0)) * BTINTEL_PCIE_TX_DESCS_COUNT;
total += (sizeof(struct frbd) + sizeof(struct urbd1)) * BTINTEL_PCIE_RX_DESCS_COUNT;
/* Add the sum of size of index array and size of ci struct */
total += (sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 4) + sizeof(struct ctx_info);
@ -1173,36 +1178,36 @@ static int btintel_pcie_alloc(struct btintel_pcie_data *data)
data->dma_v_addr = v_addr;
/* Setup descriptor count */
data->txq.count = BTINTEL_DESCS_COUNT;
data->rxq.count = BTINTEL_DESCS_COUNT;
data->txq.count = BTINTEL_PCIE_TX_DESCS_COUNT;
data->rxq.count = BTINTEL_PCIE_RX_DESCS_COUNT;
/* Setup tfds */
data->txq.tfds_p_addr = p_addr;
data->txq.tfds = v_addr;
p_addr += (sizeof(struct tfd) * BTINTEL_DESCS_COUNT);
v_addr += (sizeof(struct tfd) * BTINTEL_DESCS_COUNT);
p_addr += (sizeof(struct tfd) * BTINTEL_PCIE_TX_DESCS_COUNT);
v_addr += (sizeof(struct tfd) * BTINTEL_PCIE_TX_DESCS_COUNT);
/* Setup urbd0 */
data->txq.urbd0s_p_addr = p_addr;
data->txq.urbd0s = v_addr;
p_addr += (sizeof(struct urbd0) * BTINTEL_DESCS_COUNT);
v_addr += (sizeof(struct urbd0) * BTINTEL_DESCS_COUNT);
p_addr += (sizeof(struct urbd0) * BTINTEL_PCIE_TX_DESCS_COUNT);
v_addr += (sizeof(struct urbd0) * BTINTEL_PCIE_TX_DESCS_COUNT);
/* Setup FRBD*/
data->rxq.frbds_p_addr = p_addr;
data->rxq.frbds = v_addr;
p_addr += (sizeof(struct frbd) * BTINTEL_DESCS_COUNT);
v_addr += (sizeof(struct frbd) * BTINTEL_DESCS_COUNT);
p_addr += (sizeof(struct frbd) * BTINTEL_PCIE_RX_DESCS_COUNT);
v_addr += (sizeof(struct frbd) * BTINTEL_PCIE_RX_DESCS_COUNT);
/* Setup urbd1 */
data->rxq.urbd1s_p_addr = p_addr;
data->rxq.urbd1s = v_addr;
p_addr += (sizeof(struct urbd1) * BTINTEL_DESCS_COUNT);
v_addr += (sizeof(struct urbd1) * BTINTEL_DESCS_COUNT);
p_addr += (sizeof(struct urbd1) * BTINTEL_PCIE_RX_DESCS_COUNT);
v_addr += (sizeof(struct urbd1) * BTINTEL_PCIE_RX_DESCS_COUNT);
/* Setup data buffers for txq */
err = btintel_pcie_setup_txq_bufs(data, &data->txq);

10
drivers/bluetooth/btintel_pcie.h
View File

@ -81,8 +81,11 @@ enum {
/* Default interrupt timeout in msec */
#define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000
/* The number of descriptors in TX/RX queues */
#define BTINTEL_DESCS_COUNT 16
/* The number of descriptors in TX queues */
#define BTINTEL_PCIE_TX_DESCS_COUNT 32
/* The number of descriptors in RX queues */
#define BTINTEL_PCIE_RX_DESCS_COUNT 64
/* Number of Queue for TX and RX
* It indicates the index of the IA(Index Array)
@ -104,9 +107,6 @@ enum {
/* Doorbell vector for TFD */
#define BTINTEL_PCIE_TX_DB_VEC 0
/* Number of pending RX requests for downlink */
#define BTINTEL_PCIE_RX_MAX_QUEUE 6
/* Doorbell vector for FRBD */
#define BTINTEL_PCIE_RX_DB_VEC 513

6
drivers/bus/fsl-mc/fsl-mc-bus.c
View File

@ -905,8 +905,10 @@ int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc,
error_cleanup_dev:
kfree(mc_dev->regions);
kfree(mc_bus);
kfree(mc_dev);
if (mc_bus)
kfree(mc_bus);
else
kfree(mc_dev);
return error;
}

2
drivers/clk/bcm/clk-raspberrypi.c
View File

@ -287,6 +287,8 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi,
init.name = devm_kasprintf(rpi->dev, GFP_KERNEL,
"fw-clk-%s",
rpi_firmware_clk_names[id]);
if (!init.name)
return ERR_PTR(-ENOMEM);
init.ops = &raspberrypi_firmware_clk_ops;
init.flags = CLK_GET_RATE_NOCACHE;

18
drivers/clk/qcom/camcc-sm6350.c
View File

@ -1694,6 +1694,9 @@ static struct clk_branch camcc_sys_tmr_clk = {
static struct gdsc bps_gdsc = {
.gdscr = 0x6004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "bps_gdsc",
},
@ -1703,6 +1706,9 @@ static struct gdsc bps_gdsc = {
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x7004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ipe_0_gdsc",
},
@ -1712,6 +1718,9 @@ static struct gdsc ipe_0_gdsc = {
static struct gdsc ife_0_gdsc = {
.gdscr = 0x9004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ife_0_gdsc",
},
@ -1720,6 +1729,9 @@ static struct gdsc ife_0_gdsc = {
static struct gdsc ife_1_gdsc = {
.gdscr = 0xa004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ife_1_gdsc",
},
@ -1728,6 +1740,9 @@ static struct gdsc ife_1_gdsc = {
static struct gdsc ife_2_gdsc = {
.gdscr = 0xb004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ife_2_gdsc",
},
@ -1736,6 +1751,9 @@ static struct gdsc ife_2_gdsc = {
static struct gdsc titan_top_gdsc = {
.gdscr = 0x14004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "titan_top_gdsc",
},

3
drivers/clk/qcom/dispcc-sm6350.c
View File

@ -680,6 +680,9 @@ static struct clk_branch disp_cc_xo_clk = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x1004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},

4
drivers/clk/qcom/gcc-msm8939.c
View File

@ -432,7 +432,7 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
{ P_GPLL6, 2 },
{ P_GPLL6, 3 },
{ P_SLEEP_CLK, 6 },
};
@ -1113,7 +1113,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
F(24000000, P_GPLL0, 1, 1, 45),
F(24000000, P_GPLL6, 1, 1, 45),
F(66670000, P_GPLL0, 12, 0, 0),
{ }
};

6
drivers/clk/qcom/gcc-sm6350.c
View File

@ -2320,6 +2320,9 @@ static struct clk_branch gcc_video_xo_clk = {
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1a004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "usb30_prim_gdsc",
},
@ -2328,6 +2331,9 @@ static struct gdsc usb30_prim_gdsc = {
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x3a004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ufs_phy_gdsc",
},

6
drivers/clk/qcom/gpucc-sm6350.c
View File

@ -412,6 +412,9 @@ static struct clk_branch gpu_cc_gx_vsense_clk = {
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x8,
.pd = {
.name = "gpu_cx_gdsc",
},
@ -422,6 +425,9 @@ static struct gdsc gpu_cx_gdsc = {
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,

9
drivers/counter/interrupt-cnt.c
View File

@ -3,12 +3,14 @@
* Copyright (c) 2021 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
*/
#include <linux/cleanup.h>
#include <linux/counter.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/types.h>
@ -19,6 +21,7 @@ struct interrupt_cnt_priv {
struct gpio_desc *gpio;
int irq;
bool enabled;
struct mutex lock;
struct counter_signal signals;
struct counter_synapse synapses;
struct counter_count cnts;
@ -41,6 +44,8 @@ static int interrupt_cnt_enable_read(struct counter_device *counter,
{
struct interrupt_cnt_priv *priv = counter_priv(counter);
guard(mutex)(&priv->lock);
*enable = priv->enabled;
return 0;
@ -51,6 +56,8 @@ static int interrupt_cnt_enable_write(struct counter_device *counter,
{
struct interrupt_cnt_priv *priv = counter_priv(counter);
guard(mutex)(&priv->lock);
if (priv->enabled == enable)
return 0;
@ -227,6 +234,8 @@ static int interrupt_cnt_probe(struct platform_device *pdev)
if (ret)
return ret;
mutex_init(&priv->lock);
ret = devm_counter_add(dev, counter);
if (ret < 0)
return dev_err_probe(dev, ret, "Failed to add counter\n");

7
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c
View File

@ -275,13 +275,16 @@ theend_sgs:
} else {
if (nr_sgs > 0)
dma_unmap_sg(ce->dev, areq->src, ns, DMA_TO_DEVICE);
dma_unmap_sg(ce->dev, areq->dst, nd, DMA_FROM_DEVICE);
if (nr_sgd > 0)
dma_unmap_sg(ce->dev, areq->dst, nd, DMA_FROM_DEVICE);
}
theend_iv:
if (areq->iv && ivsize > 0) {
if (rctx->addr_iv)
if (!dma_mapping_error(ce->dev, rctx->addr_iv))
dma_unmap_single(ce->dev, rctx->addr_iv, rctx->ivlen, DMA_TO_DEVICE);
offset = areq->cryptlen - ivsize;
if (rctx->op_dir & CE_DECRYPTION) {
memcpy(areq->iv, chan->backup_iv, ivsize);

17
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
View File

@ -832,13 +832,12 @@ static int sun8i_ce_pm_init(struct sun8i_ce_dev *ce)
err = pm_runtime_set_suspended(ce->dev);
if (err)
return err;
pm_runtime_enable(ce->dev);
return err;
}
static void sun8i_ce_pm_exit(struct sun8i_ce_dev *ce)
{
pm_runtime_disable(ce->dev);
err = devm_pm_runtime_enable(ce->dev);
if (err)
return err;
return 0;
}
static int sun8i_ce_get_clks(struct sun8i_ce_dev *ce)
@ -1041,7 +1040,7 @@ static int sun8i_ce_probe(struct platform_device *pdev)
"sun8i-ce-ns", ce);
if (err) {
dev_err(ce->dev, "Cannot request CryptoEngine Non-secure IRQ (err=%d)\n", err);
goto error_irq;
goto error_pm;
}
err = sun8i_ce_register_algs(ce);
@ -1082,8 +1081,6 @@ static int sun8i_ce_probe(struct platform_device *pdev)
return 0;
error_alg:
sun8i_ce_unregister_algs(ce);
error_irq:
sun8i_ce_pm_exit(ce);
error_pm:
sun8i_ce_free_chanlist(ce, MAXFLOW - 1);
return err;
@ -1104,8 +1101,6 @@ static void sun8i_ce_remove(struct platform_device *pdev)
#endif
sun8i_ce_free_chanlist(ce, MAXFLOW - 1);
sun8i_ce_pm_exit(ce);
}
static const struct of_device_id sun8i_ce_crypto_of_match_table[] = {

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