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net/mlx5: SHAMPO: Introduce new SHAMPO specific HCA caps
Read and cache SHAMPO specific caps for header data split capabilities. Will be used in downstream patch. Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20250109204231.1809851-4-tariqt@nvidia.com Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
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@ -281,6 +281,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
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return err;
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}
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if (MLX5_CAP_GEN(dev, shampo)) {
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err = mlx5_core_get_caps_mode(dev, MLX5_CAP_SHAMPO, HCA_CAP_OPMOD_GET_CUR);
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if (err)
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return err;
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}
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return 0;
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}
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@ -368,6 +368,10 @@ int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_ty
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u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
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int err;
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if (WARN_ON(!dev->caps.hca[cap_type]))
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/* this cap_type must be added to mlx5_hca_caps_alloc() */
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return -EINVAL;
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memset(in, 0, sizeof(in));
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out = kzalloc(out_sz, GFP_KERNEL);
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if (!out)
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@ -1788,6 +1792,7 @@ static const int types[] = {
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MLX5_CAP_MACSEC,
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MLX5_CAP_ADV_VIRTUALIZATION,
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MLX5_CAP_CRYPTO,
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MLX5_CAP_SHAMPO,
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};
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static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
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@ -1245,6 +1245,7 @@ enum mlx5_cap_type {
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MLX5_CAP_DEV_EVENT = 0x14,
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MLX5_CAP_IPSEC,
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MLX5_CAP_CRYPTO = 0x1a,
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MLX5_CAP_SHAMPO = 0x1d,
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MLX5_CAP_MACSEC = 0x1f,
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MLX5_CAP_GENERAL_2 = 0x20,
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MLX5_CAP_PORT_SELECTION = 0x25,
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@ -1470,6 +1471,9 @@ enum mlx5_qcam_feature_groups {
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#define MLX5_CAP_MACSEC(mdev, cap)\
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MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
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#define MLX5_CAP_SHAMPO(mdev, cap) \
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MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)
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enum {
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MLX5_CMD_STAT_OK = 0x0,
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MLX5_CMD_STAT_INT_ERR = 0x1,
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@ -2327,7 +2327,9 @@ struct mlx5_ifc_wq_bits {
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u8 headers_mkey[0x20];
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u8 shampo_enable[0x1];
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u8 reserved_at_1e1[0x4];
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u8 reserved_at_1e1[0x1];
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u8 shampo_mode[0x2];
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u8 reserved_at_1e4[0x1];
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u8 log_reservation_size[0x3];
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u8 reserved_at_1e8[0x5];
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u8 log_max_num_of_packets_per_reservation[0x3];
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@ -3699,6 +3701,22 @@ struct mlx5_ifc_crypto_cap_bits {
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u8 reserved_at_80[0x780];
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};
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struct mlx5_ifc_shampo_cap_bits {
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u8 reserved_at_0[0x3];
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u8 shampo_log_max_reservation_size[0x5];
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u8 reserved_at_8[0x3];
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u8 shampo_log_min_reservation_size[0x5];
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u8 shampo_min_mss_size[0x10];
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u8 shampo_header_split[0x1];
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u8 shampo_header_split_data_merge[0x1];
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u8 reserved_at_22[0x1];
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u8 shampo_log_max_headers_entry_size[0x5];
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u8 reserved_at_28[0x18];
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u8 reserved_at_40[0x7c0];
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};
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union mlx5_ifc_hca_cap_union_bits {
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struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
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struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
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