arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports

commit 794a066688038df46c01e177cc6faebded0acba4 upstream.

The mvebu-comphy driver does not currently know how to pass correct
lane-count to ATF while configuring the serdes lanes.

This causes the system to hard reset during reconfiguration, if a pci
card is present and has established a link during bootloader.

Remove the comphy handles from the respective pci nodes to avoid runtime
reconfiguration, relying solely on bootloader configuration - while
avoiding the hard reset.

When bootloader has configured the lanes correctly, the pci ports are
functional under Linux.

This issue may be addressed in the comphy driver at a future point.

Fixes: e9ff907f40 ("arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board")
Cc: stable@vger.kernel.org
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Josua Mayer 2025-09-11 20:28:06 +02:00 committed by Greg Kroah-Hartman
parent 562a134222
commit e2ded08723

View File

@ -413,7 +413,13 @@
/* SRDS #0,#1,#2,#3 - PCIe */
&cp0_pcie0 {
num-lanes = <4>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
*/
status = "okay";
};
@ -475,7 +481,13 @@
/* SRDS #0,#1 - PCIe */
&cp1_pcie0 {
num-lanes = <2>;
phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
*/
status = "okay";
};