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perf vendor events arm64: Add FUJITSU-MONAKA PMU event

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Add PMU events for FUJITSU-MONAKA.

And, also updated common-and-microarch.json and recommended.json.

FUJITSU-MONAKA Specification URL:

  https://github.com/fujitsu/FUJITSU-MONAKA

Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Akio Kakuno <fj3333bs@aa.jp.fujitsu.com>
Signed-off-by: Yoshihiro Furudera <fj5100bi@fujitsu.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linux.dev>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: Xu Yang <xu.yang_2@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20241217065751.1448755-1-fj5100bi@fujitsu.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Yoshihiro Furudera 2024-12-17 06:57:51 +00:00 committed by Arnaldo Carvalho de Melo
parent 876e80cf83
commit e5e34e9995
25 changed files with 2927 additions and 0 deletions
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715
tools/perf/pmu-events/arch/arm64/common-and-microarch.json
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@ -533,6 +533,11 @@
"EventName": "SVE_INST_SPEC",
"BriefDescription": "SVE operations speculatively executed"
},
{
"EventCode": "0x8007",
"EventName": "ASE_SVE_INST_SPEC",
"BriefDescription": "Operation speculatively executed, Advanced SIMD or SVE."
},
{
"PublicDescription": "Microarchitectural operation, Operations speculatively executed.",
"EventCode": "0x8008",
@ -551,48 +556,393 @@
"EventName": "FP_SPEC",
"BriefDescription": "Floating-point Operations speculatively executed."
},
{
"EventCode": "0x8011",
"EventName": "ASE_FP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD."
},
{
"EventCode": "0x8012",
"EventName": "SVE_FP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE."
},
{
"EventCode": "0x8013",
"EventName": "ASE_SVE_FP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE."
},
{
"PublicDescription": "Floating-point half-precision operations speculatively executed",
"EventCode": "0x8014",
"EventName": "FP_HP_SPEC",
"BriefDescription": "Floating-point half-precision operations speculatively executed"
},
{
"EventCode": "0x8015",
"EventName": "ASE_FP_HP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD half precision."
},
{
"EventCode": "0x8016",
"EventName": "SVE_FP_HP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE half precision."
},
{
"EventCode": "0x8017",
"EventName": "ASE_SVE_FP_HP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE half precision."
},
{
"PublicDescription": "Floating-point single-precision operations speculatively executed",
"EventCode": "0x8018",
"EventName": "FP_SP_SPEC",
"BriefDescription": "Floating-point single-precision operations speculatively executed"
},
{
"EventCode": "0x8019",
"EventName": "ASE_FP_SP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD single precision."
},
{
"EventCode": "0x801A",
"EventName": "SVE_FP_SP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE single precision."
},
{
"EventCode": "0x801B",
"EventName": "ASE_SVE_FP_SP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE single precision."
},
{
"PublicDescription": "Floating-point double-precision operations speculatively executed",
"EventCode": "0x801C",
"EventName": "FP_DP_SPEC",
"BriefDescription": "Floating-point double-precision operations speculatively executed"
},
{
"EventCode": "0x801D",
"EventName": "ASE_FP_DP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD double precision."
},
{
"EventCode": "0x801E",
"EventName": "SVE_FP_DP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE double precision."
},
{
"EventCode": "0x801F",
"EventName": "ASE_SVE_FP_DP_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE double precision."
},
{
"EventCode": "0x8020",
"EventName": "FP_DIV_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, divide."
},
{
"EventCode": "0x8021",
"EventName": "ASE_FP_DIV_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD divide."
},
{
"EventCode": "0x8022",
"EventName": "SVE_FP_DIV_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE divide."
},
{
"EventCode": "0x8023",
"EventName": "ASE_SVE_FP_DIV_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE divide."
},
{
"EventCode": "0x8024",
"EventName": "FP_SQRT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, square root."
},
{
"EventCode": "0x8025",
"EventName": "ASE_FP_SQRT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD square root."
},
{
"EventCode": "0x8026",
"EventName": "SVE_FP_SQRT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE square root."
},
{
"EventCode": "0x8027",
"EventName": "ASE_SVE_FP_SQRT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE square-root."
},
{
"PublicDescription": "Floating-point FMA Operations speculatively executed.",
"EventCode": "0x8028",
"EventName": "FP_FMA_SPEC",
"BriefDescription": "Floating-point FMA Operations speculatively executed."
},
{
"EventCode": "0x8029",
"EventName": "ASE_FP_FMA_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD FMA."
},
{
"EventCode": "0x802A",
"EventName": "SVE_FP_FMA_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE FMA."
},
{
"EventCode": "0x802B",
"EventName": "ASE_SVE_FP_FMA_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE FMA."
},
{
"EventCode": "0x802C",
"EventName": "FP_MUL_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, multiply."
},
{
"EventCode": "0x802D",
"EventName": "ASE_FP_MUL_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD multiply."
},
{
"EventCode": "0x802E",
"EventName": "SVE_FP_MUL_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE multiply."
},
{
"EventCode": "0x802F",
"EventName": "ASE_SVE_FP_MUL_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE multiply."
},
{
"EventCode": "0x8030",
"EventName": "FP_ADDSUB_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, add or subtract."
},
{
"EventCode": "0x8031",
"EventName": "ASE_FP_ADDSUB_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD add or subtract."
},
{
"EventCode": "0x8032",
"EventName": "SVE_FP_ADDSUB_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE add or subtract."
},
{
"EventCode": "0x8033",
"EventName": "ASE_SVE_FP_ADDSUB_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE add or subtract."
},
{
"PublicDescription": "Floating-point reciprocal estimate Operations speculatively executed.",
"EventCode": "0x8034",
"EventName": "FP_RECPE_SPEC",
"BriefDescription": "Floating-point reciprocal estimate Operations speculatively executed."
},
{
"EventCode": "0x8035",
"EventName": "ASE_FP_RECPE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD reciprocal estimate."
},
{
"EventCode": "0x8036",
"EventName": "SVE_FP_RECPE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE reciprocal estimate."
},
{
"EventCode": "0x8037",
"EventName": "ASE_SVE_FP_RECPE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE reciprocal estimate."
},
{
"PublicDescription": "floating-point convert Operations speculatively executed.",
"EventCode": "0x8038",
"EventName": "FP_CVT_SPEC",
"BriefDescription": "floating-point convert Operations speculatively executed."
},
{
"EventCode": "0x8039",
"EventName": "ASE_FP_CVT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD convert."
},
{
"EventCode": "0x803A",
"EventName": "SVE_FP_CVT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE convert."
},
{
"EventCode": "0x803B",
"EventName": "ASE_SVE_FP_CVT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE convert."
},
{
"EventCode": "0x803C",
"EventName": "SVE_FP_AREDUCE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE accumulating reduction."
},
{
"EventCode": "0x803D",
"EventName": "ASE_FP_PREDUCE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD pairwise add step."
},
{
"EventCode": "0x803E",
"EventName": "SVE_FP_VREDUCE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, SVE vector reduction."
},
{
"EventCode": "0x803F",
"EventName": "ASE_SVE_FP_VREDUCE_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE vector reduction."
},
{
"EventCode": "0x8040",
"EventName": "INT_SPEC",
"BriefDescription": "Integer Operation speculatively executed."
},
{
"EventCode": "0x8041",
"EventName": "ASE_INT_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD."
},
{
"EventCode": "0x8042",
"EventName": "SVE_INT_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE."
},
{
"PublicDescription": "Advanced SIMD and SVE integer Operations speculatively executed.",
"EventCode": "0x8043",
"EventName": "ASE_SVE_INT_SPEC",
"BriefDescription": "Advanced SIMD and SVE integer Operations speculatively executed."
},
{
"EventCode": "0x8044",
"EventName": "INT_DIV_SPEC",
"BriefDescription": "Integer Operation speculatively executed, divide."
},
{
"EventCode": "0x8045",
"EventName": "INT_DIV64_SPEC",
"BriefDescription": "Integer Operation speculatively executed, 64-bit divide."
},
{
"EventCode": "0x8046",
"EventName": "SVE_INT_DIV_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE divide."
},
{
"EventCode": "0x8047",
"EventName": "SVE_INT_DIV64_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE 64-bit divide."
},
{
"EventCode": "0x8048",
"EventName": "INT_MUL_SPEC",
"BriefDescription": "Integer Operation speculatively executed, multiply."
},
{
"EventCode": "0x8049",
"EventName": "ASE_INT_MUL_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD multiply."
},
{
"EventCode": "0x804A",
"EventName": "SVE_INT_MUL_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE multiply."
},
{
"EventCode": "0x804B",
"EventName": "ASE_SVE_INT_MUL_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE multiply."
},
{
"EventCode": "0x804C",
"EventName": "INT_MUL64_SPEC",
"BriefDescription": "Integer Operation speculatively executed, 64\u00d764 multiply."
},
{
"EventCode": "0x804D",
"EventName": "SVE_INT_MUL64_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE 64\u00d764 multiply."
},
{
"EventCode": "0x804E",
"EventName": "INT_MULH64_SPEC",
"BriefDescription": "Integer Operation speculatively executed, 64\u00d764 multiply returning high part."
},
{
"EventCode": "0x804F",
"EventName": "SVE_INT_MULH64_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE 64\u00d764 multiply high part."
},
{
"EventCode": "0x8058",
"EventName": "NONFP_SPEC",
"BriefDescription": "Non-floating-point Operation speculatively executed."
},
{
"EventCode": "0x8059",
"EventName": "ASE_NONFP_SPEC",
"BriefDescription": "Non-floating-point Operation speculatively executed, Advanced SIMD."
},
{
"EventCode": "0x805A",
"EventName": "SVE_NONFP_SPEC",
"BriefDescription": "Non-floating-point Operation speculatively executed, SVE."
},
{
"EventCode": "0x805B",
"EventName": "ASE_SVE_NONFP_SPEC",
"BriefDescription": "Non-floating-point Operation speculatively executed, Advanced SIMD or SVE."
},
{
"EventCode": "0x805D",
"EventName": "ASE_INT_VREDUCE_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD reduction."
},
{
"EventCode": "0x805E",
"EventName": "SVE_INT_VREDUCE_SPEC",
"BriefDescription": "Integer Operation speculatively executed, SVE reduction."
},
{
"EventCode": "0x805F",
"EventName": "ASE_SVE_INT_VREDUCE_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE reduction."
},
{
"EventCode": "0x8060",
"EventName": "SVE_PERM_SPEC",
"BriefDescription": "Operation speculatively executed, SVE permute."
},
{
"EventCode": "0x8065",
"EventName": "SVE_XPIPE_Z2R_SPEC",
"BriefDescription": "Operation speculatively executed, SVE vector to scalar cross-pipe."
},
{
"EventCode": "0x8066",
"EventName": "SVE_XPIPE_R2Z_SPEC",
"BriefDescription": "Operation speculatively executed, SVE scalar to vector cross-pipe."
},
{
"EventCode": "0x8068",
"EventName": "SVE_PGEN_SPEC",
"BriefDescription": "Operation speculatively executed, SVE predicate generating."
},
{
"EventCode": "0x8069",
"EventName": "SVE_PGEN_FLG_SPEC",
"BriefDescription": "Operation speculatively executed, SVE predicate flag setting."
},
{
"EventCode": "0x806D",
"EventName": "SVE_PPERM_SPEC",
"BriefDescription": "Operation speculatively executed, SVE predicate permute."
},
{
"PublicDescription": "SVE predicated Operations speculatively executed.",
"EventCode": "0x8074",
@ -629,6 +979,16 @@
"EventName": "SVE_MOVPRFX_SPEC",
"BriefDescription": "SVE MOVPRFX Operations speculatively executed."
},
{
"EventCode": "0x807D",
"EventName": "SVE_MOVPRFX_Z_SPEC",
"BriefDescription": "Operation speculatively executed, SVE MOVPRFX zeroing predication."
},
{
"EventCode": "0x807E",
"EventName": "SVE_MOVPRFX_M_SPEC",
"BriefDescription": "Operation speculatively executed, SVE MOVPRFX merging predication."
},
{
"PublicDescription": "SVE MOVPRFX unfused Operations speculatively executed.",
"EventCode": "0x807F",
@ -695,6 +1055,16 @@
"EventName": "SVE_PRF_CONTIG_SPEC",
"BriefDescription": "SVE contiguous prefetch element Operations speculatively executed."
},
{
"EventCode": "0x80A1",
"EventName": "SVE_LDNT_CONTIG_SPEC",
"BriefDescription": "Operation speculatively executed, SVE non-temporal contiguous load element."
},
{
"EventCode": "0x80A2",
"EventName": "SVE_STNT_CONTIG_SPEC",
"BriefDescription": "Operation speculatively executed, SVE non-temporal contiguous store element."
},
{
"PublicDescription": "Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed.",
"EventCode": "0x80A5",
@ -785,6 +1155,16 @@
"EventName": "FP_DP_FIXED_OPS_SPEC",
"BriefDescription": "Non-scalable double-precision floating-point element Operations speculatively executed."
},
{
"EventCode": "0x80C8",
"EventName": "INT_SCALE_OPS_SPEC",
"BriefDescription": "Scalable integer element arithmetic operations Speculatively executed."
},
{
"EventCode": "0x80C9",
"EventName": "INT_FIXED_OPS_SPEC",
"BriefDescription": "Non-scalable integer element arithmetic operations Speculatively executed."
},
{
"PublicDescription": "Advanced SIMD and SVE 8-bit integer operations speculatively executed",
"EventCode": "0x80E3",
@ -808,5 +1188,340 @@
"EventCode": "0x80EF",
"EventName": "ASE_SVE_INT64_SPEC",
"BriefDescription": "Advanced SIMD and SVE 64-bit integer operations speculatively executed"
},
{
"EventCode": "0x80F3",
"EventName": "ASE_SVE_FP_DOT_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE dot-product."
},
{
"EventCode": "0x80F7",
"EventName": "ASE_SVE_FP_MMLA_SPEC",
"BriefDescription": "Floating-point Operation speculatively executed, Advanced SIMD or SVE matrix multiply."
},
{
"EventCode": "0x80FB",
"EventName": "ASE_SVE_INT_DOT_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE dot-product."
},
{
"EventCode": "0x80FF",
"EventName": "ASE_SVE_INT_MMLA_SPEC",
"BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE matrix multiply."
},
{
"EventCode": "0x8128",
"EventName": "DTLB_WALK_PERCYC",
"BriefDescription": "Data translation table walks in progress."
},
{
"EventCode": "0x8129",
"EventName": "ITLB_WALK_PERCYC",
"BriefDescription": "Instruction translation table walks in progress."
},
{
"EventCode": "0x8136",
"EventName": "DTLB_STEP",
"BriefDescription": "Data TLB translation table walk, step."
},
{
"EventCode": "0x8137",
"EventName": "ITLB_STEP",
"BriefDescription": "Instruction TLB translation table walk, step."
},
{
"EventCode": "0x8138",
"EventName": "DTLB_WALK_LARGE",
"BriefDescription": "Data TLB large page translation table walk."
},
{
"EventCode": "0x8139",
"EventName": "ITLB_WALK_LARGE",
"BriefDescription": "Instruction TLB large page translation table walk."
},
{
"EventCode": "0x813A",
"EventName": "DTLB_WALK_SMALL",
"BriefDescription": "Data TLB small page translation table walk."
},
{
"EventCode": "0x813B",
"EventName": "ITLB_WALK_SMALL",
"BriefDescription": "Instruction TLB small page translation table walk."
},
{
"EventCode": "0x8144",
"EventName": "L1D_CACHE_MISS",
"BriefDescription": "Level 1 data cache demand access miss."
},
{
"EventCode": "0x8145",
"EventName": "L1I_CACHE_HWPRF",
"BriefDescription": "Level 1 instruction cache hardware prefetch."
},
{
"EventCode": "0x814C",
"EventName": "L2D_CACHE_MISS",
"BriefDescription": "Level 2 data cache demand access miss."
},
{
"EventCode": "0x8154",
"EventName": "L1D_CACHE_HWPRF",
"BriefDescription": "Level 1 data cache hardware prefetch."
},
{
"EventCode": "0x8155",
"EventName": "L2D_CACHE_HWPRF",
"BriefDescription": "Level 2 data cache hardware prefetch."
},
{
"EventCode": "0x8158",
"EventName": "STALL_FRONTEND_MEMBOUND",
"BriefDescription": "Frontend stall cycles, memory bound."
},
{
"EventCode": "0x8159",
"EventName": "STALL_FRONTEND_L1I",
"BriefDescription": "Frontend stall cycles, level 1 instruction cache."
},
{
"EventCode": "0x815A",
"EventName": "STALL_FRONTEND_L2I",
"BriefDescription": "Frontend stall cycles, level 2 instruction cache."
},
{
"EventCode": "0x815B",
"EventName": "STALL_FRONTEND_MEM",
"BriefDescription": "Frontend stall cycles, last level PE cache or memory."
},
{
"EventCode": "0x815C",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "Frontend stall cycles, TLB."
},
{
"EventCode": "0x8160",
"EventName": "STALL_FRONTEND_CPUBOUND",
"BriefDescription": "Frontend stall cycles, processor bound."
},
{
"EventCode": "0x8161",
"EventName": "STALL_FRONTEND_FLOW",
"BriefDescription": "Frontend stall cycles, flow control."
},
{
"EventCode": "0x8162",
"EventName": "STALL_FRONTEND_FLUSH",
"BriefDescription": "Frontend stall cycles, flush recovery."
},
{
"EventCode": "0x8163",
"EventName": "STALL_FRONTEND_RENAME",
"BriefDescription": "Frontend stall cycles, rename full."
},
{
"EventCode": "0x8164",
"EventName": "STALL_BACKEND_MEMBOUND",
"BriefDescription": "Backend stall cycles, memory bound."
},
{
"EventCode": "0x8165",
"EventName": "STALL_BACKEND_L1D",
"BriefDescription": "Backend stall cycles, level 1 data cache."
},
{
"EventCode": "0x8166",
"EventName": "STALL_BACKEND_L2D",
"BriefDescription": "Backend stall cycles, level 2 data cache."
},
{
"EventCode": "0x8167",
"EventName": "STALL_BACKEND_TLB",
"BriefDescription": "Backend stall cycles, TLB."
},
{
"EventCode": "0x8168",
"EventName": "STALL_BACKEND_ST",
"BriefDescription": "Backend stall cycles, store."
},
{
"EventCode": "0x816A",
"EventName": "STALL_BACKEND_CPUBOUND",
"BriefDescription": "Backend stall cycles, processor bound."
},
{
"EventCode": "0x816B",
"EventName": "STALL_BACKEND_BUSY",
"BriefDescription": "Backend stall cycles, backend busy."
},
{
"EventCode": "0x816C",
"EventName": "STALL_BACKEND_ILOCK",
"BriefDescription": "Backend stall cycles, input dependency."
},
{
"EventCode": "0x816D",
"EventName": "STALL_BACKEND_RENAME",
"BriefDescription": "Backend stall cycles, rename full."
},
{
"EventCode": "0x816E",
"EventName": "STALL_BACKEND_ATOMIC",
"BriefDescription": "Backend stall cycles, atomic operation."
},
{
"EventCode": "0x816F",
"EventName": "STALL_BACKEND_MEMCPYSET",
"BriefDescription": "Backend stall cycles, Memory Copy or Set operation."
},
{
"EventCode": "0x8186",
"EventName": "UOP_RETIRED",
"BriefDescription": "Micro-operation architecturally executed."
},
{
"EventCode": "0x8188",
"EventName": "DTLB_WALK_BLOCK",
"BriefDescription": "Data TLB block translation table walk."
},
{
"EventCode": "0x8189",
"EventName": "ITLB_WALK_BLOCK",
"BriefDescription": "Instruction TLB block translation table walk."
},
{
"EventCode": "0x818A",
"EventName": "DTLB_WALK_PAGE",
"BriefDescription": "Data TLB page translation table walk."
},
{
"EventCode": "0x818B",
"EventName": "ITLB_WALK_PAGE",
"BriefDescription": "Instruction TLB page translation table walk."
},
{
"EventCode": "0x81B8",
"EventName": "L1I_CACHE_REFILL_HWPRF",
"BriefDescription": "Level 1 instruction cache refill, hardware prefetch."
},
{
"EventCode": "0x81BC",
"EventName": "L1D_CACHE_REFILL_HWPRF",
"BriefDescription": "Level 1 data cache refill, hardware prefetch."
},
{
"EventCode": "0x81BD",
"EventName": "L2D_CACHE_REFILL_HWPRF",
"BriefDescription": "Level 2 data cache refill, hardware prefetch."
},
{
"EventCode": "0x81C0",
"EventName": "L1I_CACHE_HIT_RD",
"BriefDescription": "Level 1 instruction cache demand fetch hit."
},
{
"EventCode": "0x81C4",
"EventName": "L1D_CACHE_HIT_RD",
"BriefDescription": "Level 1 data cache demand access hit, read."
},
{
"EventCode": "0x81C5",
"EventName": "L2D_CACHE_HIT_RD",
"BriefDescription": "Level 2 data cache demand access hit, read."
},
{
"EventCode": "0x81C8",
"EventName": "L1D_CACHE_HIT_WR",
"BriefDescription": "Level 1 data cache demand access hit, write."
},
{
"EventCode": "0x81C9",
"EventName": "L2D_CACHE_HIT_WR",
"BriefDescription": "Level 2 data cache demand access hit, write."
},
{
"EventCode": "0x8200",
"EventName": "L1I_CACHE_HIT",
"BriefDescription": "Level 1 instruction cache hit."
},
{
"EventCode": "0x8204",
"EventName": "L1D_CACHE_HIT",
"BriefDescription": "Level 1 data cache hit."
},
{
"EventCode": "0x8205",
"EventName": "L2D_CACHE_HIT",
"BriefDescription": "Level 2 data cache hit."
},
{
"EventCode": "0x8240",
"EventName": "L1I_LFB_HIT_RD",
"BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer hit."
},
{
"EventCode": "0x8244",
"EventName": "L1D_LFB_HIT_RD",
"BriefDescription": "Level 1 data cache demand access line-fill buffer hit, read."
},
{
"EventCode": "0x8245",
"EventName": "L2D_LFB_HIT_RD",
"BriefDescription": "Level 2 data cache demand access line-fill buffer hit, read."
},
{
"EventCode": "0x8248",
"EventName": "L1D_LFB_HIT_WR",
"BriefDescription": "Level 1 data cache demand access line-fill buffer hit, write."
},
{
"EventCode": "0x8249",
"EventName": "L2D_LFB_HIT_WR",
"BriefDescription": "Level 2 data cache demand access line-fill buffer hit, write."
},
{
"EventCode": "0x8280",
"EventName": "L1I_CACHE_PRF",
"BriefDescription": "Level 1 instruction cache, preload or prefetch hit."
},
{
"EventCode": "0x8284",
"EventName": "L1D_CACHE_PRF",
"BriefDescription": "Level 1 data cache, preload or prefetch hit."
},
{
"EventCode": "0x8285",
"EventName": "L2D_CACHE_PRF",
"BriefDescription": "Level 2 data cache, preload or prefetch hit."
},
{
"EventCode": "0x8288",
"EventName": "L1I_CACHE_REFILL_PRF",
"BriefDescription": "Level 1 instruction cache refill, preload or prefetch hit."
},
{
"EventCode": "0x828C",
"EventName": "L1D_CACHE_REFILL_PRF",
"BriefDescription": "Level 1 data cache refill, preload or prefetch hit."
},
{
"EventCode": "0x828D",
"EventName": "L2D_CACHE_REFILL_PRF",
"BriefDescription": "Level 2 data cache refill, preload or prefetch hit."
},
{
"EventCode": "0x8320",
"EventName": "L1D_CACHE_REFILL_PERCYC",
"BriefDescription": "Level 1 data or unified cache refills in progress."
},
{
"EventCode": "0x8321",
"EventName": "L2D_CACHE_REFILL_PERCYC",
"BriefDescription": "Level 2 data or unified cache refills in progress."
},
{
"EventCode": "0x8324",
"EventName": "L1I_CACHE_REFILL_PERCYC",
"BriefDescription": "Level 1 instruction or unified cache refills in progress."
}
]

6
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[
{
"ArchStdEvent": "L1I_CACHE_PRF",
"BriefDescription": "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch."
}
]

122
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[
{
"EventCode": "0x0182",
"EventName": "LD_COMP_WAIT_L1_MISS",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access."
},
{
"EventCode": "0x0183",
"EventName": "LD_COMP_WAIT_L1_MISS_EX",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access."
},
{
"EventCode": "0x0184",
"EventName": "LD_COMP_WAIT",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."
},
{
"EventCode": "0x0185",
"EventName": "LD_COMP_WAIT_EX",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."
},
{
"EventCode": "0x0186",
"EventName": "LD_COMP_WAIT_PFP_BUSY",
"BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port."
},
{
"EventCode": "0x0187",
"EventName": "LD_COMP_WAIT_PFP_BUSY_EX",
"BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation."
},
{
"EventCode": "0x0188",
"EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF",
"BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction."
},
{
"EventCode": "0x0189",
"EventName": "EU_COMP_WAIT",
"BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction."
},
{
"EventCode": "0x018A",
"EventName": "FL_COMP_WAIT",
"BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction."
},
{
"EventCode": "0x018B",
"EventName": "BR_COMP_WAIT",
"BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction."
},
{
"EventCode": "0x018C",
"EventName": "ROB_EMPTY",
"BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty."
},
{
"EventCode": "0x018D",
"EventName": "ROB_EMPTY_STQ_BUSY",
"BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full."
},
{
"EventCode": "0x018E",
"EventName": "WFE_WFI_CYCLE",
"BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction."
},
{
"EventCode": "0x018F",
"EventName": "RETENTION_CYCLE",
"BriefDescription": "This event counts every cycle that the instruction unit is halted by the RETENTION state."
},
{
"EventCode": "0x0190",
"EventName": "_0INST_COMMIT",
"BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only."
},
{
"EventCode": "0x0191",
"EventName": "_1INST_COMMIT",
"BriefDescription": "This event counts every cycle that one instruction is committed."
},
{
"EventCode": "0x0192",
"EventName": "_2INST_COMMIT",
"BriefDescription": "This event counts every cycle that two instructions are committed."
},
{
"EventCode": "0x0193",
"EventName": "_3INST_COMMIT",
"BriefDescription": "This event counts every cycle that three instructions are committed."
},
{
"EventCode": "0x0194",
"EventName": "_4INST_COMMIT",
"BriefDescription": "This event counts every cycle that four instructions are committed."
},
{
"EventCode": "0x0195",
"EventName": "_5INST_COMMIT",
"BriefDescription": "This event counts every cycle that five instructions are committed."
},
{
"EventCode": "0x0198",
"EventName": "UOP_ONLY_COMMIT",
"BriefDescription": "This event counts every cycle that only any micro-operations are committed."
},
{
"EventCode": "0x0199",
"EventName": "SINGLE_MOVPRFX_COMMIT",
"BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed."
},
{
"EventCode": "0x019C",
"EventName": "LD_COMP_WAIT_L2_MISS",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache miss."
},
{
"EventCode": "0x019D",
"EventName": "LD_COMP_WAIT_L2_MISS_EX",
"BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache miss."
}
]

17
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/energy.json Normal file
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[
{
"EventCode": "0x01F0",
"EventName": "EA_CORE",
"BriefDescription": "This event counts energy consumption of core."
},
{
"EventCode": "0x03F0",
"EventName": "EA_L3",
"BriefDescription": "This event counts energy consumption of L3 cache."
},
{
"EventCode": "0x03F1",
"EventName": "EA_LDO_LOSS",
"BriefDescription": "This event counts energy consumption of LDO loss."
}
]

42
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json Normal file
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[
{
"ArchStdEvent": "EXC_TAKEN",
"BriefDescription": "This event counts each exception taken."
},
{
"ArchStdEvent": "EXC_RETURN",
"BriefDescription": "This event counts each executed exception return instruction."
},
{
"ArchStdEvent": "EXC_UNDEF",
"BriefDescription": "This event counts only other synchronous exceptions that are taken locally."
},
{
"ArchStdEvent": "EXC_SVC",
"BriefDescription": "This event counts only Supervisor Call exceptions that are taken locally."
},
{
"ArchStdEvent": "EXC_PABORT",
"BriefDescription": "This event counts only Instruction Abort exceptions that are taken locally."
},
{
"ArchStdEvent": "EXC_DABORT",
"BriefDescription": "This event counts only Data Abort or SError interrupt exceptions that are taken locally."
},
{
"ArchStdEvent": "EXC_IRQ",
"BriefDescription": "This event counts only IRQ exceptions that are taken locally, including Virtual IRQ exceptions."
},
{
"ArchStdEvent": "EXC_FIQ",
"BriefDescription": "This event counts only FIQ exceptions that are taken locally, including Virtual FIQ exceptions."
},
{
"ArchStdEvent": "EXC_SMC",
"BriefDescription": "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception."
},
{
"ArchStdEvent": "EXC_HVC",
"BriefDescription": "This event counts for both Hypervisor Call exceptions taken locally in the hypervisor and those taken as an exception from Non-secure EL1."
}
]

209
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json Normal file
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[
{
"EventCode": "0x0105",
"EventName": "FP_MV_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point move operations."
},
{
"EventCode": "0x0112",
"EventName": "FP_LD_SPEC",
"BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers."
},
{
"EventCode": "0x0113",
"EventName": "FP_ST_SPEC",
"BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers."
},
{
"ArchStdEvent": "ASE_FP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point operation."
},
{
"ArchStdEvent": "SVE_FP_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point operations."
},
{
"ArchStdEvent": "FP_HP_SPEC",
"BriefDescription": "This event counts architecturally executed half-precision floating-point operation."
},
{
"ArchStdEvent": "ASE_FP_HP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD half-precision floating-point operation."
},
{
"ArchStdEvent": "SVE_FP_HP_SPEC",
"BriefDescription": "This event counts architecturally executed SVE half-precision floating-point operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_HP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations."
},
{
"ArchStdEvent": "FP_SP_SPEC",
"BriefDescription": "This event counts architecturally executed single-precision floating-point operation."
},
{
"ArchStdEvent": "ASE_FP_SP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD single-precision floating-point operation."
},
{
"ArchStdEvent": "SVE_FP_SP_SPEC",
"BriefDescription": "This event counts architecturally executed SVE single-precision floating-point operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_SP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations."
},
{
"ArchStdEvent": "FP_DP_SPEC",
"BriefDescription": "This event counts architecturally executed double-precision floating-point operation."
},
{
"ArchStdEvent": "ASE_FP_DP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD double-precision floating-point operation."
},
{
"ArchStdEvent": "SVE_FP_DP_SPEC",
"BriefDescription": "This event counts architecturally executed SVE double-precision floating-point operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_DP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations."
},
{
"ArchStdEvent": "FP_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point divide operation."
},
{
"ArchStdEvent": "ASE_FP_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point divide operation."
},
{
"ArchStdEvent": "SVE_FP_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point divide operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations."
},
{
"ArchStdEvent": "FP_SQRT_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point square root operation."
},
{
"ArchStdEvent": "ASE_FP_SQRT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point square root operation."
},
{
"ArchStdEvent": "SVE_FP_SQRT_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point square root operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_SQRT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations."
},
{
"ArchStdEvent": "ASE_FP_FMA_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point FMA operation."
},
{
"ArchStdEvent": "SVE_FP_FMA_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point FMA operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_FMA_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations."
},
{
"ArchStdEvent": "FP_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point multiply operations."
},
{
"ArchStdEvent": "ASE_FP_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point multiply operation."
},
{
"ArchStdEvent": "SVE_FP_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point multiply operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations."
},
{
"ArchStdEvent": "FP_ADDSUB_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point add or subtract operations."
},
{
"ArchStdEvent": "ASE_FP_ADDSUB_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point add or subtract operation."
},
{
"ArchStdEvent": "SVE_FP_ADDSUB_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point add or subtract operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_ADDSUB_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations."
},
{
"ArchStdEvent": "ASE_FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations."
},
{
"ArchStdEvent": "SVE_FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operations."
},
{
"ArchStdEvent": "ASE_SVE_FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations."
},
{
"ArchStdEvent": "ASE_FP_CVT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point convert operation."
},
{
"ArchStdEvent": "SVE_FP_CVT_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point convert operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_CVT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations."
},
{
"ArchStdEvent": "SVE_FP_AREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operations."
},
{
"ArchStdEvent": "ASE_FP_PREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations."
},
{
"ArchStdEvent": "SVE_FP_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE floating-point vector reduction operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations."
},
{
"ArchStdEvent": "FP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "ASE_SVE_FP_DOT_SPEC",
"BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point dot-product operation."
},
{
"ArchStdEvent": "ASE_SVE_FP_MMLA_SPEC",
"BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point matrix multiply operation."
}
]

97
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[
{
"EventCode": "0x0880",
"EventName": "GCYCLES",
"BriefDescription": "This event counts the number of cycles at 100MHz."
},
{
"EventCode": "0x0890",
"EventName": "FL0_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 0."
},
{
"EventCode": "0x0891",
"EventName": "FL1_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 1."
},
{
"EventCode": "0x0892",
"EventName": "FL2_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 2."
},
{
"EventCode": "0x0893",
"EventName": "FL3_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 3."
},
{
"EventCode": "0x0894",
"EventName": "FL4_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 4."
},
{
"EventCode": "0x0895",
"EventName": "FL5_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 5."
},
{
"EventCode": "0x0896",
"EventName": "FL6_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 6."
},
{
"EventCode": "0x0897",
"EventName": "FL7_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 7."
},
{
"EventCode": "0x0898",
"EventName": "FL8_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 8."
},
{
"EventCode": "0x0899",
"EventName": "FL9_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 9."
},
{
"EventCode": "0x089A",
"EventName": "FL10_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 10."
},
{
"EventCode": "0x089B",
"EventName": "FL11_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 11."
},
{
"EventCode": "0x089C",
"EventName": "FL12_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 12."
},
{
"EventCode": "0x089D",
"EventName": "FL13_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 13."
},
{
"EventCode": "0x089E",
"EventName": "FL14_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 14."
},
{
"EventCode": "0x089F",
"EventName": "FL15_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the Frequency Level 15."
},
{
"EventCode": "0x08A0",
"EventName": "RETENTION_GCYCLES",
"BriefDescription": "This event counts the number of cycles where the measured core is staying in the RETENTION state."
},
{
"EventCode": "0x08A1",
"EventName": "RETENTION_COUNT",
"BriefDescription": "This event counts the number of changes from the normal state to the RETENTION state."
}
]

10
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/general.json Normal file
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[
{
"ArchStdEvent": "CPU_CYCLES",
"BriefDescription": "This event counts every cycle."
},
{
"ArchStdEvent": "CNT_CYCLES",
"BriefDescription": "This event counts the constant frequency cycles counter increments at a constant frequency equal to the rate of increment of the System counter."
}
]

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tools/perf/pmu-events/arch/arm64/fujitsu/monaka/hwpf.json Normal file
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[
{
"EventCode": "0x0230",
"EventName": "L1HWPF_STREAM_PF",
"BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher."
},
{
"EventCode": "0x0231",
"EventName": "L1HWPF_STRIDE_PF",
"BriefDescription": "This event counts stride prefetch requests to L1D cache generated by hardware prefetcher."
},
{
"EventCode": "0x0232",
"EventName": "L1HWPF_PFTGT_PF",
"BriefDescription": "This event counts LDS prefetch requests to L1D cache generated by hardware prefetcher."
},
{
"EventCode": "0x0234",
"EventName": "L2HWPF_STREAM_PF",
"BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefetcher."
},
{
"EventCode": "0x0235",
"EventName": "L2HWPF_STRIDE_PF",
"BriefDescription": "This event counts stride prefetch requests to L2 cache generated by hardware prefetcher."
},
{
"EventCode": "0x0237",
"EventName": "L2HWPF_OTHER",
"BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes."
},
{
"EventCode": "0x0238",
"EventName": "L3HWPF_STREAM_PF",
"BriefDescription": "This event counts streaming prefetch requests to L3 cache generated by hardware prefetcher."
},
{
"EventCode": "0x0239",
"EventName": "L3HWPF_STRIDE_PF",
"BriefDescription": "This event counts stride prefetch requests to L3 cache generated by hardware prefetcher."
},
{
"EventCode": "0x023B",
"EventName": "L3HWPF_OTHER",
"BriefDescription": "This event counts prefetch requests to L3 cache generated by the other causes."
},
{
"EventCode": "0x023C",
"EventName": "L1IHWPF_NEXTLINE_PF",
"BriefDescription": "This event counts next line's prefetch requests to L1I cache generated by hardware prefetcher."
}
]

113
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[
{
"ArchStdEvent": "L1D_CACHE_REFILL",
"BriefDescription": "This event counts operations that cause a refill of the L1D cache. See L1D_CACHE_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1D_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See L1D_CACHE of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1D_CACHE_WB",
"BriefDescription": "This event counts every write-back of data from the L1D cache. See L1D_CACHE_WB of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD",
"BriefDescription": "This event counts operations that cause a refill of the L1D cache that incurs additional latency."
},
{
"ArchStdEvent": "L1D_CACHE_RD",
"BriefDescription": "This event counts L1D CACHE caused by read access."
},
{
"ArchStdEvent": "L1D_CACHE_WR",
"BriefDescription": "This event counts L1D CACHE caused by write access."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR",
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access."
},
{
"EventCode": "0x0200",
"EventName": "L1D_CACHE_DM",
"BriefDescription": "This event counts L1D_CACHE caused by demand access."
},
{
"EventCode": "0x0201",
"EventName": "L1D_CACHE_DM_RD",
"BriefDescription": "This event counts L1D_CACHE caused by demand read access."
},
{
"EventCode": "0x0202",
"EventName": "L1D_CACHE_DM_WR",
"BriefDescription": "This event counts L1D_CACHE caused by demand write access."
},
{
"EventCode": "0x0208",
"EventName": "L1D_CACHE_REFILL_DM",
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
},
{
"EventCode": "0x0209",
"EventName": "L1D_CACHE_REFILL_DM_RD",
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access."
},
{
"EventCode": "0x020A",
"EventName": "L1D_CACHE_REFILL_DM_WR",
"BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand write access."
},
{
"EventCode": "0x020D",
"EventName": "L1D_CACHE_BTC",
"BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data cache, causing a coherence access to outside of the Level 1 caches of this PE."
},
{
"ArchStdEvent": "L1D_CACHE_MISS",
"BriefDescription": "This event counts demand access that misses in the Level 1 data cache, causing an access to outside of the Level 1 caches of this PE."
},
{
"ArchStdEvent": "L1D_CACHE_HWPRF",
"BriefDescription": "This event counts access counted by L1D_CACHE that is due to a hardware prefetch."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_HWPRF",
"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_CACHE_HIT_RD",
"BriefDescription": "This event counts demand read counted by L1D_CACHE_RD that hits in the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_CACHE_HIT_WR",
"BriefDescription": "This event counts demand write counted by L1D_CACHE_WR that hits in the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_CACHE_HIT",
"BriefDescription": "This event counts access counted by L1D_CACHE that hits in the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_LFB_HIT_RD",
"BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_LFB_HIT_WR",
"BriefDescription": "This event counts demand access counted by L1D_CACHE_HIT_WR that hits a cache line that is in the process of being loaded into the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_CACHE_PRF",
"BriefDescription": "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_PRF",
"BriefDescription": "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache."
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_PERCYC",
"BriefDescription": "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle."
}
]

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[
{
"ArchStdEvent": "L1I_CACHE_REFILL",
"BriefDescription": "This event counts operations that cause a refill of the L1I cache. See L1I_CACHE_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1I_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L1I cache. See L1I_CACHE of ARMv9 Reference Manual for more information."
},
{
"EventCode": "0x0207",
"EventName": "L1I_CACHE_DM_RD",
"BriefDescription": "This event counts L1I_CACHE caused by demand read access."
},
{
"EventCode": "0x020F",
"EventName": "L1I_CACHE_REFILL_DM_RD",
"BriefDescription": "This event counts L1I_CACHE_REFILL caused by demand read access."
},
{
"ArchStdEvent": "L1I_CACHE_LMISS",
"BriefDescription": "This event counts operations that cause a refill of the L1I cache that incurs additional latency."
},
{
"ArchStdEvent": "L1I_CACHE_HWPRF",
"BriefDescription": "This event counts access counted by L1I_CACHE that is due to a hardware prefetch."
},
{
"ArchStdEvent": "L1I_CACHE_REFILL_HWPRF",
"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache."
},
{
"ArchStdEvent": "L1I_CACHE_HIT_RD",
"BriefDescription": "This event counts demand fetch counted by L1I_CACHE_DM_RD that hits in the Level 1 instruction cache."
},
{
"ArchStdEvent": "L1I_CACHE_HIT",
"BriefDescription": "This event counts access counted by L1I_CACHE that hits in the Level 1 instruction cache."
},
{
"ArchStdEvent": "L1I_LFB_HIT_RD",
"BriefDescription": "This event counts demand access counted by L1I_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 instruction cache."
},
{
"ArchStdEvent": "L1I_CACHE_REFILL_PRF",
"BriefDescription": "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache."
},
{
"ArchStdEvent": "L1I_CACHE_REFILL_PERCYC",
"BriefDescription": "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
}
]

160
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[
{
"ArchStdEvent": "L2D_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L2D_CACHE of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL",
"BriefDescription": "This event counts operations that cause a refill of the L2 cache. See L2D_CACHE_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L2D_CACHE_WB",
"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace, non-temporal-store and DC ZVA."
},
{
"ArchStdEvent": "L2I_TLB_REFILL",
"BriefDescription": "This event counts operations that cause a TLB refill of the L2I TLB. See L2I_TLB_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L2I_TLB",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_TLB of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L2D_CACHE_RD",
"BriefDescription": "This event counts L2D CACHE caused by read access."
},
{
"ArchStdEvent": "L2D_CACHE_WR",
"BriefDescription": "This event counts L2D CACHE caused by write access."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD",
"BriefDescription": "This event counts L2D CACHE_REFILL caused by read access."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR",
"BriefDescription": "This event counts L2D CACHE_REFILL caused by write access."
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace."
},
{
"EventCode": "0x0300",
"EventName": "L2D_CACHE_DM",
"BriefDescription": "This event counts L2D_CACHE caused by demand access."
},
{
"EventCode": "0x0301",
"EventName": "L2D_CACHE_DM_RD",
"BriefDescription": "This event counts L2D_CACHE caused by demand read access."
},
{
"EventCode": "0x0302",
"EventName": "L2D_CACHE_DM_WR",
"BriefDescription": "This event counts L2D_CACHE caused by demand write access."
},
{
"EventCode": "0x0305",
"EventName": "L2D_CACHE_HWPRF_ADJACENT",
"BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch access."
},
{
"EventCode": "0x0308",
"EventName": "L2D_CACHE_REFILL_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access."
},
{
"EventCode": "0x0309",
"EventName": "L2D_CACHE_REFILL_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand read access."
},
{
"EventCode": "0x030A",
"EventName": "L2D_CACHE_REFILL_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write access."
},
{
"EventCode": "0x030B",
"EventName": "L2D_CACHE_REFILL_DM_WR_EXCL",
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write exclusive access."
},
{
"EventCode": "0x030C",
"EventName": "L2D_CACHE_REFILL_DM_WR_ATOM",
"BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write atomic access."
},
{
"EventCode": "0x030D",
"EventName": "L2D_CACHE_BTC",
"BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data and Level 2 caches, causing a coherence access to outside of the Level 1 and Level 2 caches of this PE."
},
{
"EventCode": "0x03B0",
"EventName": "L2D_CACHE_WB_VICTIM_CLEAN",
"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace where the data is clean. In this case, the data will usually be written to L3 cache."
},
{
"EventCode": "0x03B1",
"EventName": "L2D_CACHE_WB_NT",
"BriefDescription": "This event counts every write-back of data from the L2 cache caused by non-temporal-store."
},
{
"EventCode": "0x03B2",
"EventName": "L2D_CACHE_WB_DCZVA",
"BriefDescription": "This event counts every write-back of data from the L2 cache caused by DC ZVA."
},
{
"EventCode": "0x03B3",
"EventName": "L2D_CACHE_FB",
"BriefDescription": "This event counts every flush-back (drop) of data from the L2 cache."
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD",
"BriefDescription": "This event counts operations that cause a refill of the L2D cache that incurs additional latency."
},
{
"ArchStdEvent": "L2D_CACHE_MISS",
"BriefDescription": "This event counts demand access that misses in the Level 1 data and Level 2 caches, causing an access to outside of the Level 1 and Level 2 caches of this PE."
},
{
"ArchStdEvent": "L2D_CACHE_HWPRF",
"BriefDescription": "This event counts access counted by L2D_CACHE that is due to a hardware prefetch."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_HWPRF",
"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a refill of the Level 2 cache, or any Level 1 data and instruction cache of this PE, from outside of those caches."
},
{
"ArchStdEvent": "L2D_CACHE_HIT_RD",
"BriefDescription": "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 data cache."
},
{
"ArchStdEvent": "L2D_CACHE_HIT_WR",
"BriefDescription": "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 data cache."
},
{
"ArchStdEvent": "L2D_CACHE_HIT",
"BriefDescription": "This event counts access counted by L2D_CACHE that hits in the Level 2 data cache."
},
{
"ArchStdEvent": "L2D_LFB_HIT_RD",
"BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_RD that hits a recently fetched line in the Level 2 cache."
},
{
"ArchStdEvent": "L2D_LFB_HIT_WR",
"BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_WR that hits a recently fetched line in the Level 2 cache."
},
{
"ArchStdEvent": "L2D_CACHE_PRF",
"BriefDescription": "This event counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_PRF",
"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a refill of the Level 2 data cache from outside of the Level 1 data cache."
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_PERCYC",
"BriefDescription": "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle."
}
]

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[
{
"ArchStdEvent": "L3D_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as defined by the sum of L2D_CACHE_REFILL_L3D_CACHE and L2D_CACHE_WB_VICTIM_CLEAN events."
},
{
"ArchStdEvent": "L3D_CACHE_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events."
},
{
"EventCode": "0x0390",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L3 cache."
},
{
"EventCode": "0x0391",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access."
},
{
"EventCode": "0x0392",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access."
},
{
"EventCode": "0x0393",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access."
},
{
"EventCode": "0x0394",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access."
},
{
"EventCode": "0x0395",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access."
},
{
"EventCode": "0x0396",
"EventName": "L2D_CACHE_REFILL_L3D_MISS",
"BriefDescription": "This event counts operations that cause a miss of the L3 cache."
},
{
"EventCode": "0x0397",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access."
},
{
"EventCode": "0x0398",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access."
},
{
"EventCode": "0x0399",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access."
},
{
"EventCode": "0x039A",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access."
},
{
"EventCode": "0x039B",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access."
},
{
"EventCode": "0x039C",
"EventName": "L2D_CACHE_REFILL_L3D_HIT",
"BriefDescription": "This event counts operations that cause a hit of the L3 cache."
},
{
"EventCode": "0x039D",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access."
},
{
"EventCode": "0x039E",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand read access."
},
{
"EventCode": "0x039F",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand write access."
},
{
"EventCode": "0x03A0",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access."
},
{
"EventCode": "0x03A1",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access."
},
{
"EventCode": "0x03A2",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT",
"BriefDescription": "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer."
},
{
"EventCode": "0x03A3",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access."
},
{
"EventCode": "0x03A4",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access."
},
{
"EventCode": "0x03A5",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access."
},
{
"EventCode": "0x03A6",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_L_MEM",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests."
},
{
"EventCode": "0x03A7",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_MEM",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests."
},
{
"EventCode": "0x03A8",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_L_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests."
},
{
"EventCode": "0x03A9",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests."
},
{
"EventCode": "0x03AA",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L3",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests."
},
{
"EventCode": "0x03AB",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests."
},
{
"EventCode": "0x03AC",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L3",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests."
},
{
"ArchStdEvent": "L3D_CACHE_LMISS_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
}
]

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[
{
"ArchStdEvent": "LL_CACHE_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events."
},
{
"ArchStdEvent": "LL_CACHE_MISS_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
}
]

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[
{
"ArchStdEvent": "MEM_ACCESS",
"BriefDescription": "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LDST_SPEC events."
},
{
"ArchStdEvent": "MEM_ACCESS_RD",
"BriefDescription": "This event counts architecturally executed memory-reading instructions, as defined by the LD_SPEC events."
}
]

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[
{
"EventCode": "0x01A0",
"EventName": "EAGA_VAL",
"BriefDescription": "This event counts valid cycles of EAGA pipeline."
},
{
"EventCode": "0x01A1",
"EventName": "EAGB_VAL",
"BriefDescription": "This event counts valid cycles of EAGB pipeline."
},
{
"EventCode": "0x01A3",
"EventName": "PRX_VAL",
"BriefDescription": "This event counts valid cycles of PRX pipeline."
},
{
"EventCode": "0x01A4",
"EventName": "EXA_VAL",
"BriefDescription": "This event counts valid cycles of EXA pipeline."
},
{
"EventCode": "0x01A5",
"EventName": "EXB_VAL",
"BriefDescription": "This event counts valid cycles of EXB pipeline."
},
{
"EventCode": "0x01A6",
"EventName": "EXC_VAL",
"BriefDescription": "This event counts valid cycles of EXC pipeline."
},
{
"EventCode": "0x01A7",
"EventName": "EXD_VAL",
"BriefDescription": "This event counts valid cycles of EXD pipeline."
},
{
"EventCode": "0x01A8",
"EventName": "FLA_VAL",
"BriefDescription": "This event counts valid cycles of FLA pipeline."
},
{
"EventCode": "0x01A9",
"EventName": "FLB_VAL",
"BriefDescription": "This event counts valid cycles of FLB pipeline."
},
{
"EventCode": "0x01AA",
"EventName": "STEA_VAL",
"BriefDescription": "This event counts valid cycles of STEA pipeline."
},
{
"EventCode": "0x01AB",
"EventName": "STEB_VAL",
"BriefDescription": "This event counts valid cycles of STEB pipeline."
},
{
"EventCode": "0x01AC",
"EventName": "STFL_VAL",
"BriefDescription": "This event counts valid cycles of STFL pipeline."
},
{
"EventCode": "0x01AD",
"EventName": "STPX_VAL",
"BriefDescription": "This event counts valid cycles of STPX pipeline."
},
{
"EventCode": "0x01B0",
"EventName": "FLA_VAL_PRD_CNT",
"BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 32 when all bits are 1."
},
{
"EventCode": "0x01B1",
"EventName": "FLB_VAL_PRD_CNT",
"BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 32 when all bits are 1."
},
{
"EventCode": "0x01B2",
"EventName": "FLA_VAL_FOR_PRD",
"BriefDescription": "This event counts valid cycles of FLA pipeline."
},
{
"EventCode": "0x01B3",
"EventName": "FLB_VAL_FOR_PRD",
"BriefDescription": "This event counts valid cycles of FLB pipeline."
},
{
"EventCode": "0x0240",
"EventName": "L1_PIPE0_VAL",
"BriefDescription": "This event counts valid cycles of L1D cache pipeline#0."
},
{
"EventCode": "0x0241",
"EventName": "L1_PIPE1_VAL",
"BriefDescription": "This event counts valid cycles of L1D cache pipeline#1."
},
{
"EventCode": "0x0242",
"EventName": "L1_PIPE2_VAL",
"BriefDescription": "This event counts valid cycles of L1D cache pipeline#2."
},
{
"EventCode": "0x0250",
"EventName": "L1_PIPE0_COMP",
"BriefDescription": "This event counts completed requests in L1D cache pipeline#0."
},
{
"EventCode": "0x0251",
"EventName": "L1_PIPE1_COMP",
"BriefDescription": "This event counts completed requests in L1D cache pipeline#1."
},
{
"EventCode": "0x025A",
"EventName": "L1_PIPE_ABORT_STLD_INTLK",
"BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock."
},
{
"EventCode": "0x026C",
"EventName": "L1I_PIPE_COMP",
"BriefDescription": "This event counts completed requests in L1I cache pipeline."
},
{
"EventCode": "0x026D",
"EventName": "L1I_PIPE_VAL",
"BriefDescription": "This event counts valid cycles of L1I cache pipeline."
},
{
"EventCode": "0x0278",
"EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE",
"BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1."
},
{
"EventCode": "0x0279",
"EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE",
"BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1."
},
{
"EventCode": "0x02A0",
"EventName": "L1_PIPE0_VAL_IU_NOT_SEC0",
"BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0."
},
{
"EventCode": "0x02A1",
"EventName": "L1_PIPE1_VAL_IU_NOT_SEC0",
"BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0."
},
{
"EventCode": "0x02B0",
"EventName": "L1_PIPE_COMP_GATHER_2FLOW",
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined."
},
{
"EventCode": "0x02B1",
"EventName": "L1_PIPE_COMP_GATHER_1FLOW",
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined."
},
{
"EventCode": "0x02B2",
"EventName": "L1_PIPE_COMP_GATHER_0FLOW",
"BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0."
},
{
"EventCode": "0x02B3",
"EventName": "L1_PIPE_COMP_SCATTER_1FLOW",
"BriefDescription": "This event counts the number of flows of the scatter instructions."
},
{
"EventCode": "0x02B8",
"EventName": "L1_PIPE0_COMP_PRD_CNT",
"BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 64 when all bits are 1."
},
{
"EventCode": "0x02B9",
"EventName": "L1_PIPE1_COMP_PRD_CNT",
"BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 64 when all bits are 1."
},
{
"EventCode": "0x0330",
"EventName": "L2_PIPE_VAL",
"BriefDescription": "This event counts valid cycles of L2 cache pipeline."
},
{
"EventCode": "0x0350",
"EventName": "L2_PIPE_COMP_ALL",
"BriefDescription": "This event counts completed requests in L2 cache pipeline."
},
{
"EventCode": "0x0370",
"EventName": "L2_PIPE_COMP_PF_L2MIB_MCH",
"BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access."
},
{
"ArchStdEvent": "STALL_FRONTEND_TLB",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the instruction TLB."
},
{
"ArchStdEvent": "STALL_BACKEND_TLB",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in the data TLB."
},
{
"ArchStdEvent": "STALL_BACKEND_ST",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is stalled waiting for a store."
},
{
"ArchStdEvent": "STALL_BACKEND_ILOCK",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but at least one is not ready to be sent to the backend because of an input dependency."
}
]

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[
{
"ArchStdEvent": "PMU_OVFS",
"BriefDescription": "This event counts the event generated each time one of the condition occurs described in Arm Architecture Reference Manual for A-profile architecture. This event is only for output to the trace unit."
},
{
"ArchStdEvent": "PMU_HOVFS",
"BriefDescription": "This event counts the event generated each time an event is counted by an event counter <n> and all of the condition occur described in Arm Architecture Reference Manual for A-profile architecture. This event is only for output to the trace unit."
}
]

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[
{
"ArchStdEvent": "SW_INCR",
"BriefDescription": "This event counts on writes to the PMSWINC register."
},
{
"ArchStdEvent": "INST_RETIRED",
"BriefDescription": "This event counts every architecturally executed instruction."
},
{
"ArchStdEvent": "CID_WRITE_RETIRED",
"BriefDescription": "This event counts every write to CONTEXTIDR."
},
{
"ArchStdEvent": "BR_RETIRED",
"BriefDescription": "This event counts architecturally executed branch instruction."
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED",
"BriefDescription": "This event counts architecturally executed branch instruction which was mispredicted."
},
{
"ArchStdEvent": "OP_RETIRED",
"BriefDescription": "This event counts every architecturally executed micro-operation."
},
{
"ArchStdEvent": "UOP_RETIRED",
"BriefDescription": "This event counts micro-operation that would be executed in a Simple sequential execution of the program."
}
]

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[
{
"ArchStdEvent": "BR_MIS_PRED",
"BriefDescription": "This event counts each correction to the predicted program flow that occurs because of a misprediction from, or no prediction from, the branch prediction resources and that relates to instructions that the branch prediction resources are capable of predicting."
},
{
"ArchStdEvent": "BR_PRED",
"BriefDescription": "This event counts every branch or other change in the program flow that the branch prediction resources are capable of predicting."
},
{
"ArchStdEvent": "INST_SPEC",
"BriefDescription": "This event counts every architecturally executed instruction."
},
{
"ArchStdEvent": "OP_SPEC",
"BriefDescription": "This event counts every speculatively executed micro-operation."
},
{
"ArchStdEvent": "LDREX_SPEC",
"BriefDescription": "This event counts architecturally executed load-exclusive instructions."
},
{
"ArchStdEvent": "STREX_SPEC",
"BriefDescription": "This event counts architecturally executed store-exclusive instructions."
},
{
"ArchStdEvent": "LD_SPEC",
"BriefDescription": "This event counts architecturally executed memory-reading instructions, as defined by the LD_RETIRED event."
},
{
"ArchStdEvent": "ST_SPEC",
"BriefDescription": "This event counts architecturally executed memory-writing instructions, as defined by the ST_RETIRED event. This event counts DCZVA as a store operation."
},
{
"ArchStdEvent": "LDST_SPEC",
"BriefDescription": "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LD_RETIRED and ST_RETIRED events."
},
{
"ArchStdEvent": "DP_SPEC",
"BriefDescription": "This event counts architecturally executed integer data-processing instructions. See DP_SPEC of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "ASE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD data-processing instructions."
},
{
"ArchStdEvent": "VFP_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point data-processing instructions."
},
{
"ArchStdEvent": "PC_WRITE_SPEC",
"BriefDescription": "This event counts only software changes of the PC that defined by the instruction architecturally executed, condition code check pass, software change of the PC event."
},
{
"ArchStdEvent": "CRYPTO_SPEC",
"BriefDescription": "This event counts architecturally executed cryptographic instructions, except PMULL and VMULL."
},
{
"ArchStdEvent": "BR_IMMED_SPEC",
"BriefDescription": "This event counts architecturally executed immediate branch instructions."
},
{
"ArchStdEvent": "BR_RETURN_SPEC",
"BriefDescription": "This event counts architecturally executed procedure return operations that defined by the BR_RETURN_RETIRED event."
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC",
"BriefDescription": "This event counts architecturally executed indirect branch instructions that includes software change of the PC other than exception-generating instructions and immediate branch instructions."
},
{
"ArchStdEvent": "ISB_SPEC",
"BriefDescription": "This event counts architecturally executed Instruction Synchronization Barrier instructions."
},
{
"ArchStdEvent": "DSB_SPEC",
"BriefDescription": "This event counts architecturally executed Data Synchronization Barrier instructions."
},
{
"ArchStdEvent": "DMB_SPEC",
"BriefDescription": "This event counts architecturally executed Data Memory Barrier instructions, excluding the implied barrier operations of load/store operations with release consistency semantics."
},
{
"ArchStdEvent": "CSDB_SPEC",
"BriefDescription": "This event counts speculatively executed control speculation barrier instructions."
},
{
"EventCode": "0x0108",
"EventName": "PRD_SPEC",
"BriefDescription": "This event counts architecturally executed operations that using predicate register."
},
{
"EventCode": "0x0109",
"EventName": "IEL_SPEC",
"BriefDescription": "This event counts architecturally executed inter-element manipulation operations."
},
{
"EventCode": "0x010A",
"EventName": "IREG_SPEC",
"BriefDescription": "This event counts architecturally executed inter-register manipulation operations."
},
{
"EventCode": "0x011A",
"EventName": "BC_LD_SPEC",
"BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations."
},
{
"EventCode": "0x011B",
"EventName": "DCZVA_SPEC",
"BriefDescription": "This event counts architecturally executed zero blocking operations due to the DC ZVA instruction."
},
{
"EventCode": "0x0121",
"EventName": "EFFECTIVE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction."
},
{
"EventCode": "0x0123",
"EventName": "PRE_INDEX_SPEC",
"BriefDescription": "This event counts architecturally executed operations that uses pre-index as its addressing mode."
},
{
"EventCode": "0x0124",
"EventName": "POST_INDEX_SPEC",
"BriefDescription": "This event counts architecturally executed operations that uses post-index as its addressing mode."
},
{
"EventCode": "0x0139",
"EventName": "UOP_SPLIT",
"BriefDescription": "This event counts the occurrence count of the micro-operation split."
},
{
"ArchStdEvent": "ASE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD operations."
},
{
"ArchStdEvent": "INT_SPEC",
"BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Integer instructions section of ARMv9 Reference Manual."
},
{
"ArchStdEvent": "INT_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed integer divide operation."
},
{
"ArchStdEvent": "INT_DIV64_SPEC",
"BriefDescription": "This event counts architecturally executed 64-bit integer divide operation."
},
{
"ArchStdEvent": "INT_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed integer multiply operation."
},
{
"ArchStdEvent": "INT_MUL64_SPEC",
"BriefDescription": "This event counts architecturally executed integer 64-bit x 64-bit multiply operation."
},
{
"ArchStdEvent": "INT_MULH64_SPEC",
"BriefDescription": "This event counts architecturally executed integer 64-bit x 64-bit multiply returning high part operation."
},
{
"ArchStdEvent": "NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed non-floating-point operations."
},
{
"ArchStdEvent": "INT_SCALE_OPS_SPEC",
"BriefDescription": "This event counts each integer ALU operation counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction."
},
{
"ArchStdEvent": "INT_FIXED_OPS_SPEC",
"BriefDescription": "This event counts each integer ALU operation counted by INT_SPEC that is not counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction."
}
]

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[
{
"ArchStdEvent": "STALL_FRONTEND",
"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because there are no operations available to issue for this PE from the frontend."
},
{
"ArchStdEvent": "STALL_BACKEND",
"BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operations."
},
{
"ArchStdEvent": "STALL",
"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit."
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND",
"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the backend."
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND",
"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the frontend."
},
{
"ArchStdEvent": "STALL_SLOT",
"BriefDescription": "This event counts every cycle that no instruction or operation Slot was dispatched from decode unit."
},
{
"ArchStdEvent": "STALL_BACKEND_MEM",
"BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to memory stall."
},
{
"ArchStdEvent": "STALL_FRONTEND_MEMBOUND",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when no instructions are delivered from the memory system."
},
{
"ArchStdEvent": "STALL_FRONTEND_L1I",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the first level of instruction cache."
},
{
"ArchStdEvent": "STALL_FRONTEND_L2I",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the second level of instruction cache."
},
{
"ArchStdEvent": "STALL_FRONTEND_MEM",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the last level of instruction cache within the PE clock domain or a non-cacheable instruction fetch in progress."
},
{
"ArchStdEvent": "STALL_FRONTEND_CPUBOUND",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when the frontend is stalled on a frontend processor resource, not including memory."
},
{
"ArchStdEvent": "STALL_FRONTEND_FLOW",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is stalled on unavailability of prediction flow resources."
},
{
"ArchStdEvent": "STALL_FRONTEND_FLUSH",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is recovering from a pipeline flush."
},
{
"ArchStdEvent": "STALL_FRONTEND_RENAME",
"BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available."
},
{
"ArchStdEvent": "STALL_BACKEND_MEMBOUND",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is waiting for a memory access to complete."
},
{
"ArchStdEvent": "STALL_BACKEND_L1D",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L1D cache."
},
{
"ArchStdEvent": "STALL_BACKEND_L2D",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2D cache."
},
{
"ArchStdEvent": "STALL_BACKEND_CPUBOUND",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is stalled on a processor resource, not including memory."
},
{
"ArchStdEvent": "STALL_BACKEND_BUSY",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but the backend is not able to accept an operation because an execution unit is busy."
},
{
"ArchStdEvent": "STALL_BACKEND_RENAME",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available."
},
{
"ArchStdEvent": "STALL_BACKEND_ATOMIC",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing an Atomic operation."
},
{
"ArchStdEvent": "STALL_BACKEND_MEMCPYSET",
"BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing a Memory Copy or Set instruction."
}
]

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[
{
"ArchStdEvent": "SIMD_INST_RETIRED",
"BriefDescription": "This event counts architecturally executed SIMD instructions, excluding the Advanced SIMD scalar instructions and the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual."
},
{
"ArchStdEvent": "SVE_INST_RETIRED",
"BriefDescription": "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual."
},
{
"ArchStdEvent": "SVE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual."
},
{
"ArchStdEvent": "ASE_SVE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE operations."
},
{
"ArchStdEvent": "UOP_SPEC",
"BriefDescription": "This event counts all architecturally executed micro-operations."
},
{
"ArchStdEvent": "SVE_MATH_SPEC",
"BriefDescription": "This event counts architecturally executed math function operations due to the SVE FTSMUL, FTMAD, FTSSEL, and FEXPA instructions."
},
{
"ArchStdEvent": "FP_SPEC",
"BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Floating-point instructions section of ARMv9 Reference Manual."
},
{
"ArchStdEvent": "FP_FMA_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations."
},
{
"ArchStdEvent": "FP_RECPE_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point reciprocal estimate operations due to the Advanced SIMD scalar, Advanced SIMD vector, and SVE FRECPE and FRSQRTE instructions."
},
{
"ArchStdEvent": "FP_CVT_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point convert operations due to the scalar, Advanced SIMD, and SVE floating-point conversion instructions listed in Floating-point conversions section of ARMv9 Reference Manual."
},
{
"ArchStdEvent": "ASE_INT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD integer operations."
},
{
"ArchStdEvent": "SVE_INT_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer operations."
},
{
"ArchStdEvent": "ASE_SVE_INT_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer operations."
},
{
"ArchStdEvent": "SVE_INT_DIV_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer divide operation."
},
{
"ArchStdEvent": "SVE_INT_DIV64_SPEC",
"BriefDescription": "This event counts architecturally executed SVE 64-bit integer divide operation."
},
{
"ArchStdEvent": "ASE_INT_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD integer multiply operation."
},
{
"ArchStdEvent": "SVE_INT_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer multiply operation."
},
{
"ArchStdEvent": "ASE_SVE_INT_MUL_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer multiply operations."
},
{
"ArchStdEvent": "SVE_INT_MUL64_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply operation."
},
{
"ArchStdEvent": "SVE_INT_MULH64_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operations."
},
{
"ArchStdEvent": "ASE_NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD non-floating-point operations."
},
{
"ArchStdEvent": "SVE_NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed SVE non-floating-point operations."
},
{
"ArchStdEvent": "ASE_SVE_NONFP_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE non-floating-point operations."
},
{
"ArchStdEvent": "ASE_INT_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD integer reduction operation."
},
{
"ArchStdEvent": "SVE_INT_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed SVE integer reduction operation."
},
{
"ArchStdEvent": "ASE_SVE_INT_VREDUCE_SPEC",
"BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE integer reduction operations."
},
{
"ArchStdEvent": "SVE_PERM_SPEC",
"BriefDescription": "This event counts architecturally executed vector or predicate permute operation."
},
{
"ArchStdEvent": "SVE_XPIPE_Z2R_SPEC",
"BriefDescription": "This event counts architecturally executed vector to general-purpose scalar cross-pipeline transfer operation."
},
{
"ArchStdEvent": "SVE_XPIPE_R2Z_SPEC",
"BriefDescription": "This event counts architecturally executed general-purpose scalar to vector cross-pipeline transfer operation."
},
{
"ArchStdEvent": "SVE_PGEN_SPEC",
"BriefDescription": "This event counts architecturally executed predicate-generating operation."
},
{
"ArchStdEvent": "SVE_PGEN_FLG_SPEC",
"BriefDescription": "This event counts architecturally executed predicate-generating operation that sets condition flags."
},
{
"ArchStdEvent": "SVE_PPERM_SPEC",
"BriefDescription": "This event counts architecturally executed predicate permute operation."
},
{
"ArchStdEvent": "SVE_PRED_SPEC",
"BriefDescription": "This event counts architecturally executed SIMD data-processing and load/store operations due to SVE instructions with a Governing predicate operand that determines the Active elements."
},
{
"ArchStdEvent": "SVE_MOVPRFX_SPEC",
"BriefDescription": "This event counts architecturally executed operations due to MOVPRFX instructions, whether or not they were fused with the prefixed instruction."
},
{
"ArchStdEvent": "SVE_MOVPRFX_Z_SPEC",
"BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses zeroing predication."
},
{
"ArchStdEvent": "SVE_MOVPRFX_M_SPEC",
"BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses merging predication."
},
{
"ArchStdEvent": "SVE_MOVPRFX_U_SPEC",
"BriefDescription": "This event counts architecturally executed operations due to MOVPRFX instructions that were not fused with the prefixed instruction."
},
{
"ArchStdEvent": "ASE_SVE_LD_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions."
},
{
"ArchStdEvent": "ASE_SVE_ST_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions."
},
{
"ArchStdEvent": "PRF_SPEC",
"BriefDescription": "This event counts architecturally executed prefetch operations due to scalar PRFM, PRFUM and SVE PRF instructions."
},
{
"ArchStdEvent": "BASE_LD_REG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to an instruction that loads a general-purpose register."
},
{
"ArchStdEvent": "BASE_ST_REG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to an instruction that stores a general-purpose register, excluding the DC ZVA instruction."
},
{
"ArchStdEvent": "SVE_LDR_REG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to an SVE LDR instruction."
},
{
"ArchStdEvent": "SVE_STR_REG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to an SVE STR instruction."
},
{
"ArchStdEvent": "SVE_LDR_PREG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to an SVE LDR (predicate) instruction."
},
{
"ArchStdEvent": "SVE_STR_PREG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to an SVE STR (predicate) instruction."
},
{
"ArchStdEvent": "SVE_PRF_CONTIG_SPEC",
"BriefDescription": "This event counts architecturally executed operations that prefetch memory due to an SVE predicated single contiguous element prefetch instruction."
},
{
"ArchStdEvent": "SVE_LDNT_CONTIG_SPEC",
"BriefDescription": "This event counts architecturally executed operation that reads from memory with a non-temporal hint due to an SVE non-temporal contiguous element load instruction."
},
{
"ArchStdEvent": "SVE_STNT_CONTIG_SPEC",
"BriefDescription": "This event counts architecturally executed operation that writes to memory with a non-temporal hint due to an SVE non-temporal contiguous element store instruction."
},
{
"ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions."
},
{
"ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions."
},
{
"ArchStdEvent": "SVE_LD_GATHER_SPEC",
"BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE non-contiguous gather-load instructions."
},
{
"ArchStdEvent": "SVE_ST_SCATTER_SPEC",
"BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE non-contiguous scatter-store instructions."
},
{
"ArchStdEvent": "SVE_PRF_GATHER_SPEC",
"BriefDescription": "This event counts architecturally executed operations that prefetch memory due to SVE non-contiguous gather-prefetch instructions."
},
{
"ArchStdEvent": "SVE_LDFF_SPEC",
"BriefDescription": "This event counts architecturally executed memory read operations due to SVE First-fault and Non-fault load instructions."
},
{
"ArchStdEvent": "FP_HP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE half-precision arithmetic operations. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_HP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operations. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_SP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE single-precision arithmetic operations. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_SP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operations. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_DP_SCALE_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed SVE double-precision arithmetic operations. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC."
},
{
"ArchStdEvent": "FP_DP_FIXED_OPS_SPEC",
"BriefDescription": "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operations. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
},
{
"ArchStdEvent": "ASE_SVE_INT_DOT_SPEC",
"BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer dot-product operation."
},
{
"ArchStdEvent": "ASE_SVE_INT_MMLA_SPEC",
"BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer matrix multiply operation."
}
]

362
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/tlb.json Normal file
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@ -0,0 +1,362 @@
[
{
"ArchStdEvent": "L1I_TLB_REFILL",
"BriefDescription": "This event counts operations that cause a TLB refill of the L1I TLB. See L1I_TLB_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1D_TLB_REFILL",
"BriefDescription": "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_TLB_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1D_TLB",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_TLB of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L1I_TLB",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_TLB of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L2D_TLB_REFILL",
"BriefDescription": "This event counts operations that cause a TLB refill of the L2D TLB. See L2D_TLB_REFILL of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "L2D_TLB",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_TLB of ARMv9 Reference Manual for more information."
},
{
"ArchStdEvent": "DTLB_WALK",
"BriefDescription": "This event counts data TLB access with at least one translation table walk."
},
{
"ArchStdEvent": "ITLB_WALK",
"BriefDescription": "This event counts instruction TLB access with at least one translation table walk."
},
{
"EventCode": "0x0C00",
"EventName": "L1I_TLB_4K",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page."
},
{
"EventCode": "0x0C01",
"EventName": "L1I_TLB_64K",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page."
},
{
"EventCode": "0x0C02",
"EventName": "L1I_TLB_2M",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page."
},
{
"EventCode": "0x0C03",
"EventName": "L1I_TLB_32M",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page."
},
{
"EventCode": "0x0C04",
"EventName": "L1I_TLB_512M",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 512MB page."
},
{
"EventCode": "0x0C05",
"EventName": "L1I_TLB_1G",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 1GB page."
},
{
"EventCode": "0x0C06",
"EventName": "L1I_TLB_16G",
"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 16GB page."
},
{
"EventCode": "0x0C08",
"EventName": "L1D_TLB_4K",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 4KB page."
},
{
"EventCode": "0x0C09",
"EventName": "L1D_TLB_64K",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 64KB page."
},
{
"EventCode": "0x0C0A",
"EventName": "L1D_TLB_2M",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 2MB page."
},
{
"EventCode": "0x0C0B",
"EventName": "L1D_TLB_32M",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 32MB page."
},
{
"EventCode": "0x0C0C",
"EventName": "L1D_TLB_512M",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 512MB page."
},
{
"EventCode": "0x0C0D",
"EventName": "L1D_TLB_1G",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 1GB page."
},
{
"EventCode": "0x0C0E",
"EventName": "L1D_TLB_16G",
"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 16GB page."
},
{
"EventCode": "0x0C10",
"EventName": "L1I_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 4KB page."
},
{
"EventCode": "0x0C11",
"EventName": "L1I_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 64KB page."
},
{
"EventCode": "0x0C12",
"EventName": "L1I_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 2MB page."
},
{
"EventCode": "0x0C13",
"EventName": "L1I_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 32MB page."
},
{
"EventCode": "0x0C14",
"EventName": "L1I_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 512MB page."
},
{
"EventCode": "0x0C15",
"EventName": "L1I_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 1GB page."
},
{
"EventCode": "0x0C16",
"EventName": "L1I_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1I in 16GB page."
},
{
"EventCode": "0x0C18",
"EventName": "L1D_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 4KB page."
},
{
"EventCode": "0x0C19",
"EventName": "L1D_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 64KB page."
},
{
"EventCode": "0x0C1A",
"EventName": "L1D_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 2MB page."
},
{
"EventCode": "0x0C1B",
"EventName": "L1D_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 32MB page."
},
{
"EventCode": "0x0C1C",
"EventName": "L1D_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 512MB page."
},
{
"EventCode": "0x0C1D",
"EventName": "L1D_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 1GB page."
},
{
"EventCode": "0x0C1E",
"EventName": "L1D_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L1D in 16GB page."
},
{
"EventCode": "0x0C20",
"EventName": "L2I_TLB_4K",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 4KB page."
},
{
"EventCode": "0x0C21",
"EventName": "L2I_TLB_64K",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 64KB page."
},
{
"EventCode": "0x0C22",
"EventName": "L2I_TLB_2M",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 2MB page."
},
{
"EventCode": "0x0C23",
"EventName": "L2I_TLB_32M",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 32MB page."
},
{
"EventCode": "0x0C24",
"EventName": "L2I_TLB_512M",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 512MB page."
},
{
"EventCode": "0x0C25",
"EventName": "L2I_TLB_1G",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 1GB page."
},
{
"EventCode": "0x0C26",
"EventName": "L2I_TLB_16G",
"BriefDescription": "This event counts operations that cause a TLB access to the L2I in 16GB page."
},
{
"EventCode": "0x0C28",
"EventName": "L2D_TLB_4K",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 4KB page."
},
{
"EventCode": "0x0C29",
"EventName": "L2D_TLB_64K",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 64KB page."
},
{
"EventCode": "0x0C2A",
"EventName": "L2D_TLB_2M",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 2MB page."
},
{
"EventCode": "0x0C2B",
"EventName": "L2D_TLB_32M",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 32MB page."
},
{
"EventCode": "0x0C2C",
"EventName": "L2D_TLB_512M",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 512MB page."
},
{
"EventCode": "0x0C2D",
"EventName": "L2D_TLB_1G",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 1GB page."
},
{
"EventCode": "0x0C2E",
"EventName": "L2D_TLB_16G",
"BriefDescription": "This event counts operations that cause a TLB access to the L2D in 16GB page."
},
{
"EventCode": "0x0C30",
"EventName": "L2I_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2Iin 4KB page."
},
{
"EventCode": "0x0C31",
"EventName": "L2I_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 64KB page."
},
{
"EventCode": "0x0C32",
"EventName": "L2I_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 2MB page."
},
{
"EventCode": "0x0C33",
"EventName": "L2I_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 32MB page."
},
{
"EventCode": "0x0C34",
"EventName": "L2I_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 512MB page."
},
{
"EventCode": "0x0C35",
"EventName": "L2I_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 1GB page."
},
{
"EventCode": "0x0C36",
"EventName": "L2I_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2I in 16GB page."
},
{
"EventCode": "0x0C38",
"EventName": "L2D_TLB_REFILL_4K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 4KB page."
},
{
"EventCode": "0x0C39",
"EventName": "L2D_TLB_REFILL_64K",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 64KB page."
},
{
"EventCode": "0x0C3A",
"EventName": "L2D_TLB_REFILL_2M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 2MB page."
},
{
"EventCode": "0x0C3B",
"EventName": "L2D_TLB_REFILL_32M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 32MB page."
},
{
"EventCode": "0x0C3C",
"EventName": "L2D_TLB_REFILL_512M",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 512MB page."
},
{
"EventCode": "0x0C3D",
"EventName": "L2D_TLB_REFILL_1G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 1GB page."
},
{
"EventCode": "0x0C3E",
"EventName": "L2D_TLB_REFILL_16G",
"BriefDescription": "This event counts operations that cause a TLB refill to the L2D in 16GB page."
},
{
"ArchStdEvent": "DTLB_WALK_PERCYC",
"BriefDescription": "This event counts the number of DTLB_WALK events in progress on each Processor cycle."
},
{
"ArchStdEvent": "ITLB_WALK_PERCYC",
"BriefDescription": "This event counts the number of ITLB_WALK events in progress on each Processor cycle."
},
{
"ArchStdEvent": "DTLB_STEP",
"BriefDescription": "This event counts translation table walk access made by a refill of the data TLB."
},
{
"ArchStdEvent": "ITLB_STEP",
"BriefDescription": "This event counts translation table walk access made by a refill of the instruction TLB."
},
{
"ArchStdEvent": "DTLB_WALK_LARGE",
"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a large page size."
},
{
"ArchStdEvent": "ITLB_WALK_LARGE",
"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a large page size."
},
{
"ArchStdEvent": "DTLB_WALK_SMALL",
"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a small page size."
},
{
"ArchStdEvent": "ITLB_WALK_SMALL",
"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a small page size."
},
{
"ArchStdEvent": "DTLB_WALK_BLOCK",
"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a Block."
},
{
"ArchStdEvent": "ITLB_WALK_BLOCK",
"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a Block."
},
{
"ArchStdEvent": "DTLB_WALK_PAGE",
"BriefDescription": "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a Page."
},
{
"ArchStdEvent": "ITLB_WALK_PAGE",
"BriefDescription": "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a Page."
}
]

18
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/trace.json Normal file
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@ -0,0 +1,18 @@
[
{
"ArchStdEvent": "TRB_WRAP",
"BriefDescription": "This event counts the event generated each time the current write pointer is wrapped to the base pointer."
},
{
"ArchStdEvent": "TRB_TRIG",
"BriefDescription": "This event counts the event generated when a Trace Buffer Extension Trigger Event occurs."
},
{
"ArchStdEvent": "TRCEXTOUT0",
"BriefDescription": "This event counts the event generated each time an event is signaled by the trace unit external event 0."
},
{
"ArchStdEvent": "CTI_TRIGOUT4",
"BriefDescription": "This event counts the event generated each time an event is signaled on CTI output trigger 4."
}
]

1
tools/perf/pmu-events/arch/arm64/mapfile.csv
View File

@ -39,6 +39,7 @@
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000460f0010,v1,fujitsu/a64fx,core
0x00000000460f0030,v1,fujitsu/monaka,core
0x00000000480fd010,v1,hisilicon/hip08,core
0x00000000500f0000,v1,ampere/emag,core
0x00000000c00fac30,v1,ampere/ampereone,core

1 # Format:
39 0x00000000420f5160,v1,cavium/thunderx2,core
40 0x00000000430f0af0,v1,cavium/thunderx2,core
41 0x00000000460f0010,v1,fujitsu/a64fx,core
42 0x00000000460f0030,v1,fujitsu/monaka,core
43 0x00000000480fd010,v1,hisilicon/hip08,core
44 0x00000000500f0000,v1,ampere/emag,core
45 0x00000000c00fac30,v1,ampere/ampereone,core

5
tools/perf/pmu-events/arch/arm64/recommended.json
View File

@ -317,6 +317,11 @@
"EventName": "DMB_SPEC",
"BriefDescription": "Barrier speculatively executed, DMB"
},
{
"EventCode": "0x7F",
"EventName": "CSDB_SPEC",
"BriefDescription": "Barrier Speculatively executed, CSDB."
},
{
"PublicDescription": "Exception taken, Other synchronous",
"EventCode": "0x81",