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ASoC: fsl_xcvr: get channel status data when PHY is not exists
[ Upstream commitca592e2065
] There is no PHY for the XCVR module on i.MX93, the channel status needs to be obtained from FSL_XCVR_RX_CS_DATA_* registers. And channel status acknowledge (CSA) bit should be set once channel status is processed. Fixes:e240b9329a
("ASoC: fsl_xcvr: Add support for i.MX93 platform") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/20250710030405.3370671-2-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1197,6 +1197,26 @@ static irqreturn_t irq0_isr(int irq, void *devid)
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/* clear CS control register */
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memset_io(reg_ctrl, 0, sizeof(val));
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}
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} else {
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regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0,
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(u32 *)&xcvr->rx_iec958.status[0]);
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regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1,
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(u32 *)&xcvr->rx_iec958.status[4]);
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regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2,
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(u32 *)&xcvr->rx_iec958.status[8]);
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regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3,
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(u32 *)&xcvr->rx_iec958.status[12]);
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regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4,
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(u32 *)&xcvr->rx_iec958.status[16]);
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regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5,
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(u32 *)&xcvr->rx_iec958.status[20]);
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for (i = 0; i < 6; i++) {
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val = *(u32 *)(xcvr->rx_iec958.status + i * 4);
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*(u32 *)(xcvr->rx_iec958.status + i * 4) =
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bitrev32(val);
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}
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regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL,
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FSL_XCVR_RX_DPTH_CTRL_CSA);
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}
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}
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if (isr & FSL_XCVR_IRQ_NEW_UD) {
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