The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro.
Utilize them instead of open coded variants in the driver.
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231204160033.1872569-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
New drivers:
- Realtek RTD family pin control driver and RTD1619B,
RTD1319D and RTD1315E subdrivers.
- Nuvoton NPCM8xx combined pin control and GPIO driver.
- Amlogic T7 pin control driver.
- Renesas RZ/G3S pin control driver.
Improvements:
- A number of additional UART groups added to the Mediatek
MT7981 driver.
- MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125
and SDM660.
- Extra GPIO banks for the Sunxi H616.
- MLSP I2C6 function support in Qualcomm MSM8226.
- Some __counted_by() annotations for dynamic arrays.
- Ongoing work to make remove() return void.
- LSBC groups and functions in the Renesas R8A7778.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmVEp+oACgkQQRCzN7AZ
XXPmqg/7BX2u2/1jpOpEjoqbUC7KEU3ptR2j1vAMCBibBq0IsnHVUH3DQ80leEpf
gcf5vbY72PCTg5KGYZZ35XvrqzEP/z25qOnUZ+4Y7JljoXyNBb6eW1I3UstdPR1C
E9hFVjMVFD7YePCGK/Ytwp/1dFLgLsADjk6Zc4gfHlPV/Op8NaxIIcM0FjFvu+X1
znf3lRkaxedhdM0TsL6efOoNXJNHGZNXI+dUzgbEr+fyYcjHJFjh8HejJvcZDyvc
581k6EVE0aGBz857OZz+ojADhtnE2+GYCB2kkdT5iHFeHtHGbRrwIc6Fh3gInMBI
6yj86AaZEFJwLec/ckMn+kWdKwF17Q2qUOryr7UHlU8YP5DBAjSAZaocFynNto+I
ikQPde2s04tRpveMCJSYnvy2eQpJ2DEpWtkSAGMzg0Ly71zfSH1TMrhjR9AxDP0F
nrIBB7hEzTosxvrFTXHcCh8LxSDlohUL/UveA2Tiz/m1gvR51OnIx61EzqizHF5x
WkuLxgLlC4P1ZqFyV1guwcOqUD4rpwpqTyIgAIoVIQfnvZR5jgFXHBKDJPXyjJTD
oDEX8fVWX0xzwAoqBXqVs/TJcD9q8qKuuPaK8266XP5D/zM/PP1jRKQnC8IFPSq2
Ory4TDLCrSmVw+c8q+jZHgKiEXuwGzPJ+ImypTMV+uZZzCdR4YE=
=vonG
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"No pin control core changes this time.
New drivers:
- Realtek RTD family pin control driver and RTD1619B, RTD1319D and
RTD1315E subdrivers
- Nuvoton NPCM8xx combined pin control and GPIO driver
- Amlogic T7 pin control driver
- Renesas RZ/G3S pin control driver
Improvements:
- A number of additional UART groups added to the Mediatek MT7981
driver
- MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125 and SDM660
- Extra GPIO banks for the Sunxi H616
- MLSP I2C6 function support in Qualcomm MSM8226
- Some __counted_by() annotations for dynamic arrays
- Ongoing work to make remove() return void
- LSBC groups and functions in the Renesas R8A7778"
* tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
pinctrl: Use device_get_match_data()
dt-bindings: pinctrl: qcom,sa8775p-tlmm: add missing wakeup-parent
dt-bindings: pinctrl: nuvoton,npcm845: Add missing additionalProperties on gpio child nodes
dt-bindings: pinctrl: brcm: Ensure all child node properties are documented
pinctrl: renesas: rzn1: Convert to platform remove callback returning void
pinctrl: renesas: rzg2l: Add RZ/G3S support
dt-bindings: pinctrl: renesas: Document RZ/G3S SoC
pinctrl: renesas: rzg2l: Add support for different DS values on different groups
pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration
pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S
pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets
pinctrl: renesas: rzg2l: Index all registers based on port offset
pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request()
pinctrl: renesas: r8a7778: Add LBSC pins, groups, and functions
pinctrl: intel: fetch community only when we need it
pinctrl: cherryview: reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case
pinctrl: cherryview: Convert to platform remove callback returning void
pinctrl: sprd-sc9860: Convert to platform remove callback returning void
pinctrl: qcom/msm: Convert to platform remove callback returning void
pinctrl: qcom/lpi: Convert to platform remove callback returning void
...
Write into 'pctrl->gpio_bank' happens before the check for GPIO index
validity, so out of bounds write may happen.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: a1d1e0e3d8 ("pinctrl: nuvoton: Add driver for WPCM450")
Signed-off-by: Mikhail Kobuk <m.kobuk@ispras.ru>
Reviewed-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20230825101532.6624-1-m.kobuk@ispras.ru
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the pinconf_generic_dt_node_to_map_all() helper instead of
open-coding the same operation, to avoid having to provide custom
pinctrl_ops.dt_node_to_map() callbacks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/81e9ab48f78d63153b23a163b3349b3059d2b7fc.1692871558.git.geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0
selects the GPIO function and 1 selects the special function, in these
two fields, 0 selects the special function and 1 selects the GPIO
function.
Adjust the code to handle this quirk.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20221105185911.1547847-3-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In preparation for the next patch, which makes the logic around
setting/resetting bits in MFSEL a little more complicated, move that
code to a new function
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20221105185911.1547847-2-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning for irqchips that are not marked with
IRQCHIP_IMMUTABLE.
Convert the pinctrl-wpcm450 driver to an immutable irqchip.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20221031222833.201322-1-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
fwnode_irq_get() can return zero to indicate IRQ mapping errors.
Handle this case by skipping the interrupt resource.
Fixes: a1d1e0e3d8 ("pinctrl: nuvoton: Add driver for WPCM450")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220927175509.15695-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In case of error, the function devm_platform_ioremap_resource()
returns ERR_PTR() and never returns NULL. The NULL test in the
return value check should be replaced with IS_ERR().
Fixes: a1d1e0e3d8 ("pinctrl: nuvoton: Add driver for WPCM450")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220317065851.495394-1-zhangjialin11@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The > WPCM450_NUM_BANKS should be >= or it leads to an out of bounds
access on the next line.
Fixes: a1d1e0e3d8 ("pinctrl: nuvoton: Add driver for WPCM450")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220318071131.GA29472@kili
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sparse complains:
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c:626:9:
sparse: sparse: obsolete array initializer, use C99 syntax
This is because no equal sign is between the array index
and the assignments, in the macro.
Fix it up.
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver is based on the one for NPCM7xx, because the WPCM450 is a
predecessor of those SoCs. Notable differences:
- On WPCM450, the GPIO registers are not organized in multiple banks,
but rather placed continually into the same register block. This
affects how register offsets are computed.
- Pinmux nodes can explicitly select GPIO mode, whereas in the npcm7xx
driver, this happens automatically when a GPIO is requested.
Some functionality implemented in the hardware was (for now) left unused
in the driver, specifically blinking and pull-up/down.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220129115228.2257310-6-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
