Commit Graph

8 Commits

Author SHA1 Message Date
Kuan-Ying Lee
7d8742bf85 scripts/gdb: change VA_BITS_MIN when we use 16K page
Change VA_BITS_MIN when we use 16K page.

Link: https://lkml.kernel.org/r/20240619074911.100434-6-kuan-ying.lee@canonical.com
Fixes: 9684ec186f ("arm64: Enable LPA2 at boot if supported by the system")
Signed-off-by: Kuan-Ying Lee <kuan-ying.lee@canonical.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Kieran Bingham <kbingham@kernel.org>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-06-28 19:36:29 -07:00
Kuan-Ying Lee
04a40baec0 scripts/gdb: set vabits_actual based on TCR_EL1
We encounter the following issue after commit 9cce9c6c2c ("arm64: mm: Handle
LVA support as a CPU feature").

(gdb) lx-slabinfo
Python Exception <class 'gdb.error'>: No symbol "vabits_actual" in current context.
Error occurred in Python: No symbol "vabits_actual" in current context.

We set vabits_actual based on TCR_EL1 value when
VA_BITS is bigger than 48.

Link: https://lkml.kernel.org/r/20240619074911.100434-5-kuan-ying.lee@canonical.com
Fixes: 9cce9c6c2c ("arm64: mm: Handle LVA support as a CPU feature")
Signed-off-by: Kuan-Ying Lee <kuan-ying.lee@canonical.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Kieran Bingham <kbingham@kernel.org>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-06-28 19:36:29 -07:00
Kuan-Ying Lee
3c0e9a2004 scripts/gdb: change the layout of vmemmap
We need to change the layout of vmemmap in gdb scripts after
commit 32697ff382 ("arm64: vmemmap: Avoid base2 order of
struct page size to dimension region") changed it.

Link: https://lkml.kernel.org/r/20240619074911.100434-4-kuan-ying.lee@canonical.com
Fixes: 32697ff382 ("arm64: vmemmap: Avoid base2 order of struct page size to dimension region")
Signed-off-by: Kuan-Ying Lee <kuan-ying.lee@canonical.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Kieran Bingham <kbingham@kernel.org>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-06-28 19:36:28 -07:00
Kuan-Ying Lee
f2eaed1565 scripts/gdb: rework module VA range
After we enlarge the module VA range, we also change the module VA
range in gdb scripts.

Link: https://lkml.kernel.org/r/20240619074911.100434-3-kuan-ying.lee@canonical.com
Fixes: 3e35d303ab ("arm64: module: rework module VA range selection")
Signed-off-by: Kuan-Ying Lee <kuan-ying.lee@canonical.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Kieran Bingham <kbingham@kernel.org>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-06-28 19:36:28 -07:00
Kuan-Ying Lee
63ce5947ef scripts/gdb: redefine MAX_ORDER sanely
Patch series "Fix GDB command error".

This patchset fixes some GDB command errors.

1. Since memory layout of AARCH64 has been changed, we need to modify
   the layout in GDB scripts as well.

2. Fix pool_index naming of stackdepot.


This patch (of 6):

Change the definition of MAX_ORDER to be inclusive.

Link: https://lkml.kernel.org/r/20240619074911.100434-1-kuan-ying.lee@canonical.com
Link: https://lkml.kernel.org/r/20240619074911.100434-2-kuan-ying.lee@canonical.com
Fixes: 23baf831a3 ("mm, treewide: redefine MAX_ORDER sanely")
Signed-off-by: Kuan-Ying Lee <kuan-ying.lee@canonical.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Kieran Bingham <kbingham@kernel.org>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-06-28 19:36:28 -07:00
Arnd Bergmann
d3e5bab923 arch: simplify architecture specific page size configuration
arc, arm64, parisc and powerpc all have their own Kconfig symbols
in place of the common CONFIG_PAGE_SIZE_4KB symbols. Change these
so the common symbols are the ones that are actually used, while
leaving the arhcitecture specific ones as the user visible
place for configuring it, to avoid breaking user configs.

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> (powerpc32)
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Helge Deller <deller@gmx.de> # parisc
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-03-06 19:29:03 +01:00
Kuan-Ying Lee
eb985b5dbf scripts/gdb/aarch64: add aarch64 page operation helper commands and configs
1. Move page table debugging from mm.py to pgtable.py.

2. Add aarch64 kernel config and memory constants value.

3. Add below aarch64 page operation helper commands.
   page_to_pfn, page_to_phys, pfn_to_page, page_address,
   virt_to_phys, sym_to_pfn, pfn_to_kaddr, virt_to_page.

4. Only support CONFIG_SPARSEMEM_VMEMMAP=y now.

Link: https://lkml.kernel.org/r/20230808083020.22254-5-Kuan-Ying.Lee@mediatek.com
Signed-off-by: Kuan-Ying Lee <Kuan-Ying.Lee@mediatek.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: Chinwen Chang <chinwen.chang@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Qun-Wei Lin <qun-wei.lin@mediatek.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-08-21 13:46:22 -07:00
Dmitrii Bundin
e36903b0c1 scripts/gdb: add mm introspection utils
This command provides a way to traverse the entire page hierarchy by a
given virtual address on x86.  In addition to qemu's commands info
tlb/info mem it provides the complete information about the paging
structure for an arbitrary virtual address.  It supports 4KB/2MB/1GB and 5
level paging.

Here is an example output for 2MB success translation:

(gdb) translate-vm address
cr3:
    cr3 binary data                0x1085be003
    next entry physical address   0x1085be000
    ---
    bit  3          page level write through       False
    bit  4          page level cache disabled      False
level 4:
    entry address                  0xffff8881085be7f8
    page entry binary data         0x800000010ac83067
    next entry physical address   0x10ac83000
    ---
    bit  0          entry present                  True
    bit  1          read/write access allowed      True
    bit  2          user access allowed            True
    bit  3          page level write through       False
    bit  4          page level cache disabled      False
    bit  5          entry has been accessed        True
    bit  7          page size                      False
    bit  11         restart to ordinary            False
    bit  63         execute disable                True
level 3:
    entry address                  0xffff88810ac83a48
    page entry binary data         0x101af7067
    next entry physical address   0x101af7000
    ---
    bit  0          entry present                  True
    bit  1          read/write access allowed      True
    bit  2          user access allowed            True
    bit  3          page level write through       False
    bit  4          page level cache disabled      False
    bit  5          entry has been accessed        True
    bit  7          page size                      False
    bit  11         restart to ordinary            False
    bit  63         execute disable                False
level 2:
    entry address                  0xffff888101af7368
    page entry binary data         0x80000001634008e7
    page size                      2MB
    page physical address         0x163400000
    ---
    bit  0          entry present                  True
    bit  1          read/write access allowed      True
    bit  2          user access allowed            True
    bit  3          page level write through       False
    bit  4          page level cache disabled      False
    bit  5          entry has been accessed        True
    bit  7          page size                      True
    bit  6          page dirty                     True
    bit  8          global translation             False
    bit  11         restart to ordinary            True
    bit  12         pat                            False
    bits (59, 62)   protection key                 0
    bit  63         execute disable                True

[dmitrii.bundin.a@gmail.com: add SPDX line, other tweaks]
  Link: https://lkml.kernel.org/r/20230113175151.22278-1-dmitrii.bundin.a@gmail.com
[akpm@linux-foundation.org: s/physicall/physical/]
Link: https://lkml.kernel.org/r/20230102171014.31408-1-dmitrii.bundin.a@gmail.com
Signed-off-by: Dmitrii Bundin <dmitrii.bundin.a@gmail.com>
Acked by: Mike Rapoport (IBM) <rppt@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Kieran Bingham <kbingham@kernel.org>
Cc: Vlastimil Babka <vbabka@suse.cz>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-02-02 22:50:03 -08:00