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45fe957ae7
Currently, we may bump into pll mismatch errors during the
state verification stage. This happens when we try to use
fastset instead of full modeset. Hence, we would need to add
a check for pipe configuration to ensure that the sw and the
hw configuration will match. In case of hw and sw mismatch,
we would need to disable fastset and use full modeset instead.
v2: Fix C10 error on PLL comparison (BAT)
Use memcmp instead of fixed loops for pll config
comparison (Jani)
Clean up and use intel_cx0pll_dump_hw_state() to dump
pll information (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-3-mika.kahola@intel.com
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_CX0_PHY_H__
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#define __INTEL_CX0_PHY_H__
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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enum icl_port_dpll_id;
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_c10pll_state;
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struct intel_c20pll_state;
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struct intel_cx0pll_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_encoder;
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struct intel_hdmi;
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bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
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void intel_mtl_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mtl_pll_disable(struct intel_encoder *encoder);
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enum icl_port_dpll_id
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intel_mtl_port_pll_type(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
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void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
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struct intel_cx0pll_state *pll_state);
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int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
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const struct intel_cx0pll_state *pll_state);
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void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
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const struct intel_cx0pll_state *hw_state);
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void intel_cx0pll_state_verify(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
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const struct intel_cx0pll_state *b);
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void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
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int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
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#endif /* __INTEL_CX0_PHY_H__ */
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