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38e8c4184e
Enable power gating for all units and sub-pipes that
are disabled by default.
v2: change the init function name
use symmetric calls for enable/disable pg
re-pharase commit message (Rodrigo)
modify the sub-pipe power gating condition
v3: set hysteresis value for render and media
when GuC PC is disabled
skip CPG for PVC (Vinay)
v4: rebase
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v2
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-3-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
20 lines
434 B
C
20 lines
434 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GT_IDLE_H_
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#define _XE_GT_IDLE_H_
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#include "xe_gt_idle_types.h"
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struct xe_gt;
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int xe_gt_idle_init(struct xe_gt_idle *gtidle);
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void xe_gt_idle_enable_c6(struct xe_gt *gt);
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void xe_gt_idle_disable_c6(struct xe_gt *gt);
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void xe_gt_idle_enable_pg(struct xe_gt *gt);
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void xe_gt_idle_disable_pg(struct xe_gt *gt);
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#endif /* _XE_GT_IDLE_H_ */
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