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e02cea83d3
Add heci_cscfi support bit for new CSC engine type. It has same mmio offsets as DG2 GSC but separate interrupt flow. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240708084906.2827024-1-alexander.usyskin@intel.com
42 lines
997 B
C
42 lines
997 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2023, Intel Corporation. All rights reserved.
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*/
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#ifndef __XE_HECI_GSC_DEV_H__
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#define __XE_HECI_GSC_DEV_H__
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#include <linux/types.h>
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struct xe_device;
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struct mei_aux_device;
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/*
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* GSC HECI1 bit corresponds to bit15 and HECI2 to bit14.
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* The reason for this is to allow growth for more interfaces in the future.
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*/
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#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
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/*
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* CSC HECI1 bit corresponds to bit9 and HECI2 to bit10.
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*/
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#define CSC_IRQ_INTF(_x) BIT(9 + (_x))
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/**
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* struct xe_heci_gsc - graphics security controller for xe, HECI interface
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*
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* @adev : pointer to mei auxiliary device structure
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* @irq : irq number
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*
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*/
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struct xe_heci_gsc {
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struct mei_aux_device *adev;
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int irq;
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};
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void xe_heci_gsc_init(struct xe_device *xe);
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void xe_heci_gsc_fini(struct xe_device *xe);
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void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir);
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void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir);
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#endif /* __XE_HECI_GSC_DEV_H__ */
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