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dae5d79a3b
Export hw engine's mmio accessors. This is in preparation to use these from eudebug code. v2: s/hw_engine_mmio/xe_hw_engine_mmio (Matthew) v3: kernel doc (Matthew) Cc: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240806153009.1081382-1-mika.kuoppala@linux.intel.com
85 lines
2.7 KiB
C
85 lines
2.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef _XE_HW_ENGINE_H_
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#define _XE_HW_ENGINE_H_
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#include "xe_hw_engine_types.h"
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struct drm_printer;
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struct drm_xe_engine_class_instance;
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struct xe_device;
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#ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MIN
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#define XE_HW_ENGINE_JOB_TIMEOUT_MIN CONFIG_DRM_XE_JOB_TIMEOUT_MIN
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#else
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#define XE_HW_ENGINE_JOB_TIMEOUT_MIN 1
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#endif
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#ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MAX
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#define XE_HW_ENGINE_JOB_TIMEOUT_MAX CONFIG_DRM_XE_JOB_TIMEOUT_MAX
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#else
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#define XE_HW_ENGINE_JOB_TIMEOUT_MAX (10 * 1000)
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#endif
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#ifdef CONFIG_DRM_XE_TIMESLICE_MIN
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#define XE_HW_ENGINE_TIMESLICE_MIN CONFIG_DRM_XE_TIMESLICE_MIN
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#else
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#define XE_HW_ENGINE_TIMESLICE_MIN 1
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#endif
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#ifdef CONFIG_DRM_XE_TIMESLICE_MAX
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#define XE_HW_ENGINE_TIMESLICE_MAX CONFIG_DRM_XE_TIMESLICE_MAX
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#else
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#define XE_HW_ENGINE_TIMESLICE_MAX (10 * 1000 * 1000)
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#endif
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#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT
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#define XE_HW_ENGINE_PREEMPT_TIMEOUT CONFIG_DRM_XE_PREEMPT_TIMEOUT
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#else
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#define XE_HW_ENGINE_PREEMPT_TIMEOUT (640 * 1000)
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#endif
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#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN
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#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN
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#else
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#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN 1
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#endif
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#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX
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#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX
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#else
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#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX (10 * 1000 * 1000)
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#endif
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int xe_hw_engines_init_early(struct xe_gt *gt);
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int xe_hw_engines_init(struct xe_gt *gt);
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void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec);
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void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
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u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
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enum xe_engine_class engine_class);
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struct xe_hw_engine_snapshot *
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xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe);
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void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot);
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void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
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struct drm_printer *p);
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void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p);
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void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe);
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bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe);
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struct xe_hw_engine *
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xe_hw_engine_lookup(struct xe_device *xe,
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struct drm_xe_engine_class_instance eci);
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static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe)
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{
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return hwe->name;
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}
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const char *xe_hw_engine_class_to_str(enum xe_engine_class class);
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u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe);
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enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe);
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void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);
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u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);
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#endif
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