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f0295913c4
Add two new kernel command line parameters to limit the page-sizes used for v1 page-tables: nohugepages - Limits page-sizes to 4KiB v2_pgsizes_only - Limits page-sizes to 4Kib/2Mib/1GiB; The same as the sizes used with v2 page-tables This is needed for multiple scenarios. When assigning devices to SEV-SNP guests the IOMMU page-sizes need to match the sizes in the RMP table, otherwise the device will not be able to access all shared memory. Also, some ATS devices do not work properly with arbitrary IO page-sizes as supported by AMD-Vi, so limiting the sizes used by the driver is a suitable workaround. All-in-all, these parameters are only workarounds until the IOMMU core and related APIs gather the ability to negotiate the page-sizes in a better way. Signed-off-by: Joerg Roedel <jroedel@suse.de> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Link: https://lore.kernel.org/r/20240905072240.253313-1-joro@8bytes.org
180 lines
5.7 KiB
C
180 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef AMD_IOMMU_H
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#define AMD_IOMMU_H
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#include <linux/iommu.h>
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#include "amd_iommu_types.h"
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irqreturn_t amd_iommu_int_thread(int irq, void *data);
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irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data);
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irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data);
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irqreturn_t amd_iommu_int_thread_galog(int irq, void *data);
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irqreturn_t amd_iommu_int_handler(int irq, void *data);
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void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
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void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type,
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u8 cntrl_intr, u8 cntrl_log,
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u32 status_run_mask, u32 status_overflow_mask);
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void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
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void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
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void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
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void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
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void iommu_feature_enable(struct amd_iommu *iommu, u8 bit);
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void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
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gfp_t gfp, size_t size);
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#ifdef CONFIG_AMD_IOMMU_DEBUGFS
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void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
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#else
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static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
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#endif
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/* Needed for interrupt remapping */
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int amd_iommu_prepare(void);
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int amd_iommu_enable(void);
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void amd_iommu_disable(void);
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int amd_iommu_reenable(int mode);
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int amd_iommu_enable_faulting(unsigned int cpu);
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extern int amd_iommu_guest_ir;
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extern enum io_pgtable_fmt amd_iommu_pgtable;
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extern int amd_iommu_gpt_level;
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extern unsigned long amd_iommu_pgsize_bitmap;
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/* Protection domain ops */
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struct protection_domain *protection_domain_alloc(unsigned int type, int nid);
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void protection_domain_free(struct protection_domain *domain);
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struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev,
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struct mm_struct *mm);
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void amd_iommu_domain_free(struct iommu_domain *dom);
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int iommu_sva_set_dev_pasid(struct iommu_domain *domain,
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struct device *dev, ioasid_t pasid);
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void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid,
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struct iommu_domain *domain);
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/* SVA/PASID */
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bool amd_iommu_pasid_supported(void);
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/* IOPF */
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int amd_iommu_iopf_init(struct amd_iommu *iommu);
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void amd_iommu_iopf_uninit(struct amd_iommu *iommu);
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void amd_iommu_page_response(struct device *dev, struct iopf_fault *evt,
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struct iommu_page_response *resp);
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int amd_iommu_iopf_add_device(struct amd_iommu *iommu,
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struct iommu_dev_data *dev_data);
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void amd_iommu_iopf_remove_device(struct amd_iommu *iommu,
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struct iommu_dev_data *dev_data);
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/* GCR3 setup */
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int amd_iommu_set_gcr3(struct iommu_dev_data *dev_data,
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ioasid_t pasid, unsigned long gcr3);
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int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid);
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/* PPR */
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int __init amd_iommu_alloc_ppr_log(struct amd_iommu *iommu);
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void __init amd_iommu_free_ppr_log(struct amd_iommu *iommu);
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void amd_iommu_enable_ppr_log(struct amd_iommu *iommu);
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void amd_iommu_poll_ppr_log(struct amd_iommu *iommu);
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int amd_iommu_complete_ppr(struct device *dev, u32 pasid, int status, int tag);
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/*
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* This function flushes all internal caches of
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* the IOMMU used by this driver.
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*/
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void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
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void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
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void amd_iommu_domain_update(struct protection_domain *domain);
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void amd_iommu_domain_flush_pages(struct protection_domain *domain,
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u64 address, size_t size);
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void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data,
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ioasid_t pasid, u64 address, size_t size);
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#ifdef CONFIG_IRQ_REMAP
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int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
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#else
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static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
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{
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return 0;
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}
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#endif
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static inline bool is_rd890_iommu(struct pci_dev *pdev)
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{
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return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
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(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
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}
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static inline bool check_feature(u64 mask)
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{
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return (amd_iommu_efr & mask);
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}
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static inline bool check_feature2(u64 mask)
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{
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return (amd_iommu_efr2 & mask);
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}
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static inline bool amd_iommu_gt_ppr_supported(void)
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{
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return (check_feature(FEATURE_GT) &&
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check_feature(FEATURE_PPR) &&
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check_feature(FEATURE_EPHSUP));
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}
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static inline u64 iommu_virt_to_phys(void *vaddr)
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{
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return (u64)__sme_set(virt_to_phys(vaddr));
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}
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static inline void *iommu_phys_to_virt(unsigned long paddr)
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{
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return phys_to_virt(__sme_clr(paddr));
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}
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static inline int get_pci_sbdf_id(struct pci_dev *pdev)
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{
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int seg = pci_domain_nr(pdev->bus);
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u16 devid = pci_dev_id(pdev);
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return PCI_SEG_DEVID_TO_SBDF(seg, devid);
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}
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/*
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* This must be called after device probe completes. During probe
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* use rlookup_amd_iommu() get the iommu.
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*/
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static inline struct amd_iommu *get_amd_iommu_from_dev(struct device *dev)
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{
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return iommu_get_iommu_dev(dev, struct amd_iommu, iommu);
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}
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/* This must be called after device probe completes. */
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static inline struct amd_iommu *get_amd_iommu_from_dev_data(struct iommu_dev_data *dev_data)
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{
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return iommu_get_iommu_dev(dev_data->dev, struct amd_iommu, iommu);
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}
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static inline struct protection_domain *to_pdomain(struct iommu_domain *dom)
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{
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return container_of(dom, struct protection_domain, domain);
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}
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bool translation_pre_enabled(struct amd_iommu *iommu);
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int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
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#ifdef CONFIG_DMI
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void amd_iommu_apply_ivrs_quirks(void);
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#else
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static inline void amd_iommu_apply_ivrs_quirks(void) { }
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#endif
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void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
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u64 *root, int mode);
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struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
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#endif
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