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fd94213e14
The deferred_reset logic was added to vfio migration drivers to prevent a circular locking dependency with respect to mm_lock and state mutex. This is mainly because of the copy_to/from_user() functions(which takes mm_lock) invoked under state mutex. But for HiSilicon driver, the only place where we now hold the state mutex for copy_to_user is during the PRE_COPY IOCTL. So for pre_copy, release the lock as soon as we have updated the data and perform copy_to_user without state mutex. By this, we can get rid of the deferred_reset logic. Link: https://lore.kernel.org/kvm/20240220132459.GM13330@nvidia.com/ Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Brett Creeley <brett.creeley@amd.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20240229091152.56664-1-shameerali.kolothum.thodi@huawei.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
116 lines
2.7 KiB
C
116 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2021 HiSilicon Ltd. */
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#ifndef HISI_ACC_VFIO_PCI_H
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#define HISI_ACC_VFIO_PCI_H
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#include <linux/hisi_acc_qm.h>
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#define MB_POLL_PERIOD_US 10
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#define MB_POLL_TIMEOUT_US 1000
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#define QM_CACHE_WB_START 0x204
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#define QM_CACHE_WB_DONE 0x208
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#define QM_MB_CMD_PAUSE_QM 0xe
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#define QM_ABNORMAL_INT_STATUS 0x100008
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#define QM_IFC_INT_STATUS 0x0028
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#define SEC_CORE_INT_STATUS 0x301008
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#define HPRE_HAC_INT_STATUS 0x301800
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#define HZIP_CORE_INT_STATUS 0x3010AC
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#define QM_VFT_CFG_RDY 0x10006c
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#define QM_VFT_CFG_OP_WR 0x100058
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#define QM_VFT_CFG_TYPE 0x10005c
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#define QM_VFT_CFG 0x100060
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#define QM_VFT_CFG_OP_ENABLE 0x100054
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#define QM_VFT_CFG_DATA_L 0x100064
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#define QM_VFT_CFG_DATA_H 0x100068
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#define ERROR_CHECK_TIMEOUT 100
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#define CHECK_DELAY_TIME 100
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#define QM_SQC_VFT_BASE_SHIFT_V2 28
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#define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
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#define QM_SQC_VFT_NUM_SHIFT_V2 45
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#define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)
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/* RW regs */
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#define QM_REGS_MAX_LEN 7
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#define QM_REG_ADDR_OFFSET 0x0004
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#define QM_XQC_ADDR_OFFSET 32U
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#define QM_VF_AEQ_INT_MASK 0x0004
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#define QM_VF_EQ_INT_MASK 0x000c
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#define QM_IFC_INT_SOURCE_V 0x0020
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#define QM_IFC_INT_MASK 0x0024
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#define QM_IFC_INT_SET_V 0x002c
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#define QM_QUE_ISO_CFG_V 0x0030
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#define QM_PAGE_SIZE 0x0034
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#define QM_EQC_DW0 0X8000
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#define QM_AEQC_DW0 0X8020
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struct acc_vf_data {
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#define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
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/* QM match information */
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#define ACC_DEV_MAGIC 0XCDCDCDCDFEEDAACC
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u64 acc_magic;
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u32 qp_num;
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u32 dev_id;
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u32 que_iso_cfg;
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u32 qp_base;
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u32 vf_qm_state;
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/* QM reserved match information */
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u32 qm_rsv_state[3];
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/* QM RW regs */
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u32 aeq_int_mask;
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u32 eq_int_mask;
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u32 ifc_int_source;
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u32 ifc_int_mask;
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u32 ifc_int_set;
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u32 page_size;
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/* QM_EQC_DW has 7 regs */
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u32 qm_eqc_dw[7];
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/* QM_AEQC_DW has 7 regs */
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u32 qm_aeqc_dw[7];
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/* QM reserved 5 regs */
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u32 qm_rsv_regs[5];
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u32 padding;
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/* QM memory init information */
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u64 eqe_dma;
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u64 aeqe_dma;
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u64 sqc_dma;
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u64 cqc_dma;
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};
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struct hisi_acc_vf_migration_file {
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struct file *filp;
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struct mutex lock;
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bool disabled;
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struct hisi_acc_vf_core_device *hisi_acc_vdev;
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struct acc_vf_data vf_data;
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size_t total_length;
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};
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struct hisi_acc_vf_core_device {
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struct vfio_pci_core_device core_device;
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u8 match_done;
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/* For migration state */
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struct mutex state_mutex;
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enum vfio_device_mig_state mig_state;
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struct pci_dev *pf_dev;
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struct pci_dev *vf_dev;
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struct hisi_qm *pf_qm;
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struct hisi_qm vf_qm;
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u32 vf_qm_state;
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int vf_id;
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struct hisi_acc_vf_migration_file *resuming_migf;
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struct hisi_acc_vf_migration_file *saving_migf;
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};
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#endif /* HISI_ACC_VFIO_PCI_H */
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