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63ba5b0fb4
Currently, the RISC-V firmware JSON file has duplicate event name
"FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1],
the event name should be "FW_SFENCE_VMA_ASID_SENT".
Before this patch:
$ perf list
firmware:
fw_access_load
[Load access trap event. Unit: cpu]
fw_access_store
[Store access trap event. Unit: cpu]
....
fw_set_timer
[Set timer event. Unit: cpu]
fw_sfence_vma_asid_received
[Received SFENCE.VMA with ASID request from other HART event. Unit: cpu]
fw_sfence_vma_received
[Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu]
After this patch:
$ perf list
firmware:
fw_access_load
[Load access trap event. Unit: cpu]
fw_access_store
[Store access trap event. Unit: cpu]
.....
fw_set_timer
[Set timer event. Unit: cpu]
fw_sfence_vma_asid_received
[Received SFENCE.VMA with ASID request from other HART event. Unit: cpu]
fw_sfence_vma_asid_sent
[Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu]
fw_sfence_vma_received
[Received SFENCE.VMA request from other HART event. Unit: cpu]
Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1]
Fixes: 8f0dcb4e73 ("perf arch events: riscv sbi firmware std event files")
Fixes: c4f769d409 ("perf vendor events riscv: add Sifive U74 JSON file")
Fixes: acbf6de674 ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file")
Fixes: 7340c6df49 ("perf vendor events riscv: add T-HEAD C9xx JSON file")
Fixes: f5102e31c2 ("riscv: andes: Support specifying symbolic firmware and hardware raw event")
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240719115018.27356-1-eric.lin@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
69 lines
1.1 KiB
JSON
69 lines
1.1 KiB
JSON
[
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{
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"ArchStdEvent": "FW_MISALIGNED_LOAD"
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},
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{
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"ArchStdEvent": "FW_MISALIGNED_STORE"
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},
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{
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"ArchStdEvent": "FW_ACCESS_LOAD"
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},
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{
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"ArchStdEvent": "FW_ACCESS_STORE"
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},
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{
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"ArchStdEvent": "FW_ILLEGAL_INSN"
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},
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{
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"ArchStdEvent": "FW_SET_TIMER"
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},
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{
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"ArchStdEvent": "FW_IPI_SENT"
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},
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{
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"ArchStdEvent": "FW_IPI_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_SENT"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_SENT"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
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}
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]
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