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Add metrics for tlb and cache statistics: - finite_cpi: Cycles per Instructions from Finite cache/memory - est_cpi: Estimated Instruction Complexity CPI infinite Level 1 - scpl1m: Estimated Sourcing Cycles per Level 1 Miss - tlb_percent: Estimated TLB CPU percentage of Total CPU - tlb_miss: Estimated Cycles per TLB Miss For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K ... dd output removed Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K': 667,726 DTLB2_MISSES # 440.96 tlb_miss 198 ITLB2_WRITES 795,170,260 L1C_TLB2_MISSES 9,478 ITLB2_MISSES 820 DTLB2_WRITES 1,197,126,869 L1D_PENALTY_CYCLES 2,457,447 L1I_PENALTY_CYCLES 1.249342187 seconds time elapsed 0.001030000 seconds user 1.248105000 seconds sys # Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Ian Rogers <irogers@google.com> Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
78 lines
4.0 KiB
JSON
78 lines
4.0 KiB
JSON
[
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{
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"BriefDescription": "Transaction count",
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"MetricName": "transaction",
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"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
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},
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{
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"BriefDescription": "Cycles per Instruction",
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"MetricName": "cpi",
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"MetricExpr": "CPU_CYCLES / INSTRUCTIONS"
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},
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{
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"BriefDescription": "Problem State Instruction Ratio",
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"MetricName": "prbstate",
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"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100"
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},
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{
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"BriefDescription": "Level One Miss per 100 Instructions",
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"MetricName": "l1mp",
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"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 2 cache",
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"MetricName": "l2p",
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"MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
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"MetricName": "l3p",
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"MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
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"MetricName": "l4lp",
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"MetricExpr": "((L1D_ONNODE_L4_SOURCED_WRITES + L1D_ONNODE_L3_SOURCED_WRITES_IV + L1D_ONNODE_L3_SOURCED_WRITES + L1I_ONNODE_L4_SOURCED_WRITES + L1I_ONNODE_L3_SOURCED_WRITES_IV + L1I_ONNODE_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
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"MetricName": "l4rp",
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"MetricExpr": "((L1D_ONDRAWER_L4_SOURCED_WRITES + L1D_ONDRAWER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES + L1I_ONDRAWER_L4_SOURCED_WRITES + L1I_ONDRAWER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from memory",
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"MetricName": "memp",
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"MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Cycles per Instructions from Finite cache/memory",
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"MetricName": "finite_cpi",
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"MetricExpr": "L1C_TLB1_MISSES / INSTRUCTIONS"
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},
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{
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"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
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"MetricName": "est_cpi",
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"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)"
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},
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{
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"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
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"MetricName": "scpl1m",
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"MetricExpr": "L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
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},
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{
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"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
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"MetricName": "tlb_percent",
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"MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
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},
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{
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"BriefDescription": "Estimated Cycles per TLB Miss",
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"MetricName": "tlb_miss",
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"MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
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},
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{
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"BriefDescription": "Page Table Entry misses",
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"MetricName": "pte_miss",
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"MetricExpr": "(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100"
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}
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]
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