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On s390 z/VM virtual machines command 'perf list' also displays metrics:
# perf list | grep -A 20 'Metric Groups:'
Metric Groups:
No_group:
cpi
[Cycles per Instruction]
est_cpi
[Estimated Instruction Complexity CPI infinite Level 1]
finite_cpi
[Cycles per Instructions from Finite cache/memory]
l1mp
[Level One Miss per 100 Instructions]
l2p
[Percentage sourced from Level 2 cache]
l3p
[Percentage sourced from Level 3 on same chip cache]
l4lp
[Percentage sourced from Level 4 Local cache on same book]
l4rp
[Percentage sourced from Level 4 Remote cache on different book]
memp
[Percentage sourced from memory]
....
#
The command
# perf stat -M cpi -- true
event syntax error: '{CPU_CYCLES/metric-id=CPU_CYCLES/.....'
\___ Bad event or PMU
Unable to find PMU or event on a PMU of 'CPU_CYCLES'
event syntax error: '{CPU_CYCLES/metric-id=CPU_CYCLES/...'
\___ Cannot find PMU `CPU_CYCLES'.
Missing kernel support?
#
fails. 'perf stat' should not fail on metrics when the referenced CPU
Counter Measurement PMU is not available.
Output after:
# perf stat -M est_cpi -- sleep 1
Performance counter stats for 'sleep 1':
1,000,887,494 ns duration_time # 0.00 est_cpi
1.000887494 seconds time elapsed
0.000143000 seconds user
0.000662000 seconds sys
#
Fixes: 7f76b31130
("perf list: Add IBM z16 event description for s390")
Suggested-by: Ian Rogers <irogers@google.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Sumanth Korikkar <sumanthk@linux.ibm.com>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Link: https://lore.kernel.org/r/20240404064806.1362876-2-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
73 lines
3.8 KiB
JSON
73 lines
3.8 KiB
JSON
[
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{
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"BriefDescription": "Transaction count",
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"MetricName": "transaction",
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"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0"
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},
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{
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"BriefDescription": "Cycles per Instruction",
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"MetricName": "cpi",
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"MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Problem State Instruction Ratio",
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"MetricName": "prbstate",
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"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Level One Miss per 100 Instructions",
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"MetricName": "l1mp",
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"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 2 cache",
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"MetricName": "l2p",
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"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
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"MetricName": "l3p",
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"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
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"MetricName": "l4lp",
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"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
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"MetricName": "l4rp",
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"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from memory",
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"MetricName": "memp",
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"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0"
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},
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{
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"BriefDescription": "Cycles per Instructions from Finite cache/memory",
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"MetricName": "finite_cpi",
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"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0"
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},
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{
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"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
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"MetricName": "est_cpi",
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"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
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"MetricName": "scpl1m",
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"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0"
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},
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{
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"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
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"MetricName": "tlb_percent",
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"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0"
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},
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{
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"BriefDescription": "Estimated Cycles per TLB Miss",
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"MetricName": "tlb_miss",
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"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0"
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}
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]
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