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11c2302c9e
Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in:475892a969and later patches. The TMA 4.8 information was updated in:59194d4d90Co-authored-by: Weilin Wang <weilin.wang@intel.com> Co-authored-by: Caleb Biggers <caleb.biggers@intel.com> Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240620181752.3945845-16-irogers@google.com
94 lines
3.7 KiB
JSON
94 lines
3.7 KiB
JSON
[
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{
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"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
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"Counter": "0,1,2,3",
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"EventCode": "0xC6",
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"EventName": "AVX_INSTS.ALL",
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"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
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"SampleAfterValue": "2000003",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Cycles with any input/output SSE or FP assist",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.ANY",
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"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x1e"
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to input values",
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"Counter": "0,1,2,3",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_INPUT",
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"PublicDescription": "Number of SIMD FP assists due to input values.",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to Output values",
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"Counter": "0,1,2,3",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_OUTPUT",
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"PublicDescription": "Number of SIMD FP assists due to output values.",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of X87 assists due to input value.",
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"Counter": "0,1,2,3",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_INPUT",
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"PublicDescription": "Number of X87 FP assists due to input values.",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of X87 assists due to output value.",
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"Counter": "0,1,2,3",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_OUTPUT",
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"PublicDescription": "Number of X87 FP assists due to output values.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
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"Counter": "0,1,2,3",
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"EventCode": "0x58",
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"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
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"PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
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"SampleAfterValue": "1000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
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"Counter": "0,1,2,3",
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"EventCode": "0x58",
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"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
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"PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
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"Counter": "0,1,2,3",
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"Errata": "HSD56, HSM57",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
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"Counter": "0,1,2,3",
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"Errata": "HSD56, HSM57",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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}
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]
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