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238a2117cc
Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in:475892a969and later patches. The TMA 4.8 information was updated in:59194d4d90Co-authored-by: Weilin Wang <weilin.wang@intel.com> Co-authored-by: Caleb Biggers <caleb.biggers@intel.com> Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240620181752.3945845-19-irogers@google.com
41 lines
1.5 KiB
JSON
41 lines
1.5 KiB
JSON
[
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{
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"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
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"Counter": "0,1,2,3",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING0",
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"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EdgeDetect": "1",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING0_TRANS",
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"PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
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"Counter": "0,1,2,3",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING123",
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"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
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"Counter": "0,1,2,3",
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"EventCode": "0x63",
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"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
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"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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