mirror of
git://git.yoctoproject.org/linux-yocto.git
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af557589c4
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
475892a969
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-25-irogers@google.com
110 lines
3.1 KiB
JSON
110 lines
3.1 KiB
JSON
[
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{
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"BriefDescription": "DTLB load misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "DTLB load miss caused by low part of address",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "DTLB second level hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
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"SampleAfterValue": "2000000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "DTLB load miss page walks complete",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "DTLB misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "DTLB first level misses but second level hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.STLB_HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "DTLB miss page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "ITLB flushes",
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"Counter": "0,1,2,3",
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"EventCode": "0xAE",
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"EventName": "ITLB_FLUSH",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB miss",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB miss page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC8",
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"EventName": "ITLB_MISS_RETIRED",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xCB",
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"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC",
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"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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}
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]
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