linux-yocto/tools/perf/pmu-events/arch/x86/sandybridge/other.json
Ian Rogers 01cb5e3d98 perf vendor events: Update sandybridge metrics add event counter information
Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
475892a969
and later patches.

The TMA 4.8 information was updated in:
59194d4d90

Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-28-irogers@google.com
2024-06-20 16:55:45 -07:00

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JSON

[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Valid instructions written to IQ per cycle.",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]