Jiawen Wu 4174c0c331 net: ngbe: specify IRQ vector when the number of VFs is 7 ... For NGBE devices, the queue number is limited to be 1 when SRIOV is enabled. In this case, IRQ vector[0] is used for MISC and vector[1] is used for queue, based on the previous patches. But for the hardware design, the IRQ vector[1] must be allocated for use by the VF[6] when the number of VFs is 7. So the IRQ vector[0] should be shared for PF MISC and QUEUE interrupts. +-----------+----------------------+ | Vector | Assigned To | +-----------+----------------------+ | Vector 0 | PF MISC and QUEUE | | Vector 1 | VF 6 | | Vector 2 | VF 5 | | Vector 3 | VF 4 | | Vector 4 | VF 3 | | Vector 5 | VF 2 | | Vector 6 | VF 1 | | Vector 7 | VF 0 | +-----------+----------------------+ Minimize code modifications, only adjust the IRQ vector number for this case. Fixes: 877253d2cb ("net: ngbe: add sriov function support") Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Larysa Zaremba <larysa.zaremba@intel.com> Link: https://patch.msgid.link/20250701063030.59340-4-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>		2025-07-03 11:51:40 +02:00
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libwx	net: ngbe: specify IRQ vector when the number of VFs is 7	2025-07-03 11:51:40 +02:00
ngbe	net: ngbe: specify IRQ vector when the number of VFs is 7	2025-07-03 11:51:40 +02:00
txgbe	net: wangxun: revert the adjustment of the IRQ vector sequence	2025-07-03 11:51:40 +02:00
Kconfig	net: txgbe: Update module description	2025-04-15 08:21:08 -07:00
Makefile	net: txgbe: Store PCI info	2022-10-28 11:25:53 +01:00