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a6156e7031
In subsequent patches the GICv3 driver will choose the regular interrupt priority at boot time. In preparation for using dynamic priorities, place the priorities in variables and update the code to pass these as parameters. Users of GICD_INT_DEF_PRI_X4 are modified to replicate the priority byte using REPEAT_BYTE_U32(). There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Alexandru Elisei <alexandru.elisei@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20240617111841.2529370-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
20 lines
480 B
C
20 lines
480 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* include/linux/irqchip/arm-gic-common.h
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*
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* Copyright (C) 2016 ARM Limited, All Rights Reserved.
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*/
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#ifndef __LINUX_IRQCHIP_ARM_GIC_COMMON_H
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#define __LINUX_IRQCHIP_ARM_GIC_COMMON_H
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#include <linux/irqchip/arm-vgic-info.h>
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#define GICD_INT_DEF_PRI 0xa0
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struct irq_domain;
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struct fwnode_handle;
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int gicv2m_init(struct fwnode_handle *parent_handle,
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struct irq_domain *parent);
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#endif /* __LINUX_IRQCHIP_ARM_GIC_COMMON_H */
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