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fbe826b1c1
RISC-V IMSIC interrupt controller provides IPI and MSI support. Currently, DT based drivers setup the IPI feature early during boot but defer setting up the MSI functionality. However, in ACPI systems, PCI subsystem is probed early and assume MSI controller is already setup. Hence, both IPI and MSI features need to be initialized early itself. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-16-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H
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#define __LINUX_IRQCHIP_RISCV_IMSIC_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/fwnode.h>
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#include <asm/csr.h>
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#define IMSIC_MMIO_PAGE_SHIFT 12
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#define IMSIC_MMIO_PAGE_SZ BIT(IMSIC_MMIO_PAGE_SHIFT)
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#define IMSIC_MMIO_PAGE_LE 0x00
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#define IMSIC_MMIO_PAGE_BE 0x04
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#define IMSIC_MIN_ID 63
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#define IMSIC_MAX_ID 2048
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#define IMSIC_EIDELIVERY 0x70
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#define IMSIC_EITHRESHOLD 0x72
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#define IMSIC_EIP0 0x80
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#define IMSIC_EIP63 0xbf
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#define IMSIC_EIPx_BITS 32
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#define IMSIC_EIE0 0xc0
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#define IMSIC_EIE63 0xff
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#define IMSIC_EIEx_BITS 32
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#define IMSIC_FIRST IMSIC_EIDELIVERY
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#define IMSIC_LAST IMSIC_EIE63
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#define IMSIC_MMIO_SETIPNUM_LE 0x00
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#define IMSIC_MMIO_SETIPNUM_BE 0x04
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struct imsic_local_config {
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phys_addr_t msi_pa;
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void __iomem *msi_va;
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};
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struct imsic_global_config {
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/*
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* MSI Target Address Scheme
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*
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* XLEN-1 12 0
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* | | |
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* -------------------------------------------------------------
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* |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
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* -------------------------------------------------------------
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*/
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/* Bits representing Guest index, HART index, and Group index */
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u32 guest_index_bits;
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u32 hart_index_bits;
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u32 group_index_bits;
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u32 group_index_shift;
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/* Global base address matching all target MSI addresses */
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phys_addr_t base_addr;
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/* Number of interrupt identities */
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u32 nr_ids;
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/* Number of guest interrupt identities */
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u32 nr_guest_ids;
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/* Per-CPU IMSIC addresses */
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struct imsic_local_config __percpu *local;
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};
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#ifdef CONFIG_RISCV_IMSIC
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const struct imsic_global_config *imsic_get_global_config(void);
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#else
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static inline const struct imsic_global_config *imsic_get_global_config(void)
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{
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return NULL;
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}
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#endif
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#ifdef CONFIG_ACPI
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int imsic_platform_acpi_probe(struct fwnode_handle *fwnode);
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struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev);
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#else
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static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) { return NULL; }
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#endif
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#endif
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