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2494fce26e
The ioread/iowrite functions on sh only do memory mapped I/O like the generic verion, and never map onto non-MMIO inb/outb variants, so they just add complexity. In particular, the use of asm-generic/iomap.h ties the declaration to the x86 implementation. Remove the custom versions and use the architecture-independent fallback code instead. Some of the calling conventions on sh are different here, so fix that by adding 'volatile' keywords where required by the generic implementation and change the cpg clock driver to no longer depend on the interesting choice of return types for ioread8/ioread16/ioread32. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
292 lines
8.4 KiB
C
292 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l,q}/write{b,w,l,q} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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*
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* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
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* and 'string' versions: ins{b,w,l}/outs{b,w,l}
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*
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* While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
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* automatically, there are also __raw versions, which do not.
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*/
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#include <linux/errno.h>
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#include <asm/cache.h>
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#include <asm/addrspace.h>
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#include <asm/machvec.h>
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#include <asm/page.h>
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#include <linux/pgtable.h>
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#define __IO_PREFIX generic
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#include <asm/io_generic.h>
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#include <asm-generic/pci_iomap.h>
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#include <mach/mangle-port.h>
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
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#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
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#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
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#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
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#define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; })
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#define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; })
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#define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
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#define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
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#define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c))
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
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#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
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#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
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#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
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#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
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#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
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#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
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#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
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#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
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#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
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#define readsb(p,d,l) __raw_readsb(p,d,l)
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#define readsw(p,d,l) __raw_readsw(p,d,l)
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#define readsl(p,d,l) __raw_readsl(p,d,l)
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#define writesb(p,d,l) __raw_writesb(p,d,l)
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#define writesw(p,d,l) __raw_writesw(p,d,l)
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#define writesl(p,d,l) __raw_writesl(p,d,l)
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#define __BUILD_UNCACHED_IO(bwlq, type) \
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static inline type read##bwlq##_uncached(unsigned long addr) \
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{ \
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type ret; \
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jump_to_uncached(); \
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ret = __raw_read##bwlq(addr); \
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back_to_cached(); \
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return ret; \
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} \
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\
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static inline void write##bwlq##_uncached(type v, unsigned long addr) \
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{ \
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jump_to_uncached(); \
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__raw_write##bwlq(v, addr); \
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back_to_cached(); \
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}
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__BUILD_UNCACHED_IO(b, u8)
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__BUILD_UNCACHED_IO(w, u16)
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__BUILD_UNCACHED_IO(l, u32)
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__BUILD_UNCACHED_IO(q, u64)
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#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
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\
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static inline void \
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pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
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unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void pfx##reads##bwlq(const volatile void __iomem *mem, \
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void *addr, unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __raw_read##bwlq(mem); \
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__addr++; \
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} \
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}
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__BUILD_MEMORY_STRING(__raw_, b, u8)
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__BUILD_MEMORY_STRING(__raw_, w, u16)
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void __raw_writesl(void volatile __iomem *addr, const void *data, int longlen);
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void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
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__BUILD_MEMORY_STRING(__raw_, q, u64)
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#define ioport_map ioport_map
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#define pci_iounmap pci_iounmap
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#ifdef CONFIG_HAS_IOPORT_MAP
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extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* On SuperH I/O ports are memory mapped, so we access them using normal
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* load/store instructions. sh_io_port_base is the virtual address to
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* which all ports are being mapped.
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*/
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extern unsigned long sh_io_port_base;
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static inline void __set_io_port_base(unsigned long pbase)
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{
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*(unsigned long *)&sh_io_port_base = pbase;
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barrier();
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}
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#ifdef CONFIG_GENERIC_IOMAP
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#define __ioport_map ioport_map
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#else
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extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
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#endif
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#ifdef CONF_SLOWDOWN_IO
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#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
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#else
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#define SLOW_DOWN_IO
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#endif
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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\
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__addr = (void __iomem *)sh_io_port_base + port; \
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*__addr = val; \
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slow; \
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} \
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\
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static inline type pfx##in##bwlq##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void __iomem *)sh_io_port_base + port; \
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__val = *__addr; \
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slow; \
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\
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return __val; \
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}
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#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
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#define BUILDIO_IOPORT(bwlq, type) \
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__BUILD_IOPORT_PFX(, bwlq, type)
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BUILDIO_IOPORT(b, u8)
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BUILDIO_IOPORT(w, u16)
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BUILDIO_IOPORT(l, u32)
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BUILDIO_IOPORT(q, u64)
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#define __BUILD_IOPORT_STRING(bwlq, type) \
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\
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static inline void outs##bwlq(unsigned long port, const void *addr, \
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unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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out##bwlq(*__addr, port); \
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__addr++; \
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} \
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} \
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\
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static inline void ins##bwlq(unsigned long port, void *addr, \
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unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = in##bwlq(port); \
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__addr++; \
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} \
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}
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__BUILD_IOPORT_STRING(b, u8)
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__BUILD_IOPORT_STRING(w, u16)
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__BUILD_IOPORT_STRING(l, u32)
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__BUILD_IOPORT_STRING(q, u64)
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#else /* !CONFIG_HAS_IOPORT_MAP */
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#include <asm/io_noioport.h>
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#endif
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#define inb(addr) inb(addr)
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#define inw(addr) inw(addr)
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#define inl(addr) inl(addr)
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#define outb(x, addr) outb((x), (addr))
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#define outw(x, addr) outw((x), (addr))
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#define outl(x, addr) outl((x), (addr))
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#define inb_p(addr) inb(addr)
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#define inw_p(addr) inw(addr)
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#define inl_p(addr) inl(addr)
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#define outb_p(x, addr) outb((x), (addr))
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#define outw_p(x, addr) outw((x), (addr))
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#define outl_p(x, addr) outl((x), (addr))
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#define insb insb
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#define insw insw
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#define insl insl
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#define outsb outsb
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#define outsw outsw
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#define outsl outsl
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#define IO_SPACE_LIMIT 0xffffffff
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/* We really want to try and get these to memcpy etc */
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#define memset_io memset_io
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#define memcpy_fromio memcpy_fromio
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#define memcpy_toio memcpy_toio
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void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
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void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
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void memset_io(volatile void __iomem *, int, unsigned long);
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/* Quad-word real-mode I/O, don't ask.. */
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unsigned long long peek_real_address_q(unsigned long long addr);
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unsigned long long poke_real_address_q(unsigned long long addr,
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unsigned long long val);
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#if !defined(CONFIG_MMU)
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#define virt_to_phys(address) ((unsigned long)(address))
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#define phys_to_virt(address) ((void *)(address))
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#else
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#define virt_to_phys(address) (__pa(address))
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#define phys_to_virt(address) (__va(address))
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#endif
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#ifdef CONFIG_MMU
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/*
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* I/O memory mapping functions.
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*/
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#define ioremap_prot ioremap_prot
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#define iounmap iounmap
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#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_NOCACHE)
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#define ioremap_cache(addr, size) \
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ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
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#endif /* CONFIG_MMU */
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#include <asm-generic/io.h>
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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int valid_phys_addr_range(phys_addr_t addr, size_t size);
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int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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#endif /* __ASM_SH_IO_H */
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