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1aba1eab0b
The older MIPS-based chips incorporated a memory controller with the revision A.0.0, update the binding to list that compatible. Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250729205213.3392481-2-florian.fainelli@broadcom.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
71 lines
2.1 KiB
YAML
71 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Memory controller (MEMC) for Broadcom STB
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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properties:
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compatible:
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oneOf:
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- description: Revision > 2.1 controllers
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items:
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- enum:
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- brcm,brcmstb-memc-ddr-rev-b.2.2
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- brcm,brcmstb-memc-ddr-rev-b.2.3
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- brcm,brcmstb-memc-ddr-rev-b.2.5
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- brcm,brcmstb-memc-ddr-rev-b.2.6
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- brcm,brcmstb-memc-ddr-rev-b.2.7
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- brcm,brcmstb-memc-ddr-rev-b.2.8
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- brcm,brcmstb-memc-ddr-rev-b.3.0
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- brcm,brcmstb-memc-ddr-rev-b.3.1
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- brcm,brcmstb-memc-ddr-rev-c.1.0
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- brcm,brcmstb-memc-ddr-rev-c.1.1
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- brcm,brcmstb-memc-ddr-rev-c.1.2
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- brcm,brcmstb-memc-ddr-rev-c.1.3
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- brcm,brcmstb-memc-ddr-rev-c.1.4
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- const: brcm,brcmstb-memc-ddr-rev-b.2.1
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- const: brcm,brcmstb-memc-ddr
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- description: Revision 2.1 controllers
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items:
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- const: brcm,brcmstb-memc-ddr-rev-b.2.1
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- const: brcm,brcmstb-memc-ddr
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- description: Revision 2.0 controllers
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items:
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- const: brcm,brcmstb-memc-ddr-rev-b.2.0
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- const: brcm,brcmstb-memc-ddr
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- description: Revision 1.x controllers
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items:
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- const: brcm,brcmstb-memc-ddr-rev-b.1.x
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- const: brcm,brcmstb-memc-ddr
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- description: Revision 0.x controllers
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items:
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- const: brcm,brcmstb-memc-ddr-rev-a.0.0
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- const: brcm,brcmstb-memc-ddr
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reg:
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maxItems: 1
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clock-frequency:
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description: DDR PHY frequency in Hz
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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memory-controller@9902000 {
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compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
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"brcm,brcmstb-memc-ddr-rev-b.2.1",
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"brcm,brcmstb-memc-ddr";
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reg = <0x9902000 0x600>;
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clock-frequency = <2133000000>;
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};
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