mirror of
git://git.yoctoproject.org/linux-yocto.git
synced 2025-07-05 05:15:23 +02:00
0c2f6d0461
Intel CPUs have a MSR bit to limit CPUID enumeration to leaf two. If
this bit is set by the BIOS then CPUID evaluation including topology
enumeration does not work correctly as the evaluation code does not try
to analyze any leaf greater than two.
This went unnoticed before because the original topology code just
repeated evaluation several times and managed to overwrite the initial
limited information with the correct one later. The new evaluation code
does it once and therefore ends up with the limited and wrong
information.
Cure this by unlocking CPUID right before evaluating anything which
depends on the maximum CPUID leaf being greater than two instead of
rereading stuff after unlock.
Fixes: 22d63660c3 ("x86/cpu: Use common topology code for Intel")
Reported-by: Peter Schneider <pschneider1968@googlemail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Peter Schneider <pschneider1968@googlemail.com>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/fd3f73dc-a86f-4bcf-9c60-43556a21eb42@googlemail.com
103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef ARCH_X86_CPU_H
|
|
#define ARCH_X86_CPU_H
|
|
|
|
#include <asm/cpu.h>
|
|
#include <asm/topology.h>
|
|
|
|
#include "topology.h"
|
|
|
|
/* attempt to consolidate cpu attributes */
|
|
struct cpu_dev {
|
|
const char *c_vendor;
|
|
|
|
/* some have two possibilities for cpuid string */
|
|
const char *c_ident[2];
|
|
|
|
void (*c_early_init)(struct cpuinfo_x86 *);
|
|
void (*c_bsp_init)(struct cpuinfo_x86 *);
|
|
void (*c_init)(struct cpuinfo_x86 *);
|
|
void (*c_identify)(struct cpuinfo_x86 *);
|
|
void (*c_detect_tlb)(struct cpuinfo_x86 *);
|
|
int c_x86_vendor;
|
|
#ifdef CONFIG_X86_32
|
|
/* Optional vendor specific routine to obtain the cache size. */
|
|
unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *,
|
|
unsigned int);
|
|
|
|
/* Family/stepping-based lookup table for model names. */
|
|
struct legacy_cpu_model_info {
|
|
int family;
|
|
const char *model_names[16];
|
|
} legacy_models[5];
|
|
#endif
|
|
};
|
|
|
|
struct _tlb_table {
|
|
unsigned char descriptor;
|
|
char tlb_type;
|
|
unsigned int entries;
|
|
/* unsigned int ways; */
|
|
char info[128];
|
|
};
|
|
|
|
#define cpu_dev_register(cpu_devX) \
|
|
static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
|
|
__section(".x86_cpu_dev.init") = \
|
|
&cpu_devX;
|
|
|
|
extern const struct cpu_dev *const __x86_cpu_dev_start[],
|
|
*const __x86_cpu_dev_end[];
|
|
|
|
#ifdef CONFIG_CPU_SUP_INTEL
|
|
enum tsx_ctrl_states {
|
|
TSX_CTRL_ENABLE,
|
|
TSX_CTRL_DISABLE,
|
|
TSX_CTRL_RTM_ALWAYS_ABORT,
|
|
TSX_CTRL_NOT_SUPPORTED,
|
|
};
|
|
|
|
extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
|
|
|
|
extern void __init tsx_init(void);
|
|
void tsx_ap_init(void);
|
|
void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c);
|
|
#else
|
|
static inline void tsx_init(void) { }
|
|
static inline void tsx_ap_init(void) { }
|
|
static inline void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) { }
|
|
#endif /* CONFIG_CPU_SUP_INTEL */
|
|
|
|
extern void init_spectral_chicken(struct cpuinfo_x86 *c);
|
|
|
|
extern void get_cpu_cap(struct cpuinfo_x86 *c);
|
|
extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
|
|
extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
|
|
extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
|
|
extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
|
|
extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
|
|
extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
|
|
|
|
extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
|
|
|
|
void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);
|
|
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);
|
|
|
|
unsigned int aperfmperf_get_khz(int cpu);
|
|
void cpu_select_mitigations(void);
|
|
|
|
extern void x86_spec_ctrl_setup_ap(void);
|
|
extern void update_srbds_msr(void);
|
|
extern void update_gds_msr(void);
|
|
|
|
extern enum spectre_v2_mitigation spectre_v2_enabled;
|
|
|
|
static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
|
|
{
|
|
return mode == SPECTRE_V2_EIBRS ||
|
|
mode == SPECTRE_V2_EIBRS_RETPOLINE ||
|
|
mode == SPECTRE_V2_EIBRS_LFENCE;
|
|
}
|
|
|
|
#endif /* ARCH_X86_CPU_H */
|