linux-yocto/include/dt-bindings
Stephen Boyd 8397c58ea7
Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next
- Add Mediatek MT8196 clk drivers

* clk-marvell:
  clk: mmp: pxa1908: Instantiate power driver through auxiliary bus

* clk-xilinx:
  clk: clocking-wizard: Fix output clock register offset for Versal platforms
  clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()

* clk-mediatek: (31 commits)
  clk: mediatek: Add MT8196 vencsys clock support
  clk: mediatek: Add MT8196 vdecsys clock support
  clk: mediatek: Add MT8196 ovl1 clock support
  clk: mediatek: Add MT8196 ovl0 clock support
  clk: mediatek: Add MT8196 disp-ao clock support
  clk: mediatek: Add MT8196 disp1 clock support
  clk: mediatek: Add MT8196 disp0 clock support
  clk: mediatek: Add MT8196 mfg clock support
  clk: mediatek: Add MT8196 mdpsys clock support
  clk: mediatek: Add MT8196 mcu clock support
  clk: mediatek: Add MT8196 I2C clock support
  clk: mediatek: Add MT8196 pextpsys clock support
  clk: mediatek: Add MT8196 ufssys clock support
  clk: mediatek: Add MT8196 peripheral clock support
  clk: mediatek: Add MT8196 vlpckgen clock support
  clk: mediatek: Add MT8196 topckgen2 clock support
  clk: mediatek: Add MT8196 topckgen clock support
  clk: mediatek: Add MT8196 apmixedsys clock support
  dt-bindings: clock: mediatek: Describe MT8196 clock controllers
  clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
  ...

* clk-loongson:
  clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
  clk: loongson2: Avoid hardcoding firmware name of the reference clock
  clk: loongson2: Allow zero divisors for dividers
  clk: loongson2: Support scale clocks with an alternative mode
  clk: loongson2: Allow specifying clock flags for gate clock
  dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
2025-10-06 13:00:22 -05:00
..
arm dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family 2025-07-16 22:53:26 -05:00
ata
bus
clock Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next 2025-10-06 13:00:22 -05:00
display
dma
firmware
gce
gpio
i2c
i3c
iio dt-bindings: iio: adc: mt6359: Add MT6373 PMIC AuxADC 2025-07-13 15:36:26 +01:00
input
interconnect dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller 2025-08-11 10:05:20 -05:00
interrupt-controller
leds
mailbox
media
memory dt-bindings: memory: tegra: Add Tegra264 support 2025-07-11 16:48:06 +02:00
mfd
mips
mux
net
nvmem
phy
pinctrl dt-bindings: pinctrl: renesas: Document RZ/T2H and RZ/N2H SoCs 2025-08-11 15:47:03 +02:00
pmu
power drm for 6.17-rc1 2025-07-30 19:26:49 -07:00
pwm
regulator soc: dt changes for 6.17 2025-07-29 11:04:52 -07:00
reset Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next 2025-10-06 13:00:22 -05:00
soc
sound USB/Thunderbolt changes for 6.16-rc1 2025-06-06 12:45:35 -07:00
spmi
thermal
usb
watchdog