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8f7e001e03
This fixes two issues: I truncated the warning's hart ID when porting to the 64-bit hart ID code, and the original code's warning handling could fire on an uninitialized hart ID. The biggest change here is that riscv_cbom_block_size is no longer initialized, as IMO the default isn't sane: there's nothing in the ISA that mandates any specific cache block size, so falling back to one will just silently produce the wrong answer on some systems. This also changes the probing order so the cache block size is known before enabling Zicbom support. CC: stable@vger.kernel.org CC: Andrew Jones <ajones@ventanamicro.com> CC: Heiko Stuebner <heiko@sntech.de> CC: Atish Patra <atishp@rivosinc.com> Fixes:3aefb2ee5b("riscv: implement Zicbom-based CMO instructions + the t-head variant") Fixes:1631ba1259("riscv: Add support for non-coherent devices using zicbom extension") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [Conor: fixed the redefinition errors] Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220912224800.998121-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CACHEFLUSH_H
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#define _ASM_RISCV_CACHEFLUSH_H
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#include <linux/mm.h>
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static inline void local_flush_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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#define PG_dcache_clean PG_arch_1
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static inline void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range(start, end) flush_icache_all()
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#define flush_icache_user_page(vma, pg, addr, len) \
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flush_icache_mm(vma->vm_mm, 0)
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#ifndef CONFIG_SMP
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#define flush_icache_all() local_flush_icache_all()
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#define flush_icache_mm(mm, local) flush_icache_all()
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#else /* CONFIG_SMP */
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void flush_icache_all(void);
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void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_RISCV_ISA_ZICBOM
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extern unsigned int riscv_cbom_block_size;
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void riscv_init_cbom_blocksize(void);
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#else
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static inline void riscv_init_cbom_blocksize(void) { }
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#endif
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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void riscv_noncoherent_supported(void);
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#endif
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/*
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* Bits in sys_riscv_flush_icache()'s flags argument.
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*/
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#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
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#define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
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#include <asm-generic/cacheflush.h>
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#endif /* _ASM_RISCV_CACHEFLUSH_H */
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