mirror of
git://git.yoctoproject.org/linux-yocto.git
synced 2025-10-22 15:03:53 +02:00
ad41ddeeac
pcie_read_tlp_log() handles only 4 Header Log DWORDs but TLP Prefix Log
(PCIe r6.1 secs 7.8.4.12 & 7.9.14.13) may also be present.
Generalize pcie_read_tlp_log() and struct pcie_tlp_log to also handle TLP
Prefix Log. The relevant registers are formatted identically in AER and DPC
Capability, but has these variations:
a) The offsets of TLP Prefix Log registers vary.
b) DPC RP PIO TLP Prefix Log register can be < 4 DWORDs.
c) AER TLP Prefix Log Present (PCIe r6.1 sec 7.8.4.7) can indicate Prefix
Log is not present.
Therefore callers must pass the offset of the TLP Prefix Log register and
the entire length to pcie_read_tlp_log() to be able to read the correct
number of TLP Prefix DWORDs from the correct offset.
Link: https://lore.kernel.org/r/20250114170840.1633-8-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
[bhelgaas: squash ternary fix from
https://lore.kernel.org/r/20250116172019.88116-1-colin.i.king@gmail.com]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (C) 2006 Intel Corp.
|
|
* Tom Long Nguyen (tom.l.nguyen@intel.com)
|
|
* Zhang Yanmin (yanmin.zhang@intel.com)
|
|
*/
|
|
|
|
#ifndef _AER_H_
|
|
#define _AER_H_
|
|
|
|
#include <linux/errno.h>
|
|
#include <linux/types.h>
|
|
|
|
#define AER_NONFATAL 0
|
|
#define AER_FATAL 1
|
|
#define AER_CORRECTABLE 2
|
|
#define DPC_FATAL 3
|
|
|
|
/*
|
|
* AER and DPC capabilities TLP Logging register sizes (PCIe r6.2, sec 7.8.4
|
|
* & 7.9.14).
|
|
*/
|
|
#define PCIE_STD_NUM_TLP_HEADERLOG 4
|
|
#define PCIE_STD_MAX_TLP_PREFIXLOG 4
|
|
|
|
struct pci_dev;
|
|
|
|
struct pcie_tlp_log {
|
|
u32 dw[PCIE_STD_NUM_TLP_HEADERLOG];
|
|
u32 prefix[PCIE_STD_MAX_TLP_PREFIXLOG];
|
|
};
|
|
|
|
struct aer_capability_regs {
|
|
u32 header;
|
|
u32 uncor_status;
|
|
u32 uncor_mask;
|
|
u32 uncor_severity;
|
|
u32 cor_status;
|
|
u32 cor_mask;
|
|
u32 cap_control;
|
|
struct pcie_tlp_log header_log;
|
|
u32 root_command;
|
|
u32 root_status;
|
|
u16 cor_err_source;
|
|
u16 uncor_err_source;
|
|
};
|
|
|
|
#if defined(CONFIG_PCIEAER)
|
|
int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
|
|
int pcie_aer_is_native(struct pci_dev *dev);
|
|
#else
|
|
static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
|
|
#endif
|
|
|
|
void pci_print_aer(struct pci_dev *dev, int aer_severity,
|
|
struct aer_capability_regs *aer);
|
|
int cper_severity_to_aer(int cper_severity);
|
|
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
|
|
int severity, struct aer_capability_regs *aer_regs);
|
|
#endif //_AER_H_
|
|
|