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e86c8186d0
Allow to disable ACPI PM Timer on suspend and enable on resume. A disabled timer helps optimise power consumption when the system is suspended. On resume the timer is only reactivated if it was activated prior to suspend, so unless the ACPI PM timer is enabled in the BIOS, this won't change anything. The ACPI PM timer is used by Intel's iTCO/wdat_wdt watchdog to drive the watchdog, so it doesn't need to run during suspend. Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20240812184208.1080710-1-mmaslanka@google.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
333 lines
8.8 KiB
C
333 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file contains platform specific structure definitions
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* and init function used by Alder Lake PCH.
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*
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* Copyright (c) 2022, Intel Corporation.
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* All Rights Reserved.
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*
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*/
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#include "core.h"
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/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
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const struct pmc_bit_map adl_pfear_map[] = {
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{"SPI/eSPI", BIT(2)},
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{"XHCI", BIT(3)},
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{"SPA", BIT(4)},
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{"SPB", BIT(5)},
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{"SPC", BIT(6)},
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{"GBE", BIT(7)},
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{"SATA", BIT(0)},
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{"HDA_PGD0", BIT(1)},
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{"HDA_PGD1", BIT(2)},
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{"HDA_PGD2", BIT(3)},
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{"HDA_PGD3", BIT(4)},
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{"SPD", BIT(5)},
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{"LPSS", BIT(6)},
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{"SMB", BIT(0)},
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{"ISH", BIT(1)},
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{"ITH", BIT(3)},
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{"XDCI", BIT(1)},
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{"DCI", BIT(2)},
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{"CSE", BIT(3)},
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{"CSME_KVM", BIT(4)},
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{"CSME_PMT", BIT(5)},
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{"CSME_CLINK", BIT(6)},
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{"CSME_PTIO", BIT(7)},
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{"CSME_USBR", BIT(0)},
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{"CSME_SUSRAM", BIT(1)},
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{"CSME_SMT1", BIT(2)},
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{"CSME_SMS2", BIT(4)},
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{"CSME_SMS1", BIT(5)},
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{"CSME_RTC", BIT(6)},
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{"CSME_PSF", BIT(7)},
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{"CNVI", BIT(3)},
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{"HDA_PGD4", BIT(2)},
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{"HDA_PGD5", BIT(3)},
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{"HDA_PGD6", BIT(4)},
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{}
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};
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const struct pmc_bit_map *ext_adl_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of cnp_reg_map for
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* a list of core SoCs using this.
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*/
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adl_pfear_map,
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NULL
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};
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const struct pmc_bit_map adl_ltr_show_map[] = {
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{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
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{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
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{"SATA", CNP_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
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{"XHCI", CNP_PMC_LTR_XHCI},
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{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
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{"ME", CNP_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"SATA1", CNP_PMC_LTR_EVA},
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{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
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{"HD_AUDIO", CNP_PMC_LTR_AZ},
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{"CNV", CNP_PMC_LTR_CNV},
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{"LPSS", CNP_PMC_LTR_LPSS},
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{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
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{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
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{"SATA2", CNP_PMC_LTR_CAM},
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{"ESPI", CNP_PMC_LTR_ESPI},
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{"SCC", CNP_PMC_LTR_SCC},
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{"ISH", CNP_PMC_LTR_ISH},
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{"UFSX2", CNP_PMC_LTR_UFSX2},
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{"EMMC", CNP_PMC_LTR_EMMC},
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/*
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* Check intel_pmc_core_ids[] users of cnp_reg_map for
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* a list of core SoCs using this.
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*/
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{"WIGIG", ICL_PMC_LTR_WIGIG},
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{"THC0", TGL_PMC_LTR_THC0},
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{"THC1", TGL_PMC_LTR_THC1},
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{"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
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/* Below two cannot be used for LTR_IGNORE */
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{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
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{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
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{}
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};
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const struct pmc_bit_map adl_clocksource_status_map[] = {
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{"CLKPART1_OFF_STS", BIT(0)},
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{"CLKPART2_OFF_STS", BIT(1)},
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{"CLKPART3_OFF_STS", BIT(2)},
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{"CLKPART4_OFF_STS", BIT(3)},
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{"CLKPART5_OFF_STS", BIT(4)},
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{"CLKPART6_OFF_STS", BIT(5)},
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{"CLKPART7_OFF_STS", BIT(6)},
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{"CLKPART8_OFF_STS", BIT(7)},
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{"PCIE0PLL_OFF_STS", BIT(10)},
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{"PCIE1PLL_OFF_STS", BIT(11)},
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{"PCIE2PLL_OFF_STS", BIT(12)},
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{"PCIE3PLL_OFF_STS", BIT(13)},
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{"PCIE4PLL_OFF_STS", BIT(14)},
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{"PCIE5PLL_OFF_STS", BIT(15)},
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{"PCIE6PLL_OFF_STS", BIT(16)},
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{"USB2PLL_OFF_STS", BIT(18)},
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{"OCPLL_OFF_STS", BIT(22)},
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{"AUDIOPLL_OFF_STS", BIT(23)},
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{"GBEPLL_OFF_STS", BIT(24)},
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{"Fast_XTAL_Osc_OFF_STS", BIT(25)},
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{"AC_Ring_Osc_OFF_STS", BIT(26)},
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{"MC_Ring_Osc_OFF_STS", BIT(27)},
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{"SATAPLL_OFF_STS", BIT(29)},
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{"USB3PLL_OFF_STS", BIT(31)},
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{}
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};
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const struct pmc_bit_map adl_power_gating_status_0_map[] = {
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{"PMC_PGD0_PG_STS", BIT(0)},
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{"DMI_PGD0_PG_STS", BIT(1)},
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{"ESPISPI_PGD0_PG_STS", BIT(2)},
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{"XHCI_PGD0_PG_STS", BIT(3)},
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{"SPA_PGD0_PG_STS", BIT(4)},
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{"SPB_PGD0_PG_STS", BIT(5)},
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{"SPC_PGD0_PG_STS", BIT(6)},
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{"GBE_PGD0_PG_STS", BIT(7)},
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{"SATA_PGD0_PG_STS", BIT(8)},
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{"DSP_PGD0_PG_STS", BIT(9)},
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{"DSP_PGD1_PG_STS", BIT(10)},
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{"DSP_PGD2_PG_STS", BIT(11)},
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{"DSP_PGD3_PG_STS", BIT(12)},
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{"SPD_PGD0_PG_STS", BIT(13)},
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{"LPSS_PGD0_PG_STS", BIT(14)},
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{"SMB_PGD0_PG_STS", BIT(16)},
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{"ISH_PGD0_PG_STS", BIT(17)},
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{"NPK_PGD0_PG_STS", BIT(19)},
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{"PECI_PGD0_PG_STS", BIT(21)},
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{"XDCI_PGD0_PG_STS", BIT(25)},
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{"EXI_PGD0_PG_STS", BIT(26)},
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{"CSE_PGD0_PG_STS", BIT(27)},
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{"KVMCC_PGD0_PG_STS", BIT(28)},
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{"PMT_PGD0_PG_STS", BIT(29)},
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{"CLINK_PGD0_PG_STS", BIT(30)},
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{"PTIO_PGD0_PG_STS", BIT(31)},
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{}
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};
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const struct pmc_bit_map adl_power_gating_status_1_map[] = {
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{"USBR0_PGD0_PG_STS", BIT(0)},
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{"SMT1_PGD0_PG_STS", BIT(2)},
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{"CSMERTC_PGD0_PG_STS", BIT(6)},
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{"CSMEPSF_PGD0_PG_STS", BIT(7)},
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{"CNVI_PGD0_PG_STS", BIT(19)},
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{"DSP_PGD4_PG_STS", BIT(26)},
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{"SPG_PGD0_PG_STS", BIT(27)},
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{"SPE_PGD0_PG_STS", BIT(28)},
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{}
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};
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const struct pmc_bit_map adl_power_gating_status_2_map[] = {
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{"THC0_PGD0_PG_STS", BIT(7)},
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{"THC1_PGD0_PG_STS", BIT(8)},
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{"SPF_PGD0_PG_STS", BIT(14)},
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{}
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};
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const struct pmc_bit_map adl_d3_status_0_map[] = {
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{"ISH_D3_STS", BIT(2)},
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{"LPSS_D3_STS", BIT(3)},
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{"XDCI_D3_STS", BIT(4)},
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{"XHCI_D3_STS", BIT(5)},
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{"SPA_D3_STS", BIT(12)},
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{"SPB_D3_STS", BIT(13)},
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{"SPC_D3_STS", BIT(14)},
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{"SPD_D3_STS", BIT(15)},
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{"SPE_D3_STS", BIT(16)},
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{"DSP_D3_STS", BIT(19)},
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{"SATA_D3_STS", BIT(20)},
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{"DMI_D3_STS", BIT(22)},
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{}
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};
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const struct pmc_bit_map adl_d3_status_1_map[] = {
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{"GBE_D3_STS", BIT(19)},
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{"CNVI_D3_STS", BIT(27)},
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{}
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};
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const struct pmc_bit_map adl_d3_status_2_map[] = {
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{"CSMERTC_D3_STS", BIT(1)},
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{"CSE_D3_STS", BIT(4)},
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{"KVMCC_D3_STS", BIT(5)},
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{"USBR0_D3_STS", BIT(6)},
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{"SMT1_D3_STS", BIT(8)},
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{"PTIO_D3_STS", BIT(16)},
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{"PMT_D3_STS", BIT(17)},
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{}
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};
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const struct pmc_bit_map adl_d3_status_3_map[] = {
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{"THC0_D3_STS", BIT(14)},
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{"THC1_D3_STS", BIT(15)},
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{}
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};
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const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
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{"ISH_VNN_REQ_STS", BIT(2)},
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{"ESPISPI_VNN_REQ_STS", BIT(18)},
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{"DSP_VNN_REQ_STS", BIT(19)},
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{}
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};
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const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
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{"NPK_VNN_REQ_STS", BIT(4)},
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{"EXI_VNN_REQ_STS", BIT(9)},
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{"GBE_VNN_REQ_STS", BIT(19)},
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{"SMB_VNN_REQ_STS", BIT(25)},
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{"CNVI_VNN_REQ_STS", BIT(27)},
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{}
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};
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const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
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{"CSMERTC_VNN_REQ_STS", BIT(1)},
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{"CSE_VNN_REQ_STS", BIT(4)},
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{"SMT1_VNN_REQ_STS", BIT(8)},
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{"CLINK_VNN_REQ_STS", BIT(14)},
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{"GPIOCOM4_VNN_REQ_STS", BIT(20)},
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{"GPIOCOM3_VNN_REQ_STS", BIT(21)},
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{"GPIOCOM2_VNN_REQ_STS", BIT(22)},
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{"GPIOCOM1_VNN_REQ_STS", BIT(23)},
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{"GPIOCOM0_VNN_REQ_STS", BIT(24)},
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{}
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};
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const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
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{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
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{}
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};
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const struct pmc_bit_map adl_vnn_misc_status_map[] = {
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{"CPU_C10_REQ_STS", BIT(0)},
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{"PCIe_LPM_En_REQ_STS", BIT(3)},
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{"ITH_REQ_STS", BIT(5)},
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{"CNVI_REQ_STS", BIT(6)},
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{"ISH_REQ_STS", BIT(7)},
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{"USB2_SUS_PG_Sys_REQ_STS", BIT(10)},
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{"PCIe_Clk_REQ_STS", BIT(12)},
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{"MPHY_Core_DL_REQ_STS", BIT(16)},
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{"Break-even_En_REQ_STS", BIT(17)},
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{"MPHY_SUS_REQ_STS", BIT(22)},
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{"xDCI_attached_REQ_STS", BIT(24)},
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{}
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};
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const struct pmc_bit_map *adl_lpm_maps[] = {
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adl_clocksource_status_map,
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adl_power_gating_status_0_map,
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adl_power_gating_status_1_map,
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adl_power_gating_status_2_map,
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adl_d3_status_0_map,
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adl_d3_status_1_map,
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adl_d3_status_2_map,
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adl_d3_status_3_map,
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adl_vnn_req_status_0_map,
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adl_vnn_req_status_1_map,
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adl_vnn_req_status_2_map,
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adl_vnn_req_status_3_map,
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adl_vnn_misc_status_map,
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tgl_signal_status_map,
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NULL
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};
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const struct pmc_reg_map adl_reg_map = {
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.pfear_sts = ext_adl_pfear_map,
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.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
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.ltr_show_sts = adl_ltr_show_map,
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.msr_sts = msr_map,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
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.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
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.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
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.lpm_num_modes = ADL_LPM_NUM_MODES,
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.lpm_num_maps = ADL_LPM_NUM_MAPS,
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.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
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.etr3_offset = ETR3_OFFSET,
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.lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET,
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.lpm_priority_offset = ADL_LPM_PRI_OFFSET,
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.lpm_en_offset = ADL_LPM_EN_OFFSET,
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.lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET,
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.lpm_sts = adl_lpm_maps,
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.lpm_status_offset = ADL_LPM_STATUS_OFFSET,
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.lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET,
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.pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,
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.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
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};
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int adl_core_init(struct pmc_dev *pmcdev)
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{
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struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
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int ret;
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pmcdev->suspend = cnl_suspend;
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pmcdev->resume = cnl_resume;
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pmc->map = &adl_reg_map;
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ret = get_primary_reg_base(pmc);
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if (ret)
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return ret;
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pmc_core_get_low_power_modes(pmcdev);
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return 0;
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}
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