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e86c8186d0
Allow to disable ACPI PM Timer on suspend and enable on resume. A disabled timer helps optimise power consumption when the system is suspended. On resume the timer is only reactivated if it was activated prior to suspend, so unless the ACPI PM timer is enabled in the BIOS, this won't change anything. The ACPI PM timer is used by Intel's iTCO/wdat_wdt watchdog to drive the watchdog, so it doesn't need to run during suspend. Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20240812184208.1080710-1-mmaslanka@google.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file contains platform specific structure definitions
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* and init function used by Ice Lake PCH.
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*
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* Copyright (c) 2022, Intel Corporation.
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* All Rights Reserved.
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*
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*/
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#include "core.h"
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const struct pmc_bit_map icl_pfear_map[] = {
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{"RES_65", BIT(0)},
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{"RES_66", BIT(1)},
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{"RES_67", BIT(2)},
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{"TAM", BIT(3)},
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{"GBETSN", BIT(4)},
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{"TBTLSX", BIT(5)},
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{"RES_71", BIT(6)},
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{"RES_72", BIT(7)},
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{}
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};
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const struct pmc_bit_map *ext_icl_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of icl_reg_map for
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* a list of core SoCs using this.
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*/
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cnp_pfear_map,
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icl_pfear_map,
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NULL
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};
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const struct pmc_reg_map icl_reg_map = {
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.pfear_sts = ext_icl_pfear_map,
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.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
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.slps0_dbg_maps = cnp_slps0_dbg_maps,
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.ltr_show_sts = cnp_ltr_show_map,
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.msr_sts = msr_map,
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.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET,
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.acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE,
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.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
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.etr3_offset = ETR3_OFFSET,
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};
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int icl_core_init(struct pmc_dev *pmcdev)
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{
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struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
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int ret;
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pmc->map = &icl_reg_map;
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ret = get_primary_reg_base(pmc);
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if (ret)
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return ret;
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pmc_core_get_low_power_modes(pmcdev);
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return ret;
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}
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