Nicholas Kazlauskas 9c553d00c5 drm/amd/display: Keep PHY active for DP displays on DCN31 ... [Why & How] Port of a change that went into DCN314 to keep the PHY enabled when we have a connected and active DP display. The PHY can hang if PHY refclk is disabled inadvertently. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Josip Pavic <josip.pavic@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-07-18 11:16:09 -04:00
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dcn31_clk_mgr.c	drm/amd/display: Keep PHY active for DP displays on DCN31	2023-07-18 11:16:09 -04:00
dcn31_clk_mgr.h	drm/amd/display: revert Blank eDP on disable/enable drv	2022-06-01 15:56:48 -04:00
dcn31_smu.c	drm/amd: Downgrade message about watermarks table after s0i3 to debug	2023-06-09 09:28:46 -04:00
dcn31_smu.h	drm/amd/display: support new PMFW interface to disable Z9 only	2022-01-18 17:41:19 -05:00